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//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2005, 2006, 2007 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 3.6.1
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// \ \ Application : MIG
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// / / Filename : s3adsp_ddr2_iobs_0.v
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// /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:41 $
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// \ \ / \ Date Created : Mon May 2 2005
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// \___\/\___\
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// Device : Spartan-3/3A/3A-DSP
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// Design Name : DDR2 SDRAM
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// Purpose : This module has the instantiations infrastructure_ios,
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// data_path_iobs and controller_iobs modules
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//*****************************************************************************
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`include "s3adsp_ddr2_parameters_0.v"
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`timescale 1ns/100ps
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(* X_CORE_INFO = "mig_v3_61_ddr2_sp3, Coregen 12.4" ,
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CORE_GENERATION_INFO = "ddr2_sp3,mig_v3_61,{component_name=ddr2_sp3, data_width=32, memory_width=8, clk_width=2, bank_address=2, row_address=13, column_address=10, no_of_cs=1, cke_width=1, registered=0, data_mask=1, mask_enable=1, load_mode_register=13'b0010100110011, ext_load_mode_register=13'b0000000000000, language=Verilog, synthesis_tool=ISE, interface_type=DDR2_SDRAM, no_of_controllers=1}" *)
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module s3adsp_ddr2_iobs_0
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(
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input clk,
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input clk90,
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input ddr_rasb_cntrl,
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input ddr_casb_cntrl,
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input ddr_web_cntrl,
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input ddr_cke_cntrl,
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input ddr_csb_cntrl,
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input ddr_odt_cntrl,
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input [(`ROW_ADDRESS-1):0] ddr_address_cntrl,
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input [(`BANK_ADDRESS-1):0] ddr_ba_cntrl,
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input rst_dqs_div_int,
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input dqs_reset,
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input dqs_enable,
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inout [((`DATA_STROBE_WIDTH)-1):0] ddr_dqs,
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inout [(`DATA_STROBE_WIDTH-1):0] ddr_dqs_n,
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inout [(`DATA_WIDTH-1):0] ddr_dq,
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input [(`DATA_WIDTH-1):0] write_data_falling,
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input [(`DATA_WIDTH-1):0] write_data_rising,
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input write_en_val,
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input [((`DATA_MASK_WIDTH)-1):0] data_mask_f,
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input [((`DATA_MASK_WIDTH)-1):0] data_mask_r,
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output [(`CLK_WIDTH-1):0] ddr2_ck,
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output [(`CLK_WIDTH-1):0] ddr2_ck_n,
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output ddr_rasb,
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output ddr_casb,
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output ddr_web,
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output [(`BANK_ADDRESS-1):0] ddr_ba,
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output [(`ROW_ADDRESS-1):0] ddr_address,
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output ddr_cke,
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output ddr_csb,
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output ddr_odt0,
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output rst_dqs_div,
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input rst_dqs_div_in,
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output rst_dqs_div_out,
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output [(`DATA_STROBE_WIDTH-1):0] dqs_int_delay_in,
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output [((`DATA_MASK_WIDTH)-1):0] ddr_dm,
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output [((`DATA_WIDTH)-1):0] dq
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);
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s3adsp_ddr2_infrastructure_iobs_0 infrastructure_iobs0
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(
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.ddr2_ck (ddr2_ck),
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.ddr2_ck_n (ddr2_ck_n),
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.clk0 (clk)
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);
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s3adsp_ddr2_controller_iobs_0 controller_iobs0
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(
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.clk0 (clk),
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.ddr_rasb_cntrl (ddr_rasb_cntrl),
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.ddr_casb_cntrl (ddr_casb_cntrl),
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.ddr_web_cntrl (ddr_web_cntrl),
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.ddr_cke_cntrl (ddr_cke_cntrl),
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.ddr_csb_cntrl (ddr_csb_cntrl),
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.ddr_odt_cntrl (ddr_odt_cntrl),
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.ddr_address_cntrl (ddr_address_cntrl),
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.ddr_ba_cntrl (ddr_ba_cntrl),
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.rst_dqs_div_int (rst_dqs_div_int),
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.ddr_rasb (ddr_rasb),
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.ddr_casb (ddr_casb),
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.ddr_web (ddr_web),
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.ddr_ba (ddr_ba),
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.ddr_address (ddr_address),
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.ddr_cke (ddr_cke),
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.ddr_csb (ddr_csb),
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.ddr_odt0 (ddr_odt0),
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.rst_dqs_div (rst_dqs_div),
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.rst_dqs_div_in (rst_dqs_div_in),
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.rst_dqs_div_out (rst_dqs_div_out)
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);
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s3adsp_ddr2_data_path_iobs_0 datapath_iobs0
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(
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.clk (clk),
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.clk90 (clk90),
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.dqs_reset (dqs_reset),
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.dqs_enable (dqs_enable),
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.ddr_dqs (ddr_dqs),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dq (ddr_dq),
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.write_data_falling (write_data_falling),
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.write_data_rising (write_data_rising),
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.write_en_val (write_en_val),
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.data_mask_f (data_mask_f),
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.data_mask_r (data_mask_r),
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.dqs_int_delay_in (dqs_int_delay_in),
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.ddr_dm (ddr_dm),
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.ddr_dq_val (dq)
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);
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endmodule
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