URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [rtl/] [verilog/] [xilinx_s3adsp_ddr2/] [s3adsp_ddr2_ram8d_0.v] - Blame information for rev 733

Go to most recent revision | Details | Compare with Previous | View Log


//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2005, 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : 3.6.1
//  \   \        Application        : MIG
//  /   /        Filename           : s3adsp_ddr2_ram8d_0.v
// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
// Device       : Spartan-3/3A/3A-DSP
// Design Name  : DDR2 SDRAM
// Purpose      : This module instantiates RAM16X1 premitives. There will be 
//                8 or 4 RAM16X1 instances depending on the number of data bits 
//                per strobe.
//*****************************************************************************
 
`timescale 1ns/100ps
`include "s3adsp_ddr2_parameters_0.v"
module s3adsp_ddr2_ram8d_0
  (
   output [(`DATABITSPERSTROBE -1):0] dout,
   input [3:0]                        waddr,
   input [(`DATABITSPERSTROBE -1):0]  din,
   input [3:0]                        raddr,
   input                              wclk0,
   input                              wclk1,
   input                              we
  );
 
 
   RAM16X1D fifo_bit0
     (
    .DPO (dout[0]),
    .A0(waddr[0]),
    .A1(waddr[1]),
    .A2(waddr[2]),
    .A3(waddr[3]),
    .D(din[0]),
    .DPRA0(raddr[0]),
    .DPRA1(raddr[1]),
    .DPRA2(raddr[2]),
    .DPRA3(raddr[3]),
    .SPO(),
    .WCLK(wclk1),
    .WE(we)
    );
 
   RAM16X1D fifo_bit1
     (
    .DPO (dout[1]),
    .A0(waddr[0]),
    .A1(waddr[1]),
    .A2(waddr[2]),
    .A3(waddr[3]),
    .D(din[1]),
    .DPRA0(raddr[0]),
    .DPRA1(raddr[1]),
    .DPRA2(raddr[2]),
    .DPRA3(raddr[3]),
    .SPO(),
    .WCLK(wclk0),
    .WE(we)
    );
 
 
   RAM16X1D fifo_bit2
     (
    .DPO (dout[2]),
    .A0(waddr[0]),
    .A1(waddr[1]),
    .A2(waddr[2]),
    .A3(waddr[3]),
    .D(din[2]),
    .DPRA0(raddr[0]),
    .DPRA1(raddr[1]),
    .DPRA2(raddr[2]),
    .DPRA3(raddr[3]),
    .SPO(),
    .WCLK(wclk1),
    .WE(we)
    );
 
   RAM16X1D fifo_bit3
     (
    .DPO (dout[3]),
    .A0(waddr[0]),
    .A1(waddr[1]),
    .A2(waddr[2]),
    .A3(waddr[3]),
    .D(din[3]),
    .DPRA0(raddr[0]),
    .DPRA1(raddr[1]),
    .DPRA2(raddr[2]),
    .DPRA3(raddr[3]),
    .SPO(),
    .WCLK(wclk0),
    .WE(we)
    );
 
   RAM16X1D fifo_bit4
     (
    .DPO (dout[4]),
    .A0(waddr[0]),
    .A1(waddr[1]),
    .A2(waddr[2]),
    .A3(waddr[3]),
    .D(din[4]),
    .DPRA0(raddr[0]),
    .DPRA1(raddr[1]),
    .DPRA2(raddr[2]),
    .DPRA3(raddr[3]),
    .SPO(),
    .WCLK(wclk1),
    .WE(we)
    );
 
   RAM16X1D fifo_bit5
     (
    .DPO (dout[5]),
    .A0(waddr[0]),
    .A1(waddr[1]),
    .A2(waddr[2]),
    .A3(waddr[3]),
    .D(din[5]),
    .DPRA0(raddr[0]),
    .DPRA1(raddr[1]),
    .DPRA2(raddr[2]),
    .DPRA3(raddr[3]),
    .SPO(),
    .WCLK(wclk0),
    .WE(we)
    );
 
   RAM16X1D fifo_bit6
     (
    .DPO (dout[6]),
    .A0(waddr[0]),
    .A1(waddr[1]),
    .A2(waddr[2]),
    .A3(waddr[3]),
    .D(din[6]),
    .DPRA0(raddr[0]),
    .DPRA1(raddr[1]),
    .DPRA2(raddr[2]),
    .DPRA3(raddr[3]),
    .SPO(),
    .WCLK(wclk1),
    .WE(we)
    );
 
   RAM16X1D fifo_bit7
     (
    .DPO (dout[7]),
    .A0(waddr[0]),
    .A1(waddr[1]),
    .A2(waddr[2]),
    .A3(waddr[3]),
    .D(din[7]),
    .DPRA0(raddr[0]),
    .DPRA1(raddr[1]),
    .DPRA2(raddr[2]),
    .DPRA3(raddr[3]),
    .SPO(),
    .WCLK(wclk0),
    .WE(we)
    );
 
 
 
 
 
  endmodule

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [rtl/] [verilog/] [xilinx_s3adsp_ddr2/] [s3adsp_ddr2_ram8d_0.v] - Blame information for rev 733

Line No.	Rev	Author	Line
1	568	julius	`//*****************************************************************************`
2			`// DISCLAIMER OF LIABILITY`
3			`//`
4			`// This file contains proprietary and confidential information of`
5			`// Xilinx, Inc. ("Xilinx"), that is distributed under a license`
6			`// from Xilinx, and may be used, copied and/or disclosed only`
7			`// pursuant to the terms of a valid license agreement with Xilinx.`
8			`//`
9			`// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION`
10			`// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER`
11			`// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT`
12			`// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,`
13			`// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx`
14			`// does not warrant that functions included in the Materials will`
15			`// meet the requirements of Licensee, or that the operation of the`
16			`// Materials will be uninterrupted or error-free, or that defects`
17			`// in the Materials will be corrected. Furthermore, Xilinx does`
18			`// not warrant or make any representations regarding use, or the`
19			`// results of the use, of the Materials in terms of correctness,`
20			`// accuracy, reliability or otherwise.`
21			`//`
22			`// Xilinx products are not designed or intended to be fail-safe,`
23			`// or for use in any application requiring fail-safe performance,`
24			`// such as life-support or safety devices or systems, Class III`
25			`// medical devices, nuclear facilities, applications related to`
26			`// the deployment of airbags, or any other applications that could`
27			`// lead to death, personal injury or severe property or`
28			`// environmental damage (individually and collectively, "critical`
29			`// applications"). Customer assumes the sole risk and liability`
30			`// of any use of Xilinx products in critical applications,`
31			`// subject only to applicable laws and regulations governing`
32			`// limitations on product liability.`
33			`//`
34			`// Copyright 2005, 2006, 2007 Xilinx, Inc.`
35			`// All rights reserved.`
36			`//`
37			`// This disclaimer and copyright notice must be retained as part`
38			`// of this file at all times.`
39			`//*****************************************************************************`
40			`// ____ ____`
41			`// / /\/ /`
42			`// /___/ \ / Vendor : Xilinx`
43			`// \ \ \/ Version : 3.6.1`
44			`// \ \ Application : MIG`
45			`// / / Filename : s3adsp_ddr2_ram8d_0.v`
46			`// /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $`
47			`// \ \ / \ Date Created : Mon May 2 2005`
48			`// \___\/\___\`
49			`// Device : Spartan-3/3A/3A-DSP`
50			`// Design Name : DDR2 SDRAM`
51			`// Purpose : This module instantiates RAM16X1 premitives. There will be`
52			`// 8 or 4 RAM16X1 instances depending on the number of data bits`
53			`// per strobe.`
54			`//*****************************************************************************`
55
56			`timescale 1ns/100ps
57			`include "s3adsp_ddr2_parameters_0.v"
58			`module s3adsp_ddr2_ram8d_0`
59			`(`
60			output [(`DATABITSPERSTROBE -1):0] dout,
61			`input [3:0] waddr,`
62			input [(`DATABITSPERSTROBE -1):0] din,
63			`input [3:0] raddr,`
64			`input wclk0,`
65			`input wclk1,`
66			`input we`
67			`);`
68
69
70			`RAM16X1D fifo_bit0`
71			`(`
72			`.DPO (dout[0]),`
73			`.A0(waddr[0]),`
74			`.A1(waddr[1]),`
75			`.A2(waddr[2]),`
76			`.A3(waddr[3]),`
77			`.D(din[0]),`
78			`.DPRA0(raddr[0]),`
79			`.DPRA1(raddr[1]),`
80			`.DPRA2(raddr[2]),`
81			`.DPRA3(raddr[3]),`
82			`.SPO(),`
83			`.WCLK(wclk1),`
84			`.WE(we)`
85			`);`
86
87			`RAM16X1D fifo_bit1`
88			`(`
89			`.DPO (dout[1]),`
90			`.A0(waddr[0]),`
91			`.A1(waddr[1]),`
92			`.A2(waddr[2]),`
93			`.A3(waddr[3]),`
94			`.D(din[1]),`
95			`.DPRA0(raddr[0]),`
96			`.DPRA1(raddr[1]),`
97			`.DPRA2(raddr[2]),`
98			`.DPRA3(raddr[3]),`
99			`.SPO(),`
100			`.WCLK(wclk0),`
101			`.WE(we)`
102			`);`
103
104
105			`RAM16X1D fifo_bit2`
106			`(`
107			`.DPO (dout[2]),`
108			`.A0(waddr[0]),`
109			`.A1(waddr[1]),`
110			`.A2(waddr[2]),`
111			`.A3(waddr[3]),`
112			`.D(din[2]),`
113			`.DPRA0(raddr[0]),`
114			`.DPRA1(raddr[1]),`
115			`.DPRA2(raddr[2]),`
116			`.DPRA3(raddr[3]),`
117			`.SPO(),`
118			`.WCLK(wclk1),`
119			`.WE(we)`
120			`);`
121
122			`RAM16X1D fifo_bit3`
123			`(`
124			`.DPO (dout[3]),`
125			`.A0(waddr[0]),`
126			`.A1(waddr[1]),`
127			`.A2(waddr[2]),`
128			`.A3(waddr[3]),`
129			`.D(din[3]),`
130			`.DPRA0(raddr[0]),`
131			`.DPRA1(raddr[1]),`
132			`.DPRA2(raddr[2]),`
133			`.DPRA3(raddr[3]),`
134			`.SPO(),`
135			`.WCLK(wclk0),`
136			`.WE(we)`
137			`);`
138
139			`RAM16X1D fifo_bit4`
140			`(`
141			`.DPO (dout[4]),`
142			`.A0(waddr[0]),`
143			`.A1(waddr[1]),`
144			`.A2(waddr[2]),`
145			`.A3(waddr[3]),`
146			`.D(din[4]),`
147			`.DPRA0(raddr[0]),`
148			`.DPRA1(raddr[1]),`
149			`.DPRA2(raddr[2]),`
150			`.DPRA3(raddr[3]),`
151			`.SPO(),`
152			`.WCLK(wclk1),`
153			`.WE(we)`
154			`);`
155
156			`RAM16X1D fifo_bit5`
157			`(`
158			`.DPO (dout[5]),`
159			`.A0(waddr[0]),`
160			`.A1(waddr[1]),`
161			`.A2(waddr[2]),`
162			`.A3(waddr[3]),`
163			`.D(din[5]),`
164			`.DPRA0(raddr[0]),`
165			`.DPRA1(raddr[1]),`
166			`.DPRA2(raddr[2]),`
167			`.DPRA3(raddr[3]),`
168			`.SPO(),`
169			`.WCLK(wclk0),`
170			`.WE(we)`
171			`);`
172
173			`RAM16X1D fifo_bit6`
174			`(`
175			`.DPO (dout[6]),`
176			`.A0(waddr[0]),`
177			`.A1(waddr[1]),`
178			`.A2(waddr[2]),`
179			`.A3(waddr[3]),`
180			`.D(din[6]),`
181			`.DPRA0(raddr[0]),`
182			`.DPRA1(raddr[1]),`
183			`.DPRA2(raddr[2]),`
184			`.DPRA3(raddr[3]),`
185			`.SPO(),`
186			`.WCLK(wclk1),`
187			`.WE(we)`
188			`);`
189
190			`RAM16X1D fifo_bit7`
191			`(`
192			`.DPO (dout[7]),`
193			`.A0(waddr[0]),`
194			`.A1(waddr[1]),`
195			`.A2(waddr[2]),`
196			`.A3(waddr[3]),`
197			`.D(din[7]),`
198			`.DPRA0(raddr[0]),`
199			`.DPRA1(raddr[1]),`
200			`.DPRA2(raddr[2]),`
201			`.DPRA3(raddr[3]),`
202			`.SPO(),`
203			`.WCLK(wclk0),`
204			`.WE(we)`
205			`);`
206
207
208
209
210
211			`endmodule`