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//*****************************************************************************

//   ____  ____

//  /   /\/   /

// /___/  \  /   Vendor             : Xilinx

// \   \   \/    Version            : 3.6.1

//  \   \        Application        : MIG

//  /   /        Filename           : s3adsp_ddr2_s3_dqs_iob.v

// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $

// \   \  /  \   Date Created       : Mon May 2 2005

//  \___\/\___\

// Device       : Spartan-3/3A/3A-DSP

// Design Name  : DDR2 SDRAM

// Purpose      : This module instantiates DDR IOB output flip-flops, an

//               output buffer with registered tri-state, and an input buffer

//               for a single strobe/dqs bit. The DDR IOB output flip-flops

//               are used to forward strobe to memory during a write. During

//               a read, the output of the IBUF is routed to the internal

//               delay module, dqs_delay.

//*****************************************************************************

`timescale 1ns/100ps

module s3adsp_ddr2_s3_dqs_iob

  (

   input            clk,

   input            ddr_dqs_reset,

   input            ddr_dqs_enable,

   inout            ddr_dqs,

   inout  ddr_dqs_n,

   output           dqs

   );

   localparam VCC = 1'b1;

   localparam GND = 1'b0;

   wire dqs_q;

   wire ddr_dqs_enable1;

   wire ddr_dqs_enable_b;

   wire data1;

   assign ddr_dqs_enable_b = ~ddr_dqs_enable;

   assign data1 = (ddr_dqs_reset == 1'b1) ? 1'b0 : 1'b1;

  (* IOB = "FORCE" *) FD  U1

      (

       .D(ddr_dqs_enable_b),

       .Q(ddr_dqs_enable1),

       .C(clk)

       )/* synthesis syn_useioff = 1 */;

   FDDRRSE U2 (

             .Q(dqs_q),

             .C0(clk),

             .C1(~clk),

             .CE(VCC),

             .D0(data1),

             .D1(GND),

             .R(GND),

             .S(GND)

             );

//***********************************************************************

//IO buffer for dqs signal. Allows for distribution of dqsto the data(DQ) loads.

//***********************************************************************

  OBUFTDS  U3  (

            .I(dqs_q),

            .T(ddr_dqs_enable1),

            .O(ddr_dqs),

            .OB(ddr_dqs_n)

            );

   IBUFDS  U4 (

                   .I(ddr_dqs),

                   .IB(ddr_dqs_n),

                   .O(dqs)

                   );

     endmodule