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//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2005, 2006, 2007 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /   Vendor             : Xilinx
// \   \   \/    Version            : 3.6.1
//  \   \        Application        : MIG
//  /   /        Filename           : s3adsp_ddr2_tap_dly.v
// /___/   /\    Date Last Modified : $Date: 2010/11/26 18:25:42 $
// \   \  /  \   Date Created       : Mon May 2 2005
//  \___\/\___\
// Device       : Spartan-3/3A/3A-DSP
// Design Name  : DDR2 SDRAM
// Purpose      : Internal dqs delay structure for ddr sdram controller
//*****************************************************************************
 
  `timescale 1ns/100ps
module s3adsp_ddr2_tap_dly
  (
   input         clk,
   input         reset,
   input         tapin,
   output [31:0] flop2
   );
 
   wire [31:0]   tap/* synthesis syn_keep=1 */;
   wire [31:0]   flop1/* synthesis syn_keep=1 */;
   wire          high;
   reg           reset_r;
 
   always @( posedge clk )
     reset_r <= reset;
 
   assign        high = 1'b1;
 
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l0
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tapin),
         .O(tap[0])
         );
 
   LUT4 #
     (
      .INIT (16'h4000)
      )
     l1
       (
         .I0(tap[0]),
         .I1(high),
         .I2(high),
         .I3(high),
         .O(tap[1])
         );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l2
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[1]),
         .O(tap[2])
         );
 
   LUT4 #
     (
      .INIT (16'h0800)
      )
     l3
       (
        .I0(high),
        .I1(high),
        .I2(tap[2]),
        .I3(high),
        .O(tap[3])
        );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l4
       ( .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[3]),
         .O(tap[4])
         );
 
   LUT4 #
     (
      .INIT (16'h0800)
      )
     l5
       (
         .I0(high),
         .I1(high),
         .I2(tap[4]),
         .I3(high),
         .O(tap[5])
         );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l6
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[5]),
         .O(tap[6])
         );
 
   LUT4 #
     (
      .INIT (16'h4000)
      )
     l7
       (
        .I0(tap[6]),
        .I1(high),
        .I2(high),
        .I3(high),
        .O(tap[7])
        );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l8
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[7]),
         .O(tap[8])
         );
 
   LUT4 #
     (
      .INIT (16'h4000)
      )
     l9
       (
         .I0(tap[8]),
         .I1(high),
         .I2(high),
         .I3(high),
         .O(tap[9])
         );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l10
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[9]),
         .O(tap[10])
         );
 
   LUT4 #
     (
      .INIT (16'h0800)
      )
     l11
       (
         .I0(high),
         .I1(high),
         .I2(tap[10]),
         .I3(high),
         .O(tap[11])
         );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l12
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[11]),
         .O(tap[12])
         );
 
   LUT4 #
     (
      .INIT (16'h0800)
      )
     l13
       (
         .I0(high),
         .I1(high),
         .I2(tap[12]),
         .I3(high),
         .O(tap[13])
         );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l14
       (
        .I0(high),
        .I1(high),
        .I2(high),
        .I3(tap[13]),
        .O(tap[14])
        );
 
   LUT4 #
     (
      .INIT (16'h4000)
      )
     l15
       (
         .I0(tap[14]),
         .I1(high),
         .I2(high),
         .I3(high),
         .O(tap[15])
         );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l16
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[15]),
         .O(tap[16])
         );
 
   LUT4 #
     (
      .INIT (16'h0800)
      )
     l17
       (
         .I0(high),
         .I1(high),
         .I2(tap[16]),
         .I3(high),
         .O(tap[17])
         );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l18
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[17]),
         .O(tap[18])
         );
 
   LUT4 #
     (
      .INIT (16'h0800)
      )
     l19
       (
        .I0(high),
        .I1(high),
        .I2(tap[18]),
        .I3(high),
        .O(tap[19])
        );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l20
       (
        .I0(high),
        .I1(high),
        .I2(high),
        .I3(tap[19]),
        .O(tap[20])
        );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l21
       (
        .I0(high),
        .I1(high),
        .I2(high),
        .I3(tap[20]),
        .O(tap[21])
        );
 
   LUT4 #
     (
      .INIT (16'h4000)
      )
     l22
       (
         .I0(tap[21]),
         .I1(high),
         .I2(high),
         .I3(high),
         .O(tap[22])
         );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l23
       (
        .I0(high),
        .I1(high),
        .I2(high),
        .I3(tap[22]),
        .O(tap[23])
        );
 
   LUT4 #
     (
      .INIT (16'h0800)
      )
     l24
       (
         .I0(high),
         .I1(high),
         .I2(tap[23]),
         .I3(high),
         .O(tap[24])
         );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l25
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[24]),
         .O(tap[25])
         );
 
   LUT4 #
     (
      .INIT (16'h0800)
      )
     l26
       (
        .I0(high),
        .I1(high),
        .I2(tap[25]),
        .I3(high),
        .O(tap[26])
        );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l27
       (
        .I0(high),
        .I1(high),
        .I2(high),
        .I3(tap[26]),
        .O(tap[27])
        );
 
   LUT4 #
     (
      .INIT (16'h4000)
      )
     l28
       (
        .I0(tap[27]),
        .I1(high),
        .I2(high),
        .I3(high),
        .O(tap[28])
        );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l29
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[28]),
         .O(tap[29])
         );
 
   LUT4 #
     (
      .INIT (16'h4000)
      )
     l30
       (
        .I0(tap[29]),
        .I1(high),
        .I2(high),
        .I3(high),
        .O(tap[30])
        );
 
   LUT4 #
     (
      .INIT (16'h0080)
      )
     l31
       (
         .I0(high),
         .I1(high),
         .I2(high),
         .I3(tap[30]),
         .O(tap[31])
         );
 
  genvar tap_i;
   generate for(tap_i = 0; tap_i < 32;  tap_i = tap_i + 1) begin: gen_tap1
      FDR r
        (
         .Q (flop1[tap_i]),
         .C (clk),
         .D (tap[tap_i]),
         .R (reset_r)
         );
   end
   endgenerate
 
   genvar tap1_i;
   generate for(tap1_i = 0; tap1_i < 31;  tap1_i = tap1_i + 1) begin: gen_tap2
      FDR u
        (
         .Q (flop2[tap1_i]),
         .C (clk),
         .D (flop1[tap1_i] ~^ flop1[tap1_i + 1]),
         .R (reset_r)
         );
   end
   endgenerate
 
   FDR u31
     (
      .Q (flop2[31]),
      .C (clk),
      .D (flop1[31]),
      .R (reset_r)
      );
 
endmodule

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [rtl/] [verilog/] [xilinx_s3adsp_ddr2/] [s3adsp_ddr2_tap_dly.v] - Blame information for rev 724

Line No.	Rev	Author	Line
1	568	julius	`//*****************************************************************************`
2			`// DISCLAIMER OF LIABILITY`
3			`//`
4			`// This file contains proprietary and confidential information of`
5			`// Xilinx, Inc. ("Xilinx"), that is distributed under a license`
6			`// from Xilinx, and may be used, copied and/or disclosed only`
7			`// pursuant to the terms of a valid license agreement with Xilinx.`
8			`//`
9			`// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION`
10			`// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER`
11			`// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT`
12			`// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,`
13			`// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx`
14			`// does not warrant that functions included in the Materials will`
15			`// meet the requirements of Licensee, or that the operation of the`
16			`// Materials will be uninterrupted or error-free, or that defects`
17			`// in the Materials will be corrected. Furthermore, Xilinx does`
18			`// not warrant or make any representations regarding use, or the`
19			`// results of the use, of the Materials in terms of correctness,`
20			`// accuracy, reliability or otherwise.`
21			`//`
22			`// Xilinx products are not designed or intended to be fail-safe,`
23			`// or for use in any application requiring fail-safe performance,`
24			`// such as life-support or safety devices or systems, Class III`
25			`// medical devices, nuclear facilities, applications related to`
26			`// the deployment of airbags, or any other applications that could`
27			`// lead to death, personal injury or severe property or`
28			`// environmental damage (individually and collectively, "critical`
29			`// applications"). Customer assumes the sole risk and liability`
30			`// of any use of Xilinx products in critical applications,`
31			`// subject only to applicable laws and regulations governing`
32			`// limitations on product liability.`
33			`//`
34			`// Copyright 2005, 2006, 2007 Xilinx, Inc.`
35			`// All rights reserved.`
36			`//`
37			`// This disclaimer and copyright notice must be retained as part`
38			`// of this file at all times.`
39			`//*****************************************************************************`
40			`// ____ ____`
41			`// / /\/ /`
42			`// /___/ \ / Vendor : Xilinx`
43			`// \ \ \/ Version : 3.6.1`
44			`// \ \ Application : MIG`
45			`// / / Filename : s3adsp_ddr2_tap_dly.v`
46			`// /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $`
47			`// \ \ / \ Date Created : Mon May 2 2005`
48			`// \___\/\___\`
49			`// Device : Spartan-3/3A/3A-DSP`
50			`// Design Name : DDR2 SDRAM`
51			`// Purpose : Internal dqs delay structure for ddr sdram controller`
52			`//*****************************************************************************`
53
54			`timescale 1ns/100ps
55			`module s3adsp_ddr2_tap_dly`
56			`(`
57			`input clk,`
58			`input reset,`
59			`input tapin,`
60			`output [31:0] flop2`
61			`);`
62
63			`wire [31:0] tap/* synthesis syn_keep=1 */;`
64			`wire [31:0] flop1/* synthesis syn_keep=1 */;`
65			`wire high;`
66			`reg reset_r;`
67
68			`always @( posedge clk )`
69			`reset_r <= reset;`
70
71			`assign high = 1'b1;`
72
73
74			`LUT4 #`
75			`(`
76			`.INIT (16'h0080)`
77			`)`
78			`l0`
79			`(`
80			`.I0(high),`
81			`.I1(high),`
82			`.I2(high),`
83			`.I3(tapin),`
84			`.O(tap[0])`
85			`);`
86
87			`LUT4 #`
88			`(`
89			`.INIT (16'h4000)`
90			`)`
91			`l1`
92			`(`
93			`.I0(tap[0]),`
94			`.I1(high),`
95			`.I2(high),`
96			`.I3(high),`
97			`.O(tap[1])`
98			`);`
99
100			`LUT4 #`
101			`(`
102			`.INIT (16'h0080)`
103			`)`
104			`l2`
105			`(`
106			`.I0(high),`
107			`.I1(high),`
108			`.I2(high),`
109			`.I3(tap[1]),`
110			`.O(tap[2])`
111			`);`
112
113			`LUT4 #`
114			`(`
115			`.INIT (16'h0800)`
116			`)`
117			`l3`
118			`(`
119			`.I0(high),`
120			`.I1(high),`
121			`.I2(tap[2]),`
122			`.I3(high),`
123			`.O(tap[3])`
124			`);`
125
126			`LUT4 #`
127			`(`
128			`.INIT (16'h0080)`
129			`)`
130			`l4`
131			`( .I0(high),`
132			`.I1(high),`
133			`.I2(high),`
134			`.I3(tap[3]),`
135			`.O(tap[4])`
136			`);`
137
138			`LUT4 #`
139			`(`
140			`.INIT (16'h0800)`
141			`)`
142			`l5`
143			`(`
144			`.I0(high),`
145			`.I1(high),`
146			`.I2(tap[4]),`
147			`.I3(high),`
148			`.O(tap[5])`
149			`);`
150
151			`LUT4 #`
152			`(`
153			`.INIT (16'h0080)`
154			`)`
155			`l6`
156			`(`
157			`.I0(high),`
158			`.I1(high),`
159			`.I2(high),`
160			`.I3(tap[5]),`
161			`.O(tap[6])`
162			`);`
163
164			`LUT4 #`
165			`(`
166			`.INIT (16'h4000)`
167			`)`
168			`l7`
169			`(`
170			`.I0(tap[6]),`
171			`.I1(high),`
172			`.I2(high),`
173			`.I3(high),`
174			`.O(tap[7])`
175			`);`
176
177			`LUT4 #`
178			`(`
179			`.INIT (16'h0080)`
180			`)`
181			`l8`
182			`(`
183			`.I0(high),`
184			`.I1(high),`
185			`.I2(high),`
186			`.I3(tap[7]),`
187			`.O(tap[8])`
188			`);`
189
190			`LUT4 #`
191			`(`
192			`.INIT (16'h4000)`
193			`)`
194			`l9`
195			`(`
196			`.I0(tap[8]),`
197			`.I1(high),`
198			`.I2(high),`
199			`.I3(high),`
200			`.O(tap[9])`
201			`);`
202
203			`LUT4 #`
204			`(`
205			`.INIT (16'h0080)`
206			`)`
207			`l10`
208			`(`
209			`.I0(high),`
210			`.I1(high),`
211			`.I2(high),`
212			`.I3(tap[9]),`
213			`.O(tap[10])`
214			`);`
215
216			`LUT4 #`
217			`(`
218			`.INIT (16'h0800)`
219			`)`
220			`l11`
221			`(`
222			`.I0(high),`
223			`.I1(high),`
224			`.I2(tap[10]),`
225			`.I3(high),`
226			`.O(tap[11])`
227			`);`
228
229			`LUT4 #`
230			`(`
231			`.INIT (16'h0080)`
232			`)`
233			`l12`
234			`(`
235			`.I0(high),`
236			`.I1(high),`
237			`.I2(high),`
238			`.I3(tap[11]),`
239			`.O(tap[12])`
240			`);`
241
242			`LUT4 #`
243			`(`
244			`.INIT (16'h0800)`
245			`)`
246			`l13`
247			`(`
248			`.I0(high),`
249			`.I1(high),`
250			`.I2(tap[12]),`
251			`.I3(high),`
252			`.O(tap[13])`
253			`);`
254
255			`LUT4 #`
256			`(`
257			`.INIT (16'h0080)`
258			`)`
259			`l14`
260			`(`
261			`.I0(high),`
262			`.I1(high),`
263			`.I2(high),`
264			`.I3(tap[13]),`
265			`.O(tap[14])`
266			`);`
267
268			`LUT4 #`
269			`(`
270			`.INIT (16'h4000)`
271			`)`
272			`l15`
273			`(`
274			`.I0(tap[14]),`
275			`.I1(high),`
276			`.I2(high),`
277			`.I3(high),`
278			`.O(tap[15])`
279			`);`
280
281			`LUT4 #`
282			`(`
283			`.INIT (16'h0080)`
284			`)`
285			`l16`
286			`(`
287			`.I0(high),`
288			`.I1(high),`
289			`.I2(high),`
290			`.I3(tap[15]),`
291			`.O(tap[16])`
292			`);`
293
294			`LUT4 #`
295			`(`
296			`.INIT (16'h0800)`
297			`)`
298			`l17`
299			`(`
300			`.I0(high),`
301			`.I1(high),`
302			`.I2(tap[16]),`
303			`.I3(high),`
304			`.O(tap[17])`
305			`);`
306
307			`LUT4 #`
308			`(`
309			`.INIT (16'h0080)`
310			`)`
311			`l18`
312			`(`
313			`.I0(high),`
314			`.I1(high),`
315			`.I2(high),`
316			`.I3(tap[17]),`
317			`.O(tap[18])`
318			`);`
319
320			`LUT4 #`
321			`(`
322			`.INIT (16'h0800)`
323			`)`
324			`l19`
325			`(`
326			`.I0(high),`
327			`.I1(high),`
328			`.I2(tap[18]),`
329			`.I3(high),`
330			`.O(tap[19])`
331			`);`
332
333			`LUT4 #`
334			`(`
335			`.INIT (16'h0080)`
336			`)`
337			`l20`
338			`(`
339			`.I0(high),`
340			`.I1(high),`
341			`.I2(high),`
342			`.I3(tap[19]),`
343			`.O(tap[20])`
344			`);`
345
346			`LUT4 #`
347			`(`
348			`.INIT (16'h0080)`
349			`)`
350			`l21`
351			`(`
352			`.I0(high),`
353			`.I1(high),`
354			`.I2(high),`
355			`.I3(tap[20]),`
356			`.O(tap[21])`
357			`);`
358
359			`LUT4 #`
360			`(`
361			`.INIT (16'h4000)`
362			`)`
363			`l22`
364			`(`
365			`.I0(tap[21]),`
366			`.I1(high),`
367			`.I2(high),`
368			`.I3(high),`
369			`.O(tap[22])`
370			`);`
371
372			`LUT4 #`
373			`(`
374			`.INIT (16'h0080)`
375			`)`
376			`l23`
377			`(`
378			`.I0(high),`
379			`.I1(high),`
380			`.I2(high),`
381			`.I3(tap[22]),`
382			`.O(tap[23])`
383			`);`
384
385			`LUT4 #`
386			`(`
387			`.INIT (16'h0800)`
388			`)`
389			`l24`
390			`(`
391			`.I0(high),`
392			`.I1(high),`
393			`.I2(tap[23]),`
394			`.I3(high),`
395			`.O(tap[24])`
396			`);`
397
398			`LUT4 #`
399			`(`
400			`.INIT (16'h0080)`
401			`)`
402			`l25`
403			`(`
404			`.I0(high),`
405			`.I1(high),`
406			`.I2(high),`
407			`.I3(tap[24]),`
408			`.O(tap[25])`
409			`);`
410
411			`LUT4 #`
412			`(`
413			`.INIT (16'h0800)`
414			`)`
415			`l26`
416			`(`
417			`.I0(high),`
418			`.I1(high),`
419			`.I2(tap[25]),`
420			`.I3(high),`
421			`.O(tap[26])`
422			`);`
423
424			`LUT4 #`
425			`(`
426			`.INIT (16'h0080)`
427			`)`
428			`l27`
429			`(`
430			`.I0(high),`
431			`.I1(high),`
432			`.I2(high),`
433			`.I3(tap[26]),`
434			`.O(tap[27])`
435			`);`
436
437			`LUT4 #`
438			`(`
439			`.INIT (16'h4000)`
440			`)`
441			`l28`
442			`(`
443			`.I0(tap[27]),`
444			`.I1(high),`
445			`.I2(high),`
446			`.I3(high),`
447			`.O(tap[28])`
448			`);`
449
450			`LUT4 #`
451			`(`
452			`.INIT (16'h0080)`
453			`)`
454			`l29`
455			`(`
456			`.I0(high),`
457			`.I1(high),`
458			`.I2(high),`
459			`.I3(tap[28]),`
460			`.O(tap[29])`
461			`);`
462
463			`LUT4 #`
464			`(`
465			`.INIT (16'h4000)`
466			`)`
467			`l30`
468			`(`
469			`.I0(tap[29]),`
470			`.I1(high),`
471			`.I2(high),`
472			`.I3(high),`
473			`.O(tap[30])`
474			`);`
475
476			`LUT4 #`
477			`(`
478			`.INIT (16'h0080)`
479			`)`
480			`l31`
481			`(`
482			`.I0(high),`
483			`.I1(high),`
484			`.I2(high),`
485			`.I3(tap[30]),`
486			`.O(tap[31])`
487			`);`
488
489			`genvar tap_i;`
490			`generate for(tap_i = 0; tap_i < 32; tap_i = tap_i + 1) begin: gen_tap1`
491			`FDR r`
492			`(`
493			`.Q (flop1[tap_i]),`
494			`.C (clk),`
495			`.D (tap[tap_i]),`
496			`.R (reset_r)`
497			`);`
498			`end`
499			`endgenerate`
500
501			`genvar tap1_i;`
502			`generate for(tap1_i = 0; tap1_i < 31; tap1_i = tap1_i + 1) begin: gen_tap2`
503			`FDR u`
504			`(`
505			`.Q (flop2[tap1_i]),`
506			`.C (clk),`
507			`.D (flop1[tap1_i] ~^ flop1[tap1_i + 1]),`
508			`.R (reset_r)`
509			`);`
510			`end`
511			`endgenerate`
512
513			`FDR u31`
514			`(`
515			`.Q (flop2[31]),`
516			`.C (clk),`
517			`.D (flop1[31]),`
518			`.R (reset_r)`
519			`);`
520
521			`endmodule`