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//*****************************************************************************
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// DISCLAIMER OF LIABILITY
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//
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// This file contains proprietary and confidential information of
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// Xilinx, Inc. ("Xilinx"), that is distributed under a license
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// from Xilinx, and may be used, copied and/or disclosed only
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// pursuant to the terms of a valid license agreement with Xilinx.
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//
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// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
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// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
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// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
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// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
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// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
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// does not warrant that functions included in the Materials will
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// meet the requirements of Licensee, or that the operation of the
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// Materials will be uninterrupted or error-free, or that defects
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// in the Materials will be corrected. Furthermore, Xilinx does
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// not warrant or make any representations regarding use, or the
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// results of the use, of the Materials in terms of correctness,
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// accuracy, reliability or otherwise.
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//
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// Xilinx products are not designed or intended to be fail-safe,
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// or for use in any application requiring fail-safe performance,
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// such as life-support or safety devices or systems, Class III
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// medical devices, nuclear facilities, applications related to
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// the deployment of airbags, or any other applications that could
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// lead to death, personal injury or severe property or
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// environmental damage (individually and collectively, "critical
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// applications"). Customer assumes the sole risk and liability
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// of any use of Xilinx products in critical applications,
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// subject only to applicable laws and regulations governing
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// limitations on product liability.
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//
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// Copyright 2005, 2006, 2007, 2008 Xilinx, Inc.
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// All rights reserved.
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//
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// This disclaimer and copyright notice must be retained as part
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// of this file at all times.
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//*****************************************************************************
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// ____ ____
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// / /\/ /
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// /___/ \ / Vendor : Xilinx
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// \ \ \/ Version : 3.6.1
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// \ \ Application : MIG
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// / / Filename : s3adsp_ddr2_top_0.v
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// /___/ /\ Date Last Modified : $Date: 2010/11/26 18:25:42 $
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// \ \ / \ Date Created : Mon May 2 2005
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// \___\/\___\
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// Device : Spartan-3/3A/3A-DSP
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// Design Name : DDR2 SDRAM
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// Purpose : This modules has the instantiations infrastructure, iobs,
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// controller and data_paths modules
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//*****************************************************************************
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`timescale 1ns/100ps
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`include "s3adsp_ddr2_parameters_0.v"
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module s3adsp_ddr2_top_0
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(
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input rst_dqs_div_in,
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output rst_dqs_div_out,
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input clk_int,
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input clk90_int,
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input [4:0] delay_sel_val,
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input sys_rst,
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input sys_rst90,
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input sys_rst180,
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input [((`DATA_WIDTH*2)-1):0] user_input_data,
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output [((`DATA_WIDTH*2)-1):0] user_output_data,
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output user_data_valid,
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input [((`ROW_ADDRESS +
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`COLUMN_ADDRESS + `BANK_ADDRESS)-1):0] user_input_address,
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input [2:0] user_command_register,
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output user_cmd_ack,
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input burst_done,
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output init_done,
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output ar_done,
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inout [((`DATA_STROBE_WIDTH)-1):0] ddr2_dqs,
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inout [(`DATA_WIDTH-1):0] ddr2_dq,
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output ddr2_cke,
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output ddr2_cs_n,
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output auto_ref_req,
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input wait_200us,
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output ddr2_ras_n,
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output ddr2_cas_n,
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output ddr2_we_n,
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output ddr2_odt,
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output [`BANK_ADDRESS-1:0] ddr2_ba,
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output [`ROW_ADDRESS-1:0] ddr2_a,
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output [(`CLK_WIDTH-1):0] ddr2_ck,
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input [((`DATA_MASK_WIDTH*2)-1):0] user_data_mask,
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output [((`DATA_MASK_WIDTH)-1):0] ddr2_dm,
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inout [(`DATA_STROBE_WIDTH-1):0] ddr2_dqs_n,
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output clk_tb,
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output clk90_tb,
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output sys_rst_tb,
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output sys_rst90_tb,
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output sys_rst180_tb,
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output [(`CLK_WIDTH-1):0] ddr2_ck_n,
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//debug_signals
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output [4:0] dbg_delay_sel,
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output dbg_rst_calib,
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input [4:0] vio_out_dqs,
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input vio_out_dqs_en,
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input [4:0] vio_out_rst_dqs_div,
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input vio_out_rst_dqs_div_en
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);
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wire rst_calib;
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wire [4:0] delay_sel;
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wire write_enable;
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wire dqs_div_rst;
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wire dqs_enable;
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wire dqs_reset;
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wire [(`DATA_WIDTH-1):0] dq;
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wire write_en_val;
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wire [((`DATA_MASK_WIDTH)-1):0] data_mask_f;
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wire [((`DATA_MASK_WIDTH)-1):0] data_mask_r;
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wire [(`DATA_WIDTH-1):0] write_data_falling;
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wire [(`DATA_WIDTH-1):0] write_data_rising;
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wire ddr_rasb_cntrl;
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wire ddr_casb_cntrl;
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wire ddr_web_cntrl;
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wire [`BANK_ADDRESS-1:0] ddr_ba_cntrl;
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wire [`ROW_ADDRESS-1:0] ddr_address_cntrl;
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wire ddr_cke_cntrl;
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wire ddr_csb_cntrl;
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wire ddr_odt_cntrl;
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wire rst_dqs_div_int;
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wire [(`DATA_STROBE_WIDTH-1):0] dqs_int_delay_in;
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assign clk_tb = clk_int;
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assign clk90_tb = clk90_int;
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assign sys_rst_tb = sys_rst;
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assign sys_rst90_tb = sys_rst90;
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assign sys_rst180_tb = sys_rst180;
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s3adsp_ddr2_controller_0 controller0
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(
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.auto_ref_req (auto_ref_req),
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.wait_200us(wait_200us),
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.clk (clk_int),
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.rst0 (sys_rst),
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.rst180 (sys_rst180),
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.address (user_input_address[((`ROW_ADDRESS +
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`COLUMN_ADDRESS +
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`BANK_ADDRESS)-1):
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`BANK_ADDRESS]),
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.bank_address (user_input_address[(`BANK_ADDRESS-1): 0]),
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.command_register (user_command_register),
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.burst_done (burst_done),
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.ddr_rasb_cntrl (ddr_rasb_cntrl),
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.ddr_casb_cntrl (ddr_casb_cntrl),
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.ddr_web_cntrl (ddr_web_cntrl),
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.ddr_ba_cntrl (ddr_ba_cntrl),
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.ddr_address_cntrl (ddr_address_cntrl),
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.ddr_cke_cntrl (ddr_cke_cntrl),
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.ddr_csb_cntrl (ddr_csb_cntrl),
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.ddr_odt_cntrl (ddr_odt_cntrl),
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.dqs_enable (dqs_enable),
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.dqs_reset (dqs_reset),
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.write_enable (write_enable),
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.rst_calib (rst_calib),
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.rst_dqs_div_int (rst_dqs_div_int),
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.cmd_ack (user_cmd_ack),
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.init (init_done),
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.ar_done (ar_done),
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.read_fifo_rden (read_fifo_rden) // Added new signal
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);
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s3adsp_ddr2_data_path_0 data_path0
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(
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.user_input_data (user_input_data),
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.user_data_mask (user_data_mask),
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.clk (clk_int),
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.clk90 (clk90_int),
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.reset (sys_rst),
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.reset90 (sys_rst90),
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.write_enable (write_enable),
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.rst_dqs_div_in (dqs_div_rst),
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.delay_sel (delay_sel),
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.dqs_int_delay_in (dqs_int_delay_in),
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.dq (dq),
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.u_data_val (user_data_valid),
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.user_output_data (user_output_data),
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.write_en_val (write_en_val),
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.data_mask_f (data_mask_f),
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.data_mask_r (data_mask_r),
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.write_data_falling (write_data_falling),
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.write_data_rising (write_data_rising),
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.read_fifo_rden (read_fifo_rden), // Added new signal
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//debug signals
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.vio_out_dqs (vio_out_dqs),
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.vio_out_dqs_en (vio_out_dqs_en),
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.vio_out_rst_dqs_div (vio_out_rst_dqs_div),
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.vio_out_rst_dqs_div_en (vio_out_rst_dqs_div_en)
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);
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s3adsp_ddr2_infrastructure infrastructure0
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(
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.clk_int (clk_int),
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.rst_calib1 (rst_calib),
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.delay_sel_val (delay_sel_val),
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.delay_sel_val1_val (delay_sel),
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.dbg_delay_sel (dbg_delay_sel),
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.dbg_rst_calib (dbg_rst_calib)
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);
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s3adsp_ddr2_iobs_0 iobs0
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(
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.clk (clk_int),
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.clk90 (clk90_int),
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.ddr_rasb_cntrl (ddr_rasb_cntrl),
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.ddr_casb_cntrl (ddr_casb_cntrl),
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.ddr_web_cntrl (ddr_web_cntrl),
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.ddr_cke_cntrl (ddr_cke_cntrl),
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.ddr_csb_cntrl (ddr_csb_cntrl),
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.ddr_odt_cntrl (ddr_odt_cntrl),
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.ddr_address_cntrl (ddr_address_cntrl),
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.ddr_ba_cntrl (ddr_ba_cntrl),
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.rst_dqs_div_int (rst_dqs_div_int),
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.dqs_reset (dqs_reset),
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.dqs_enable (dqs_enable),
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.ddr_dqs (ddr2_dqs),
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.ddr_dqs_n (ddr2_dqs_n),
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.ddr_dq (ddr2_dq),
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.write_data_falling(write_data_falling),
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.write_data_rising (write_data_rising),
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.write_en_val (write_en_val),
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.data_mask_f (data_mask_f),
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.data_mask_r (data_mask_r),
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.ddr2_ck (ddr2_ck),
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.ddr2_ck_n (ddr2_ck_n),
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.ddr_rasb (ddr2_ras_n),
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.ddr_casb (ddr2_cas_n),
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.ddr_web (ddr2_we_n),
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.ddr_ba (ddr2_ba),
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.ddr_address (ddr2_a),
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.ddr_cke (ddr2_cke),
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.ddr_csb (ddr2_cs_n),
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.ddr_odt0 (ddr2_odt),
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.rst_dqs_div (dqs_div_rst),
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.rst_dqs_div_in (rst_dqs_div_in),
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.rst_dqs_div_out (rst_dqs_div_out),
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.dqs_int_delay_in (dqs_int_delay_in),
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.ddr_dm (ddr2_dm),
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.dq (dq)
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);
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endmodule
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