URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [sw/] [Makefile.inc] - Blame information for rev 568

Details | Compare with Previous | View Log


 
# Expecting BOARD_SW_ROOT already set to indicate how far below directory we're
# in the board's software root path is.
 
# Root from the board's sw/ path
PROJ_ROOT=../../../..
 
# Figure out actual path the common software directory
SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw
 
# Set the BOARD_PATH to point to the root of this board build
BOARD=xilinx/s3adsp1800
 
# Set RTL_VERILOG_INCLUDE_DIR so software
RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include
 
# Set the processor capability flags
MARCH_FLAGS =-mhard-mul -mhard-div -mhard-float
#MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float
export MARCH_FLAGS
 
# Finally include the main software include file
 
include $(SW_ROOT)/Makefile.inc

Line No.	Rev	Author	Line
1	568	julius
2			`# Expecting BOARD_SW_ROOT already set to indicate how far below directory we're`
3			`# in the board's software root path is.`
4
5			`# Root from the board's sw/ path`
6			`PROJ_ROOT=../../../..`
7
8			`# Figure out actual path the common software directory`
9			`SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw`
10
11			`# Set the BOARD_PATH to point to the root of this board build`
12			`BOARD=xilinx/s3adsp1800`
13
14			`# Set RTL_VERILOG_INCLUDE_DIR so software`
15			`RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include`
16
17			`# Set the processor capability flags`
18			`MARCH_FLAGS =-mhard-mul -mhard-div -mhard-float`
19			`#MARCH_FLAGS =-mhard-mul -msoft-div -msoft-float`
20			`export MARCH_FLAGS`
21
22			`# Finally include the main software include file`
23
24			`include $(SW_ROOT)/Makefile.inc`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [sw/] [Makefile.inc] - Blame information for rev 568