OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [sw/] [board/] [include/] [board.h] - Blame information for rev 570

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 568 julius
#ifndef _BOARD_H_
2
#define _BOARD_H_
3
 
4
#define IN_CLK                25000000 // Hz
5
//#define IN_CLK              50000000 // Hz
6
//#define IN_CLK              66666667 // Hz
7
 
8
//
9
// ROM bootloader
10
//
11
// Uncomment the appropriate bootloader define. This will effect the bootrom.S
12
// file, which is compiled and converted into Verilog for inclusion at 
13
// synthesis time. See bootloader/bootloader.S for details on each option.
14
#ifndef PRELOAD_RAM
15
//#define BOOTROM_SPI_FLASH
16
#define BOOTROM_GOTO_RESET
17
//#define BOOTROM_LOOP_AT_ZERO
18
//#define BOOTROM_LOOP_IN_ROM
19
#else
20
 
21
// For now just go to reset on board reset
22
#define BOOTROM_GOTO_RESET
23
 
24
#endif
25
 
26
// Address bootloader should start from in FLASH
27
// Last 256KB of 8MB flash - offset 0x7c0000 (8MB-256KB)
28
#define BOOTROM_ADDR_BYTE2 0x7c
29
#define BOOTROM_ADDR_BYTE1 0x00
30
#define BOOTROM_ADDR_BYTE0 0x00
31
// Causes SPI bootloader to loop if SPI didn't give correct size of image
32
#define SPI_RETRY_IF_INSANE_SIZEWORD
33
 
34
//
35
// Defines for each core (memory map base, OR1200 interrupt line number, etc.)
36
//
37
#define SDRAM_BASE                 0x0
38
 
39
#define GPIO_0_BASE         0x91000000
40
 
41
#define UART0_BASE          0x90000000
42
#define UART0_IRQ                    2
43
#define UART0_BAUD_RATE         115200
44
 
45
 
46
#define SPI0_BASE           0xb0000000
47
#define SPI0_IRQ                     6
48
 
49
#define I2C_0_BASE          0xa0000000
50
#define I2C_0_IRQ                   10
51
 
52
#define ETH0_BASE            0x92000000
53
#define ETH0_IRQ                      4
54
 
55
#define ETH_MACADDR0               0x00
56
#define ETH_MACADDR1               0x12
57
#define ETH_MACADDR2               0x34
58
#define ETH_MACADDR3               0x56
59
#define ETH_MACADDR4               0x78
60
#define ETH_MACADDR5               0x9a
61
 
62
//
63
// OR1200 tick timer period define
64
//
65
#define TICKS_PER_SEC   100
66
 
67
 
68
 
69
//
70
// UART driver configuration
71
// 
72
#define UART_NUM_CORES 1
73
#define UART_BASE_ADDRESSES_CSV UART0_BASE
74
#define UART_BAUD_RATES_CSV UART0_BAUD_RATE
75
 
76
 
77
// 
78
// i2c_master_slave core driver configuration
79
//
80
 
81
#define I2C_MASTER_SLAVE_NUM_CORES 1
82
 
83
#define I2C_MASTER_SLAVE_BASE_ADDRESSES_CSV             \
84
        I2C_0_BASE
85
 
86
 
87
#endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.