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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [sw/] [tests/] [ddr2cache/] [sim/] [ddr2cache-1.S] - Blame information for rev 568

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Line No. Rev Author Line
1 568 julius 
/*
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        Simple test to exercise cache writeback
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        Hardcoded for cache with 4 lines of 32 bytes.
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        Julius Baxter, ORSoC AB,
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*/
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#include "spr-defs.h"
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#define NUM_LINES 4
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#define BYTES_PER_LINE 32
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        .section .vectors, "ax"
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/* ---[ 0x100: RESET exception ]----------------------------------------- */
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        .org 0x100
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        l.movhi r0, 0
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        /* Clear status register */
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        l.ori r1, r0, SPR_SR_SM
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        l.mtspr r0, r1, SPR_SR
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        /* Clear timer  */
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        l.mtspr r0, r0, SPR_TTMR
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        /* Jump to program initialisation code */
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        .global _start
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        l.movhi r4, hi(_start)
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        l.ori r4, r4, lo(_start)
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        l.jr    r4
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        l.nop
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/* =================================================== [ text ] === */
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        .section .text
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/* =================================================== [ start ] === */
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        .global _start
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_start:
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        l.movhi r1,hi(_stack)
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        l.ori   r1,r1,lo(_stack)
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        l.addi  r2, r0, -3
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        l.and   r1, r1, r2
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        l.movhi r2,0    /*r2 is counter */
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        /* Write data into addresses that should step through the
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        lines of the cache */
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        l.addi  r5,r0,-(BYTES_PER_LINE-1)
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        l.and   r4,r1,r5        /* r4 has base address of place to access */
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        l.addi  r4,r4,BYTES_PER_LINE    /* Go to safe address, past top of stack */
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        /* report this address */
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        l.ori   r3,r4,0
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        l.nop   0x2
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wr_loop:
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        l.muli  r5,r2,BYTES_PER_LINE    /* offset from base address */
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        l.add   r6,r5,r4        /* Address to write to (line offset + base) */
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        /* report this address */
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        l.ori   r3,r6,0
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        l.nop   0x2
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        /* report counter */
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        l.ori   r3,r2,0
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        l.nop   0x2
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        /* do memory access */
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        l.sw    0(r6),r2        /* Write counter to this address */
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        l.sfeqi r2,(NUM_LINES-1)        /* Done all lines? */
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        l.bnf   wr_loop
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        l.addi  r2,r2,1         /* increment line counter */
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        /* end of write loop */
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        /* reset counter */
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        l.movhi r2,0
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rd_loop:
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        l.muli  r5,r2,BYTES_PER_LINE    /* offset from base address */
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        l.add   r6,r5,r4        /* Address to write to (line offset + base) */
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        /* report this address */
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        l.ori   r3,r6,0
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        l.nop   0x2
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        /* report counter */
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        l.ori   r3,r2,0
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        l.nop   0x2
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        /* do memory access */
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        l.lwz   r7,0(r6)        /* load value */
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        /* should equal r2 */
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        l.sfne  r2,r7
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        l.bf    fail
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        l.nop
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        l.sfeqi r2,(NUM_LINES-1)        /* Done all lines? */
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        l.bnf   rd_loop
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        l.addi  r2,r2,1         /* increment line counter */
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        /* end of read loop */
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pass:
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        l.movhi r3,0x8000
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        l.ori   r3,r3,0x000d
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        l.nop   0x2
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        l.movhi r3,0
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        l.nop   0x1
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fail:
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        l.movhi r3,0xbaaa
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        l.ori   r3,r3,0xaaad
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        l.nop   0x1
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