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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [sw/] [tests/] [ethmac/] [sim/] [ethmac-rx.c] - Blame information for rev 568

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1 568 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Interrupt-driven Ethernet MAC test code                     ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Do ethernet receive path testing                            ////
7
////  Relies on testbench to provide simulus - expects at least   ////
8
////  256 packets to be sent.                                     ////
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////                                                              ////
10
////  Author(s):                                                  ////
11
////      - Julius Baxter, julius@opencores.org                   ////
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////                                                              ////
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////                                                              ////
14
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
19
//// restriction provided that this copyright statement is not    ////
20
//// removed from the file and that any derivative work contains  ////
21
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
24
//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
30
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
32
//// PURPOSE.  See the GNU Lesser General Public License for more ////
33
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
36
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
40
 
41
#include "cpu-utils.h"
42
#include "board.h"
43
#include "int.h"
44
#include "ethmac.h"
45
#include "eth-phy-mii.h"
46
 
47
volatile unsigned tx_done;
48
volatile unsigned rx_done;
49
 
50
/* Functions in this file */
51
void ethmac_setup(void);
52
void oeth_dump_bds();
53
/* Interrupt functions */
54
void oeth_interrupt(void);
55
static void oeth_rx(void);
56
static void oeth_tx(void);
57
/* Function to calculate checksum of ping responses we send */
58
unsigned short calculate_checksum(char* dats, unsigned int len) ;
59
 
60
/* Let the ethernet packets use a space beginning here for buffering */
61
#define ETH_BUFF_BASE 0x200000;
62
 
63
#define RXBUFF_PREALLOC 1
64
#define TXBUFF_PREALLOC 1
65
 
66
/* The transmitter timeout
67
 */
68
#define TX_TIMEOUT      (2*HZ)
69
 
70
/* Buffer number (must be 2^n)
71
 * Note: if changing these, must also change settings in eth_stim.v testbench
72
 * file!
73
 */
74
#define OETH_RXBD_NUM           16
75
#define OETH_TXBD_NUM           16
76
#define OETH_RXBD_NUM_MASK      (OETH_RXBD_NUM-1)
77
#define OETH_TXBD_NUM_MASK      (OETH_TXBD_NUM-1)
78
 
79
/* Buffer size
80
 */
81
#define OETH_RX_BUFF_SIZE       0x600
82
#define OETH_TX_BUFF_SIZE       0x600
83
 
84
/* Buffer size  (if not XXBUF_PREALLOC
85
 */
86
#define MAX_FRAME_SIZE          1518
87
 
88
/* The buffer descriptors track the ring buffers.
89
 */
90
struct oeth_private {
91
  //struct      sk_buff* rx_skbuff[OETH_RXBD_NUM];
92
  //struct      sk_buff* tx_skbuff[OETH_TXBD_NUM];
93
 
94
  unsigned short        tx_next;                        /* Next buffer to be sent */
95
  unsigned short        tx_last;                        /* Next buffer to be checked if packet sent */
96
  unsigned short        tx_full;                        /* Buffer ring fuul indicator */
97
  unsigned short        rx_cur;                         /* Next buffer to be checked if packet received */
98
 
99
  oeth_regs     *regs;                  /* Address of controller registers. */
100
  oeth_bd               *rx_bd_base;            /* Address of Rx BDs. */
101
  oeth_bd               *tx_bd_base;            /* Address of Tx BDs. */
102
 
103
  //    struct net_device_stats stats;
104
};
105
 
106
 
107
char CHECKSUM_BUFFER[OETH_RX_BUFF_SIZE]; // Big enough to hold a packet
108
 
109
#define PHYNUM 7
110
 
111
void ethmac_setup(void)
112
{
113
  // from arch/or32/drivers/open_eth.c
114
  volatile oeth_regs *regs;
115
 
116
  regs = (oeth_regs *)(OETH_REG_BASE);
117
 
118
  /* Reset MII mode module */
119
  regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */
120
  regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */
121
  regs->miimoder = 0x64; /* Clock divider for MII Management interface */
122
 
123
  /* Reset the controller.
124
   */
125
  regs->moder = OETH_MODER_RST; /* Reset ON */
126
  regs->moder &= ~OETH_MODER_RST;       /* Reset OFF */
127
 
128
  /* Setting TXBD base to OETH_TXBD_NUM.
129
   */
130
  regs->tx_bd_num = OETH_TXBD_NUM;
131
 
132
 
133
  /* Set min/max packet length
134
   */
135
  regs->packet_len = 0x00400600;
136
 
137
  /* Set IPGT register to recomended value
138
   */
139
  regs->ipgt = 0x12;
140
 
141
  /* Set IPGR1 register to recomended value
142
   */
143
  regs->ipgr1 = 0x0000000c;
144
 
145
  /* Set IPGR2 register to recomended value
146
   */
147
  regs->ipgr2 = 0x00000012;
148
 
149
  /* Set COLLCONF register to recomended value
150
   */
151
  regs->collconf = 0x000f003f;
152
 
153
  /* Set control module mode
154
   */
155
#if 0
156
  regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
157
#else
158
  regs->ctrlmoder = 0;
159
#endif
160
 
161
  /* Clear MIIM registers */
162
  regs->miitx_data = 0;
163
  regs->miiaddress = 0;
164
  regs->miicommand = 0;
165
 
166
  regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1;
167
  regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5;
168
 
169
  /* Clear all pending interrupts
170
   */
171
  regs->int_src = 0xffffffff;
172
 
173
  /* Promisc, IFG, CRCEn
174
   */
175
  regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD;
176
 
177
  /* Enable interrupt sources.
178
   */
179
 
180
  regs->int_mask = OETH_INT_MASK_TXB    |
181
    OETH_INT_MASK_TXE   |
182
    OETH_INT_MASK_RXF   |
183
    OETH_INT_MASK_RXE   |
184
    OETH_INT_MASK_BUSY  |
185
    OETH_INT_MASK_TXC   |
186
    OETH_INT_MASK_RXC;
187
 
188
  // Buffer setup stuff
189
  volatile oeth_bd *tx_bd, *rx_bd;
190
  int i,j,k;
191
 
192
  /* Initialize TXBD pointer
193
   */
194
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
195
 
196
  /* Initialize RXBD pointer
197
   */
198
  rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
199
 
200
  /* Preallocated ethernet buffer setup */
201
  unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */
202
 
203
  // Setup TX Buffers
204
  for(i = 0; i < OETH_TXBD_NUM; i++) {
205
      //tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
206
      tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
207
      tx_bd[i].addr = mem_addr;
208
      mem_addr += OETH_TX_BUFF_SIZE;
209
  }
210
  tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP;
211
 
212
  // Setup RX buffers
213
  for(i = 0; i < OETH_RXBD_NUM; i++) {
214
    rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ
215
    rx_bd[i].addr = mem_addr;
216
    mem_addr += OETH_RX_BUFF_SIZE;
217
  }
218
  rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps
219
 
220
  /* Enable just the receiver
221
   */
222
  regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
223
  regs->moder |= OETH_MODER_RXEN /* | OETH_MODER_TXEN*/;
224
 
225
  return;
226
}
227
 
228
void
229
ethmac_halt(void)
230
{
231
  volatile oeth_regs *regs;
232
 
233
  regs = (oeth_regs *)(OETH_REG_BASE);
234
 
235
  // Disable receive and transmit
236
  regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
237
 
238
}
239
 
240
 
241
/* The interrupt handler.
242
 */
243
void
244
oeth_interrupt(void)
245
{
246
 
247
  volatile oeth_regs *regs;
248
  regs = (oeth_regs *)(OETH_REG_BASE);
249
 
250
  uint  int_events;
251
  int serviced;
252
 
253
        serviced = 0;
254
 
255
        /* Get the interrupt events that caused us to be here.
256
         */
257
        int_events = regs->int_src;
258
        regs->int_src = int_events;
259
 
260
 
261
        /* Handle receive event in its own function.
262
         */
263
        if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
264
                serviced |= 0x1;
265
                oeth_rx();
266
        }
267
 
268
        /* Handle transmit event in its own function.
269
         */
270
        if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
271
                serviced |= 0x2;
272
                oeth_tx();
273
                serviced |= 0x2;
274
 
275
        }
276
 
277
        /* Check for receive busy, i.e. packets coming but no place to
278
         * put them.
279
         */
280
        if (int_events & OETH_INT_BUSY) {
281
                serviced |= 0x4;
282
                if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
283
                  oeth_rx();
284
        }
285
 
286
        return;
287
}
288
 
289
 
290
 
291
static void
292
oeth_rx(void)
293
{
294
  volatile oeth_regs *regs;
295
  regs = (oeth_regs *)(OETH_REG_BASE);
296
 
297
  volatile oeth_bd *rx_bdp;
298
  int   pkt_len, i;
299
  int   bad = 0;
300
 
301
  rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
302
 
303
  /* Find RX buffers marked as having received data */
304
  for(i = 0; i < OETH_RXBD_NUM; i++)
305
    {
306
      bad=0;
307
      /* Looking for buffer descriptors marked not empty */
308
      if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){
309
        /* Check status for errors.
310
         */
311
        report(i);
312
        report(rx_bdp[i].len_status);
313
        if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
314
          bad = 1;
315
          report(0xbaad0001);
316
        }
317
        if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) {
318
          bad = 1;
319
          report(0xbaad0002);
320
        }
321
        if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) {
322
          bad = 1;
323
          report(0xbaad0003);
324
        }
325
        if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) {
326
          bad = 1;
327
          report(0xbaad0004);
328
        }
329
        if (rx_bdp[i].len_status & OETH_RX_BD_MISS) {
330
          report(0xbaad0005);
331
        }
332
        if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) {
333
          bad = 1;
334
          report(0xbaad0006);
335
        }
336
        if (bad) {
337
          rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
338
          rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
339
          //exit(0xbaaaaaad);
340
 
341
          continue;
342
        }
343
        else {
344
          /*
345
           * Process the incoming frame.
346
           */
347
          pkt_len = rx_bdp[i].len_status >> 16;
348
 
349
          // Do a bit of work - ie. copy it, process it
350
          memcpy(CHECKSUM_BUFFER, rx_bdp[i].addr, pkt_len);
351
          report(0xc4eccccc);
352
          report(calculate_checksum(CHECKSUM_BUFFER, pkt_len));
353
 
354
          /* finish up */
355
          rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
356
          rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
357
          rx_done++;
358
          report(rx_done);
359
        }
360
      }
361
    }
362
}
363
 
364
// Calculate checksum on received data.
365
// From http://lkml.indiana.edu/hypermail/linux/kernel/9612.3/0060.html
366
unsigned short calculate_checksum(char* dats, unsigned int len)
367
{
368
  unsigned int itr;
369
  unsigned long accum = 0;
370
  unsigned long longsum;
371
 
372
  // Sum all pairs of data
373
  for(itr=0;itr<(len & ~0x1);itr+=2)
374
    accum += (unsigned long)(((dats[itr]<<8)&0xff00)|(dats[itr+1]&0x00ff));
375
 
376
  if (len & 0x1) // Do leftover
377
    accum += (unsigned long) ((dats[itr-1]<<8)&0xff00);
378
 
379
  longsum = (unsigned long) (accum & 0xffff);
380
  longsum += (unsigned long) (accum >> 16); // Sum the carries
381
  longsum += (longsum >> 16);
382
  return (unsigned short)((longsum ^ 0xffff) & 0xffff);
383
 
384
}
385
 
386
 
387
static void
388
oeth_tx(void)
389
{
390
  volatile oeth_bd *tx_bd;
391
  int i;
392
 
393
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
394
 
395
  /* Go through the TX buffs, search for one that was just sent */
396
  for(i = 0; i < OETH_TXBD_NUM; i++)
397
    {
398
      /* Looking for buffer NOT ready for transmit. and IRQ enabled */
399
      if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) )
400
        {
401
          /* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */
402
          tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
403
 
404
          /* Probably good to check for TX errors here */
405
 
406
          /* set our test variable */
407
          tx_done = 1;
408
 
409
        }
410
    }
411
  return;
412
}
413
 
414
// Loop to check if a number is prime by doing mod divide of the number
415
// to test by every number less than it
416
int
417
is_prime_number(unsigned long n)
418
{
419
  unsigned long c;
420
  if (n < 2) return 0;
421
  for(c=2;c<n;c++)
422
    if ((n % c) == 0)
423
      return 0;
424
  return 1;
425
}
426
 
427
int
428
main ()
429
{
430
 
431
  /* Initialise handler vector */
432
  int_init();
433
 
434
  /* Install ethernet interrupt handler, it is enabled here too */
435
  int_add(ETH0_IRQ, oeth_interrupt, 0);
436
 
437
  /* Enable interrupts in supervisor register */
438
  cpu_enable_user_interrupts();
439
 
440
  /* Enable CPU timer */
441
  cpu_enable_timer();
442
 
443
  rx_done = 0;
444
 
445
  ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX in MODER */
446
 
447
#define NUM_PRIMES_TO_CHECK 1000
448
#define RX_TEST_LENGTH_PACKETS 12
449
 
450
  char prime_check_results[NUM_PRIMES_TO_CHECK];
451
  unsigned long num_to_check;
452
 
453
  for(num_to_check=2;num_to_check<NUM_PRIMES_TO_CHECK;num_to_check++)
454
    {
455
      prime_check_results[num_to_check-2]
456
        = (char) is_prime_number(num_to_check);
457
      report(num_to_check | (0x1e<<24));
458
      report(prime_check_results[num_to_check-2] | (0x2e<<24));
459
      // Check number of packets received, testbench will hopefully send at
460
      // least this many packets
461
      if (rx_done >= (RX_TEST_LENGTH_PACKETS - 1))
462
        exit(0x8000000d);
463
    }
464
 
465
  ethmac_halt();
466
 
467
  exit(0x8000000d);
468
 
469
  return 0;
470
}

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