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[/] [openrisc/] [trunk/] [orpsocv2/] [boards/] [xilinx/] [s3adsp1800/] [sw/] [tests/] [ethmac/] [sim/] [ethmac-rxtx.c] - Blame information for rev 568

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1 568 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Interrupt-driven Ethernet MAC transmit test code            ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Send packets while receiving packets                        ////
7
////                                                              ////
8
////  Test data comes from pre-calculated array of random values, ////
9
////  MAC TX buffer pointers are set to addresses in this array,  ////
10
////  saving copying the data around before transfers.            ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - jb, jb@orsoc.se, with parts taken from Linux kernel   ////
14
////        open_eth driver.                                      ////
15
////                                                              ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
 
44
#include "cpu-utils.h"
45
#include "board.h"
46
#include "int.h"
47
#include "ethmac.h"
48
#include "eth-phy-mii.h"
49
 
50
volatile unsigned tx_done;
51
volatile unsigned rx_done;
52
static int next_tx_buf_num;
53
 
54
/* Functions in this file */
55
void ethmac_setup(void);
56
/* Interrupt functions */
57
void oeth_interrupt(void);
58
static void oeth_rx(void);
59
static void oeth_tx(void);
60
 
61
/* Let the ethernet packets use a space beginning here for buffering */
62
#define ETH_BUFF_BASE 0x200000;
63
 
64
 
65
#define RXBUFF_PREALLOC 1
66
#define TXBUFF_PREALLOC 1
67
//#undef RXBUFF_PREALLOC
68
//#undef TXBUFF_PREALLOC
69
 
70
/* The transmitter timeout
71
*/
72
#define TX_TIMEOUT      (2*HZ)
73
 
74
/* Buffer number (must be 2^n)
75
*/
76
#define OETH_RXBD_NUM           16
77
#define OETH_TXBD_NUM           16
78
#define OETH_RXBD_NUM_MASK      (OETH_RXBD_NUM-1)
79
#define OETH_TXBD_NUM_MASK      (OETH_TXBD_NUM-1)
80
 
81
/* Buffer size
82
*/
83
#define OETH_RX_BUFF_SIZE       0x600-4
84
#define OETH_TX_BUFF_SIZE       0x600-4
85
 
86
/* Buffer size  (if not XXBUF_PREALLOC
87
*/
88
#define MAX_FRAME_SIZE          1518
89
 
90
/* The buffer descriptors track the ring buffers.
91
*/
92
struct oeth_private {
93
  //struct      sk_buff* rx_skbuff[OETH_RXBD_NUM];
94
  //struct      sk_buff* tx_skbuff[OETH_TXBD_NUM];
95
 
96
  unsigned short        tx_next; /* Next buffer to be sent */
97
  unsigned short        tx_last; /* Next buffer to be checked if packet sent */
98
  unsigned short        tx_full; /* Buffer ring fuul indicator */
99
  unsigned short        rx_cur;  /* Next buffer to be checked if packet
100
                                    received */
101
 
102
  oeth_regs     *regs;                  /* Address of controller registers. */
103
  oeth_bd               *rx_bd_base;            /* Address of Rx BDs. */
104
  oeth_bd               *tx_bd_base;            /* Address of Tx BDs. */
105
 
106
  //    struct net_device_stats stats;
107
};
108
 
109
#define PHYNUM 7
110
 
111
// Data array of data to transmit, tx_data_array[]
112
//#include "eth-rxtx-data.h" // Not used
113
int tx_data_pointer;
114
 
115
 
116
void
117
eth_mii_write(char phynum, short regnum, short data)
118
{
119
  static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
120
  regs->miiaddress = (regnum << 8) | phynum;
121
  regs->miitx_data = data;
122
  regs->miicommand = OETH_MIICOMMAND_WCTRLDATA;
123
  regs->miicommand = 0;
124
  while(regs->miistatus & OETH_MIISTATUS_BUSY);
125
}
126
 
127
short
128
eth_mii_read(char phynum, short regnum)
129
{
130
  static volatile oeth_regs *regs = (oeth_regs *)(OETH_REG_BASE);
131
  regs->miiaddress = (regnum << 8) | phynum;
132
  regs->miicommand = OETH_MIICOMMAND_RSTAT;
133
  regs->miicommand = 0;
134
  while(regs->miistatus & OETH_MIISTATUS_BUSY);
135
 
136
  return regs->miirx_data;
137
}
138
 
139
 
140
 
141
// Wait here until all packets have been transmitted
142
void
143
wait_until_all_tx_clear(void)
144
{
145
  int i;
146
  volatile oeth_bd *tx_bd;
147
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
148
 
149
  int some_tx_waiting = 1;
150
 
151
  while (some_tx_waiting)
152
    {
153
      some_tx_waiting = 0;
154
      /* Go through the TX buffs, search for unused one */
155
      for(i = 0; i < OETH_TXBD_NUM; i++) {
156
 
157
        // Looking for buffer ready for transmit
158
        if((tx_bd[i].len_status & OETH_TX_BD_READY))
159
          some_tx_waiting = 1;
160
 
161
      }
162
    }
163
}
164
 
165
 
166
void
167
ethphy_set_10mbit(int phynum)
168
{
169
  wait_until_all_tx_clear();
170
  // Hardset PHY to just use 10Mbit mode
171
  short cr = eth_mii_read(phynum, MII_BMCR);
172
  cr &= ~BMCR_ANENABLE; // Clear auto negotiate bit
173
  cr &= ~BMCR_SPEED100; // Clear fast eth. bit
174
  eth_mii_write(phynum, MII_BMCR, cr);
175
}
176
 
177
 
178
void
179
ethphy_set_100mbit(int phynum)
180
{
181
  wait_until_all_tx_clear();
182
  // Hardset PHY to just use 100Mbit mode
183
  short cr = eth_mii_read(phynum, MII_BMCR);
184
  cr |= BMCR_ANENABLE; // Clear auto negotiate bit
185
  cr |= BMCR_SPEED100; // Clear fast eth. bit
186
  eth_mii_write(phynum, MII_BMCR, cr);
187
}
188
 
189
 
190
void
191
ethmac_setup(void)
192
{
193
  // from arch/or32/drivers/open_eth.c
194
  volatile oeth_regs *regs;
195
 
196
  regs = (oeth_regs *)(OETH_REG_BASE);
197
 
198
  /* Reset MII mode module */
199
  regs->miimoder = OETH_MIIMODER_RST; /* MII Reset ON */
200
  regs->miimoder &= ~OETH_MIIMODER_RST; /* MII Reset OFF */
201
  regs->miimoder = 0x64; /* Clock divider for MII Management interface */
202
 
203
  /* Reset the controller.
204
  */
205
  regs->moder = OETH_MODER_RST; /* Reset ON */
206
  regs->moder &= ~OETH_MODER_RST;       /* Reset OFF */
207
 
208
  /* Setting TXBD base to OETH_TXBD_NUM.
209
  */
210
  regs->tx_bd_num = OETH_TXBD_NUM;
211
 
212
 
213
  /* Set min/max packet length
214
  */
215
  regs->packet_len = 0x00400600;
216
 
217
  /* Set IPGT register to recomended value
218
  */
219
  regs->ipgt = 0x12;
220
 
221
  /* Set IPGR1 register to recomended value
222
  */
223
  regs->ipgr1 = 0x0000000c;
224
 
225
  /* Set IPGR2 register to recomended value
226
  */
227
  regs->ipgr2 = 0x00000012;
228
 
229
  /* Set COLLCONF register to recomended value
230
  */
231
  regs->collconf = 0x000f003f;
232
 
233
  /* Set control module mode
234
  */
235
#if 0
236
  regs->ctrlmoder = OETH_CTRLMODER_TXFLOW | OETH_CTRLMODER_RXFLOW;
237
#else
238
  regs->ctrlmoder = 0;
239
#endif
240
 
241
  /* Clear MIIM registers */
242
  regs->miitx_data = 0;
243
  regs->miiaddress = 0;
244
  regs->miicommand = 0;
245
 
246
  regs->mac_addr1 = ETH_MACADDR0 << 8 | ETH_MACADDR1;
247
  regs->mac_addr0 = ETH_MACADDR2 << 24 | ETH_MACADDR3 << 16 | ETH_MACADDR4 << 8 | ETH_MACADDR5;
248
 
249
  /* Clear all pending interrupts
250
  */
251
  regs->int_src = 0xffffffff;
252
 
253
  /* Promisc, IFG, CRCEn
254
  */
255
  regs->moder |= OETH_MODER_PRO | OETH_MODER_PAD | OETH_MODER_IFG | OETH_MODER_CRCEN | OETH_MODER_FULLD;
256
 
257
  /* Enable interrupt sources.
258
  */
259
 
260
  regs->int_mask = OETH_INT_MASK_TXB    |
261
    OETH_INT_MASK_TXE   |
262
    OETH_INT_MASK_RXF   |
263
    OETH_INT_MASK_RXE   |
264
    OETH_INT_MASK_BUSY  |
265
    OETH_INT_MASK_TXC   |
266
    OETH_INT_MASK_RXC;
267
 
268
  // Buffer setup stuff
269
  volatile oeth_bd *tx_bd, *rx_bd;
270
  int i,j,k;
271
 
272
  /* Initialize TXBD pointer
273
  */
274
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
275
 
276
  /* Initialize RXBD pointer
277
  */
278
  rx_bd = ((volatile oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
279
 
280
  /* Preallocated ethernet buffer setup */
281
  unsigned long mem_addr = ETH_BUFF_BASE; /* Defined at top */
282
 
283
  // Setup TX Buffers
284
  for(i = 0; i < OETH_TXBD_NUM; i++) {
285
    //tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC | OETH_RX_BD_IRQ;
286
    tx_bd[i].len_status = OETH_TX_BD_PAD | OETH_TX_BD_CRC;
287
    tx_bd[i].addr = mem_addr;
288
    mem_addr += OETH_TX_BUFF_SIZE;
289
  }
290
  tx_bd[OETH_TXBD_NUM - 1].len_status |= OETH_TX_BD_WRAP;
291
 
292
  // Setup RX buffers
293
  for(i = 0; i < OETH_RXBD_NUM; i++) {
294
    rx_bd[i].len_status = OETH_RX_BD_EMPTY | OETH_RX_BD_IRQ; // Init. with IRQ
295
    rx_bd[i].addr = mem_addr;
296
    mem_addr += OETH_RX_BUFF_SIZE;
297
  }
298
  rx_bd[OETH_RXBD_NUM - 1].len_status |= OETH_RX_BD_WRAP; // Last buffer wraps
299
 
300
  /* Enable RX and TX in MAC
301
  */
302
  regs->moder &= ~(OETH_MODER_RXEN | OETH_MODER_TXEN);
303
  regs->moder |= OETH_MODER_RXEN | OETH_MODER_TXEN;
304
 
305
  next_tx_buf_num = 0; // init tx buffer pointer
306
 
307
  return;
308
}
309
 
310
// Enable RX in ethernet MAC
311
void
312
oeth_enable_rx(void)
313
{
314
  volatile oeth_regs *regs;
315
  regs = (oeth_regs *)(OETH_REG_BASE);
316
  regs->moder |= OETH_MODER_RXEN;
317
}
318
 
319
// Disable RX in ethernet MAC
320
void
321
oeth_disable_rx(void)
322
{
323
  volatile oeth_regs *regs;
324
  regs = (oeth_regs *)(OETH_REG_BASE);
325
  regs->moder &= ~(OETH_MODER_RXEN);
326
}
327
 
328
 
329
/* Setup buffer descriptors with data */
330
/* length is in BYTES */
331
void tx_packet(void* data, int length)
332
{
333
  volatile oeth_regs *regs;
334
  regs = (oeth_regs *)(OETH_REG_BASE);
335
 
336
  volatile oeth_bd *tx_bd;
337
  volatile int i;
338
 
339
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
340
  tx_bd = (struct oeth_bd*) &tx_bd[next_tx_buf_num];
341
 
342
  // If it's in use - wait
343
  while ((tx_bd->len_status & OETH_TX_BD_IRQ));
344
 
345
  /* Clear all of the status flags.
346
  */
347
  tx_bd->len_status &= ~OETH_TX_BD_STATS;
348
 
349
  /* If the frame is short, tell CPM to pad it.
350
  */
351
#define ETH_ZLEN        60   /* Min. octets in frame sans FCS */
352
  if (length <= ETH_ZLEN)
353
    tx_bd->len_status |= OETH_TX_BD_PAD;
354
  else
355
    tx_bd->len_status &= ~OETH_TX_BD_PAD;
356
 
357
#ifdef _ETH_RXTX_DATA_H_
358
  // Set the address pointer to the place
359
  // in memory where the data is and transmit from there
360
 
361
  tx_bd->addr = (char*) &tx_data_array[tx_data_pointer&~(0x3)];
362
 
363
  tx_data_pointer += length + 1;
364
  if (tx_data_pointer > (255*1024))
365
    tx_data_pointer = 0;
366
 
367
 
368
#else
369
  if (data){
370
    //Copy the data into the transmit buffer, byte at a time 
371
    char* data_p = (char*) data;
372
    char* data_b = (char*) tx_bd->addr;
373
    for(i=0;i<length;i++)
374
      {
375
        data_b[i] = data_p[i];
376
      }
377
  }
378
#endif
379
 
380
  /* Set the length of the packet's data in the buffer descriptor */
381
  tx_bd->len_status = (tx_bd->len_status & 0x0000ffff) |
382
    ((length&0xffff) << 16);
383
 
384
  /* Send it on its way.  Tell controller its ready, interrupt when sent
385
  * and to put the CRC on the end.
386
  */
387
  tx_bd->len_status |= (OETH_TX_BD_READY  | OETH_TX_BD_CRC | OETH_TX_BD_IRQ);
388
 
389
  next_tx_buf_num = (next_tx_buf_num + 1) & OETH_TXBD_NUM_MASK;
390
 
391
  return;
392
 
393
 
394
}
395
 
396
/* The interrupt handler.
397
*/
398
void
399
oeth_interrupt(void)
400
{
401
 
402
  volatile oeth_regs *regs;
403
  regs = (oeth_regs *)(OETH_REG_BASE);
404
 
405
  uint  int_events;
406
  int serviced;
407
 
408
  serviced = 0;
409
 
410
  /* Get the interrupt events that caused us to be here.
411
  */
412
  int_events = regs->int_src;
413
  regs->int_src = int_events;
414
 
415
  /* Handle receive event in its own function.
416
  */
417
  if (int_events & (OETH_INT_RXF | OETH_INT_RXE)) {
418
    serviced |= 0x1;
419
    oeth_rx();
420
  }
421
 
422
  /* Handle transmit event in its own function.
423
  */
424
  if (int_events & (OETH_INT_TXB | OETH_INT_TXE)) {
425
    serviced |= 0x2;
426
    oeth_tx();
427
    serviced |= 0x2;
428
 
429
  }
430
 
431
  /* Check for receive busy, i.e. packets coming but no place to
432
  * put them.
433
  */
434
  if (int_events & OETH_INT_BUSY) {
435
    serviced |= 0x4;
436
    if (!(int_events & (OETH_INT_RXF | OETH_INT_RXE)))
437
      oeth_rx();
438
  }
439
 
440
  return;
441
}
442
 
443
 
444
 
445
static void
446
oeth_rx(void)
447
{
448
  volatile oeth_regs *regs;
449
  regs = (oeth_regs *)(OETH_REG_BASE);
450
 
451
  volatile oeth_bd *rx_bdp;
452
  int   pkt_len, i;
453
  int   bad = 0;
454
 
455
  rx_bdp = ((oeth_bd *)OETH_BD_BASE) + OETH_TXBD_NUM;
456
 
457
 
458
  /* Find RX buffers marked as having received data */
459
  for(i = 0; i < OETH_RXBD_NUM; i++)
460
    {
461
      bad=0;
462
      if(!(rx_bdp[i].len_status & OETH_RX_BD_EMPTY)){ /* Looking for NOT empty buffers desc. */
463
        /* Check status for errors.
464
        */
465
        if (rx_bdp[i].len_status & (OETH_RX_BD_TOOLONG | OETH_RX_BD_SHORT)) {
466
          bad = 1;
467
          report(0xbaad0001);
468
        }
469
        if (rx_bdp[i].len_status & OETH_RX_BD_DRIBBLE) {
470
          bad = 1;
471
          report(0xbaad0002);
472
        }
473
        if (rx_bdp[i].len_status & OETH_RX_BD_CRCERR) {
474
          bad = 1;
475
          report(0xbaad0003);
476
        }
477
        if (rx_bdp[i].len_status & OETH_RX_BD_OVERRUN) {
478
          bad = 1;
479
          report(0xbaad0004);
480
        }
481
        if (rx_bdp[i].len_status & OETH_RX_BD_MISS) {
482
          report(0xbaad0005);
483
        }
484
        if (rx_bdp[i].len_status & OETH_RX_BD_LATECOL) {
485
          bad = 1;
486
          report(0xbaad0006);
487
        }
488
        if (bad) {
489
          rx_bdp[i].len_status &= ~OETH_RX_BD_STATS;
490
          rx_bdp[i].len_status |= OETH_RX_BD_EMPTY;
491
          exit(0xbaaaaaad);
492
 
493
          continue;
494
        }
495
        else {
496
          /* Process the incoming frame.
497
          */
498
          pkt_len = rx_bdp[i].len_status >> 16;
499
 
500
          /* finish up */
501
          rx_bdp[i].len_status &= ~OETH_RX_BD_STATS; /* Clear stats */
502
          rx_bdp[i].len_status |= OETH_RX_BD_EMPTY; /* Mark RX BD as empty */
503
          rx_done++;
504
        }
505
      }
506
    }
507
}
508
 
509
 
510
 
511
static void
512
oeth_tx(void)
513
{
514
  volatile oeth_bd *tx_bd;
515
  int i;
516
 
517
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE; /* Search from beginning*/
518
 
519
  /* Go through the TX buffs, search for one that was just sent */
520
  for(i = 0; i < OETH_TXBD_NUM; i++)
521
    {
522
      /* Looking for buffer NOT ready for transmit. and IRQ enabled */
523
      if( (!(tx_bd[i].len_status & (OETH_TX_BD_READY))) && (tx_bd[i].len_status & (OETH_TX_BD_IRQ)) )
524
        {
525
          /* Single threaded so no chance we have detected a buffer that has had its IRQ bit set but not its BD_READ flag. Maybe this won't work in linux */
526
          tx_bd[i].len_status &= ~OETH_TX_BD_IRQ;
527
 
528
          /* Probably good to check for TX errors here */
529
 
530
          /* set our test variable */
531
          tx_done++;
532
 
533
        }
534
    }
535
  return;
536
}
537
 
538
// A function and defines to fill and transmit a packet
539
#define MAX_TX_BUFFER 1532
540
static char tx_buffer[MAX_TX_BUFFER];
541
 
542
void
543
fill_and_tx_packet(int size)
544
{
545
  int i;
546
 
547
  volatile oeth_regs *regs;
548
  regs = (oeth_regs *)(OETH_REG_BASE);
549
 
550
  volatile oeth_bd *tx_bd;
551
 
552
  tx_bd = (volatile oeth_bd *)OETH_BD_BASE;
553
  tx_bd = (volatile oeth_bd*) &tx_bd[next_tx_buf_num];
554
 
555
  // If it's in use - wait
556
  while ((tx_bd->len_status & OETH_TX_BD_IRQ));
557
 
558
  // Use rand() function to generate data for transmission
559
  // Assumption: ethernet buffer descriptors are 4byte aligned
560
  char* data_b = (char*) tx_bd->addr;
561
  // We will fill with words until there' less than a word to go
562
  int words_to_fill = size / sizeof(unsigned int);
563
 
564
  unsigned int* data_w = (unsigned int*) data_b;
565
 
566
  for(i=0;i<words_to_fill;i++)
567
    data_w[i] = rand();
568
 
569
  // Point data_b to offset wher word fills ended
570
  data_b += (words_to_fill * sizeof(unsigned int));
571
 
572
  int leftover_size = size - (words_to_fill * sizeof(unsigned int));
573
 
574
  for(i=0;i<leftover_size;i++)
575
    {
576
      data_b[i] = rand() & 0xff;
577
    }
578
 
579
  tx_packet((void*)0, size);
580
}
581
 
582
// Send a packet, the very first byte of which will be read by the testbench
583
// and used to indicate which test we'll use.
584
void
585
send_ethmac_rxtx_test_init_packet(char test)
586
{
587
  char cmd_tx_buffer[40];
588
  cmd_tx_buffer[0] = test;
589
  tx_packet(cmd_tx_buffer,  40); // Smallest packet that can be sent (I think)
590
}
591
 
592
// Loop to check if a number is prime by doing mod divide of the number
593
// to test by every number less than it
594
int
595
is_prime_number(unsigned long n)
596
{
597
  unsigned long c;
598
  if (n < 2) return 0;
599
  for(c=2;c<n;c++)
600
    if ((n % c) == 0)
601
      return 0;
602
  return 1;
603
}
604
 
605
 
606
int
607
main ()
608
{
609
  tx_data_pointer = 0;
610
 
611
  /* Initialise handler vector */
612
  int_init();
613
 
614
  /* Install ethernet interrupt handler, it is enabled here too */
615
  int_add(ETH0_IRQ, oeth_interrupt, 0);
616
 
617
  /* Enable interrupts in supervisor register */
618
  cpu_enable_user_interrupts();
619
 
620
  /* Enable CPU timer */
621
  cpu_enable_timer();
622
 
623
  ethmac_setup(); /* Configure MAC, TX/RX BDs and enable RX and TX in MODER */
624
 
625
  /* clear tx_done, the tx interrupt handler will set it when it's been
626
     transmitted */
627
  tx_done = 0;
628
  rx_done = 0;
629
 
630
  ethphy_set_100mbit(0);
631
 
632
  send_ethmac_rxtx_test_init_packet(0xff); // Test value of 0xFF
633
 
634
  //oeth_enable_rx();
635
 
636
#define ETH_TX_MIN_PACKET_SIZE 512
637
#define ETH_TX_NUM_PACKETS (ETH_TX_MIN_PACKET_SIZE + 32)
638
 
639
  unsigned long num_to_check;
640
  for(num_to_check=ETH_TX_MIN_PACKET_SIZE;
641
      num_to_check<ETH_TX_NUM_PACKETS;
642
      num_to_check++)
643
    fill_and_tx_packet(num_to_check);
644
 
645
  oeth_disable_rx();
646
 
647
  // Now for 10mbit mode...
648
  ethphy_set_10mbit(0);
649
 
650
  oeth_enable_rx();
651
 
652
  for(num_to_check=ETH_TX_MIN_PACKET_SIZE;
653
      num_to_check<ETH_TX_NUM_PACKETS;
654
      num_to_check++)
655
    fill_and_tx_packet(num_to_check);
656
 
657
  oeth_disable_rx();
658
 
659
  // Go back to 100-mbit mode
660
  ethphy_set_100mbit(0);
661
 
662
  oeth_enable_rx();
663
 
664
  for(num_to_check=ETH_TX_MIN_PACKET_SIZE;
665
      num_to_check<ETH_TX_NUM_PACKETS;
666
      num_to_check++)
667
    fill_and_tx_packet(num_to_check);
668
 
669
  exit(0x8000000d);
670
 
671
}

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