1 |
568 |
julius |
######################################################################
|
2 |
|
|
#### ####
|
3 |
|
|
#### ORPSoC Xilinx Synthesis Makefile ####
|
4 |
|
|
#### ####
|
5 |
|
|
#### Author(s): ####
|
6 |
|
|
#### - Julius Baxter, julius@opencores.org ####
|
7 |
|
|
#### ####
|
8 |
|
|
#### ####
|
9 |
|
|
######################################################################
|
10 |
|
|
#### ####
|
11 |
|
|
#### Copyright (C) 2009,2010,2011 Authors and OPENCORES.ORG ####
|
12 |
|
|
#### ####
|
13 |
|
|
#### This source file may be used and distributed without ####
|
14 |
|
|
#### restriction provided that this copyright statement is not ####
|
15 |
|
|
#### removed from the file and that any derivative work contains ####
|
16 |
|
|
#### the original copyright notice and the associated disclaimer. ####
|
17 |
|
|
#### ####
|
18 |
|
|
#### This source file is free software; you can redistribute it ####
|
19 |
|
|
#### and/or modify it under the terms of the GNU Lesser General ####
|
20 |
|
|
#### Public License as published by the Free Software Foundation; ####
|
21 |
|
|
#### either version 2.1 of the License, or (at your option) any ####
|
22 |
|
|
#### later version. ####
|
23 |
|
|
#### ####
|
24 |
|
|
#### This source is distributed in the hope that it will be ####
|
25 |
|
|
#### useful, but WITHOUT ANY WARRANTY; without even the implied ####
|
26 |
|
|
#### warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ####
|
27 |
|
|
#### PURPOSE. See the GNU Lesser General Public License for more ####
|
28 |
|
|
#### details. ####
|
29 |
|
|
#### ####
|
30 |
|
|
#### You should have received a copy of the GNU Lesser General ####
|
31 |
|
|
#### Public License along with this source; if not, download it ####
|
32 |
|
|
#### from http://www.opencores.org/lgpl.shtml ####
|
33 |
|
|
#### ####
|
34 |
|
|
######################################################################
|
35 |
|
|
|
36 |
|
|
# Name of the directory we're currently in
|
37 |
|
|
CUR_DIR=$(shell pwd)
|
38 |
|
|
|
39 |
|
|
# We don't want the usbhostslave module to be pulled in during synthesis because
|
40 |
|
|
# we haven't copied the headers to our RTL director
|
41 |
|
|
#COMMON_VERILOG_MODULES_EXCLUDE+= usbhostslave
|
42 |
|
|
|
43 |
|
|
|
44 |
|
|
# The root path of the board build
|
45 |
|
|
BOARD_ROOT ?=$(CUR_DIR)/../../..
|
46 |
|
|
include $(BOARD_ROOT)/Makefile.inc
|
47 |
|
|
|
48 |
|
|
RTL_TOP ?=$(DESIGN_NAME)_top
|
49 |
|
|
|
50 |
|
|
SYN_RUN_DIR=$(BOARD_SYN_DIR)/run
|
51 |
|
|
|
52 |
|
|
TIMESCALE_FILE=timescale.v
|
53 |
|
|
SYNDIR_TIMESCALE_FILE=$(SYN_RUN_DIR)/$(TIMESCALE_FILE)
|
54 |
|
|
$(SYNDIR_TIMESCALE_FILE):
|
55 |
|
|
$(Q)echo "" > $@
|
56 |
|
|
|
57 |
|
|
SYN_VERILOG_DEFINES=synthesis-defines.v
|
58 |
|
|
SYNDIR_SYN_VERILOG_DEFINES=$(SYN_RUN_DIR)/$(SYN_VERILOG_DEFINES)
|
59 |
|
|
$(SYNDIR_SYN_VERILOG_DEFINES):
|
60 |
|
|
$(Q)echo "\`define SYNTHESIS" > $@
|
61 |
|
|
$(Q)echo "\`define XILINX" >> $@
|
62 |
|
|
$(Q)echo "" >> $@
|
63 |
|
|
|
64 |
|
|
GENERATED_DEFINES = $(BOOTROM_VERILOG)
|
65 |
|
|
GENERATED_DEFINES += $(SYNDIR_TIMESCALE_FILE)
|
66 |
|
|
GENERATED_DEFINES += $(SYNDIR_SYN_VERILOG_DEFINES)
|
67 |
|
|
|
68 |
|
|
FPGA_PART ?=xc3sd1800a-fg676-4
|
69 |
|
|
#xc5vlx50-ff676-1
|
70 |
|
|
OPT_MODE ?=Speed
|
71 |
|
|
OPT_LEVEL ?=2
|
72 |
|
|
|
73 |
|
|
XILINX_FLAGS ?=-intstyle silent
|
74 |
|
|
XILINX_XST_FLAGS ?= -power NO -glob_opt AllClockNets -write_timing_constraints NO -cross_clock_analysis NO -slice_utilization_ratio 100 -bram_utilization_ratio 100 -dsp_utilization_ratio 100 -safe_implementation No -fsm_style lut -ram_extract Yes -ram_style Auto -rom_extract Yes -rom_style Auto -auto_bram_packing NO -mux_extract YES -mux_style Auto -decoder_extract YES -priority_extract YES -shreg_extract YES -shift_extract YES -xor_collapse YES -resource_sharing YES -async_to_sync NO -use_dsp48 auto -iobuf YES -max_fanout 1000 -bufg 32 -register_duplication YES -equivalent_register_removal YES -register_balancing No -slice_packing YES -optimize_primitives NO -use_clock_enable Auto -use_sync_set Auto -use_sync_reset Auto -iob Auto -slice_utilization_ratio_maxmargin 5 #-keep_hierarchy YES
|
75 |
|
|
|
76 |
|
|
XCF_FILE=$(DESIGN_NAME).xcf
|
77 |
|
|
XST_FILE=$(DESIGN_NAME).xst
|
78 |
|
|
PRJ_FILE=$(DESIGN_NAME).prj
|
79 |
|
|
NGC_FILE=$(DESIGN_NAME).ngc
|
80 |
|
|
NETLIST_FILE=$(DESIGN_NAME).v
|
81 |
|
|
|
82 |
|
|
|
83 |
|
|
XST_PRJ_FILE_SRC_DECLARE=verilog work
|
84 |
|
|
|
85 |
|
|
print-config:
|
86 |
|
|
$(Q)echo; echo "\t### Synthesis make configuration ###"; echo
|
87 |
|
|
$(Q)echo "\tFPGA_PART="$(FPGA_PART)
|
88 |
|
|
$(Q)echo "\tOPT_MODE="$(OPT_MODE)
|
89 |
|
|
$(Q)echo "\tOTP_LEVEL="$(OPT_LEVEL)
|
90 |
|
|
$(Q)echo "\tXILINX_XST_FLAGS="$(XILINX_XST_FLAGS)
|
91 |
|
|
$(Q)echo
|
92 |
|
|
|
93 |
|
|
all: $(NGC_FILE)
|
94 |
|
|
|
95 |
|
|
# Generate the .xst file
|
96 |
|
|
# See this page for information on options:
|
97 |
|
|
# http://www.xilinx.com/itp/xilinx4/data/docs/xst/command_line5.html
|
98 |
|
|
$(XST_FILE):
|
99 |
|
|
$(Q)echo; echo "\t#### Generating XST file ####"; echo
|
100 |
|
|
$(Q)echo "# XST Script for ORPSoC Synthesis" > $@
|
101 |
|
|
$(Q)echo "# This file is autogenerated - any changes will be overwritten" >> $@
|
102 |
|
|
$(Q)echo "# See the Makefile in syn/xst/bin to make changes" >> $@
|
103 |
|
|
$(Q)echo "run" >> $@
|
104 |
|
|
$(Q)echo "-ifn "$(PRJ_FILE) >> $@
|
105 |
|
|
$(Q)echo "-ifmt mixed" >> $@
|
106 |
|
|
$(Q)echo "-top "$(RTL_TOP) >> $@
|
107 |
|
|
$(Q)echo "-ofmt NGC" >> $@
|
108 |
|
|
$(Q)echo "-ofn "$(NGC_FILE) >> $@
|
109 |
|
|
$(Q)echo "-p "$(FPGA_PART) >> $@
|
110 |
|
|
$(Q)echo "-opt_level "$(OPT_LEVEL) >> $@
|
111 |
|
|
$(Q)echo "-opt_mode "$(OPT_MODE) >> $@
|
112 |
|
|
$(Q)echo "-uc "$(XCF_FILE) >> $@
|
113 |
|
|
# $(Q)echo "elaborate " >> $@
|
114 |
|
|
# $(Q)echo -n "-vlgpath \"" >> $@
|
115 |
|
|
# option missing from XST - wtf?! $(Q)for vlogpath in $(VERILOG_SRC_PATHS); do \
|
116 |
|
|
echo -n $$vlogpath" "; done >> $@
|
117 |
|
|
# $(Q)echo "\"" >> $@
|
118 |
|
|
# Give board then common verilog include paths, hoping xst does a sensible thing
|
119 |
|
|
# and searches them in order.
|
120 |
|
|
$(Q)echo "-vlgincdir { "$(BOARD_RTL_VERILOG_INCLUDE_DIR)" "$(COMMON_RTL_VERILOG_DIR)/include" "$(BOOTROM_SW_DIR) " }" >> $@
|
121 |
|
|
$(Q)echo >> $@
|
122 |
|
|
|
123 |
|
|
# Generate Xilinx project (.prj) file
|
124 |
|
|
$(PRJ_FILE): $(RTL_VERILOG_SRC)
|
125 |
|
|
$(Q)echo; echo "\t#### Generating Xilinx PRJ file ####";
|
126 |
|
|
# $(Q)echo "# Autogenerated XST .prj file" > $@
|
127 |
|
|
# $(Q)echo "# Any changes will be written over." >> $@
|
128 |
|
|
$(Q)for file in $(RTL_VERILOG_SRC); do \
|
129 |
|
|
echo $(XST_PRJ_FILE_SRC_DECLARE) $$file >> $@ ; \
|
130 |
|
|
done
|
131 |
|
|
$(Q)echo >> $@
|
132 |
|
|
$(Q)echo
|
133 |
|
|
|
134 |
|
|
# Constraints file
|
135 |
|
|
$(XCF_FILE):
|
136 |
|
|
$(Q)echo; echo "\t#### Generating Xilinx XCF file ####"; echo
|
137 |
|
|
$(Q)echo "# Autogenerated .xcf file" > $@
|
138 |
|
|
$(Q)echo "#" >> $@
|
139 |
|
|
$(Q)echo "# Not much here, XST is smart enough to determine clocks through DCMs" >> $@
|
140 |
|
|
$(Q)echo "#" >> $@
|
141 |
|
|
$(Q)echo "# 125MHz single-ended. XTAL used as main system clock" >> $@
|
142 |
|
|
$(Q)echo "Net sys_clk_i TNM_NET = sys_clk_i;" >> $@
|
143 |
|
|
$(Q)echo "TIMESPEC TS_sys_clk_i = PERIOD sys_clk_i 8000 ps; # 125MHz" >> $@
|
144 |
|
|
$(Q)echo "# Ignore the reset logic" >> $@
|
145 |
|
|
$(Q)echo "NET rst_n_pad_i* TIG;" >> $@
|
146 |
|
|
$(Q)echo "NET tck_pad_i TNM_NET = tck_pad_i;">> $@
|
147 |
|
|
$(Q)echo "TIMESPEC TS_tck_pad_i = PERIOD tck_pad_i 40 ns;" >> $@
|
148 |
|
|
|
149 |
|
|
|
150 |
|
|
# XST command
|
151 |
|
|
$(NGC_FILE): $(PRJ_FILE) $(XST_FILE) $(XCF_FILE) $(GENERATED_DEFINES)
|
152 |
|
|
$(Q)echo; echo "\t#### Running XST ####"; echo;
|
153 |
638 |
stekern |
$(Q)xst -ifn $(XST_FILE) $(XILINX_FLAGS) $(XST_FLAGS)
|
154 |
568 |
julius |
$(Q)echo
|
155 |
|
|
|
156 |
|
|
netlist: $(NETLIST_FILE)
|
157 |
|
|
|
158 |
|
|
# Netlist generation command
|
159 |
|
|
$(NETLIST_FILE): $(NGC_FILE)
|
160 |
|
|
$(Q)echo; echo "\t#### Generating verilog netlist ####"; echo;
|
161 |
638 |
stekern |
$(Q)netgen -sim -aka -dir . -ofmt verilog $< -w $@
|
162 |
568 |
julius |
|
163 |
|
|
|
164 |
|
|
clean:
|
165 |
|
|
$(Q)rm -rf *.* xst _xmsgs
|
166 |
|
|
|
167 |
|
|
clean-sw:
|
168 |
|
|
$(MAKE) -C $(PROJECT_ROOT)/sw/lib distclean
|
169 |
|
|
|
170 |
|
|
distclean: clean-sw clean
|
171 |
|
|
|
172 |
|
|
|
173 |
|
|
.PRECIOUS : $(NGC_FILE) $(XST_FILE) $(XCF_FILE)
|
174 |
|
|
|