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julius |
////////////////////////////////////////////////////////////////// ////
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//// ////
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//// Common Flash Interface (CFI) controller ////
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//// ////
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//// This file is part of the cfi_ctrl project ////
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//// http://opencores.org/project,cfi_ctrl ////
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//// ////
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//// Description ////
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//// See below ////
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//// ////
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//// To Do: ////
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//// - ////
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//// ////
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//// Author(s): ////
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//// - Julius Baxter, julius@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2011 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.gnu.org/copyleft/lesser.html ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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/*
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Top level of CFI controller with 32-bit Wishbone classic interface
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Intended to be used at about 66MHz with a 32MB CFI flash part with 16-bit
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data interface.
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This module has two configurations - one where it pulls in the CFI control
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engine, which is intended to simplify accesses to a CFI flash, such as block
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unlock, erase, and programming. The alternate configuration is essentially
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mapping Wishbone accesses to the flash's bus.
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CFI Engine Wishbone interface:
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Basic functionality:
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Bits [27:26] decode the operation.
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2'b00 : read/write to the flash memory
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2'b01 : unlock block
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2'b10 : erase block
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2'b11 : block registers, other flash control features
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0xc00_0000 : block status/control register
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bits:
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[0]: r/o : CFI controller busy
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[1]: w/o : clear flash status register
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[2]: w/o : reset flash device and controller
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0xc00_0004 : flash device status register
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bits
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[7:0] : r/o : flash device status register
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0xe00_0000 : read device identifier information
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User is able to access the device identifier information such as:
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offset 0x0 : manufacturer code
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offset 0x2 : device id
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offset bba + 0x4 : block (add increments of 128KB block size)
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offset 0xa : read config register
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See CFI docs for further details (shift offset left by 1)
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0xe01_0000 : CFI query
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User is able to access the CFI query information
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The hex offsets in the CFI spec should be shifted left by one before
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applying to the Wishbone bus.
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Addresses under 0x000_0000 cause direct access to the flash
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Addresses under 0x400_0000 cause the block (addressed in [24:0]) to be unlocked
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Addresses under 0x800_0000 cause the block (addressed in [24:0]) to be erased
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*/
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module cfi_ctrl
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(
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wb_clk_i, wb_rst_i,
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wb_dat_i, wb_adr_i,
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wb_stb_i, wb_cyc_i,
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wb_we_i, wb_sel_i,
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wb_dat_o, wb_ack_o,
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wb_err_o, wb_rty_o,
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flash_dq_io,
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flash_adr_o,
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flash_adv_n_o,
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flash_ce_n_o,
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flash_clk_o,
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flash_oe_n_o,
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flash_rst_n_o,
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flash_wait_i,
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flash_we_n_o,
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flash_wp_n_o
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);
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parameter flash_dq_width = 16;
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parameter flash_adr_width = 24;
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parameter flash_write_cycles = 4; // wlwh/Tclk = 50ns / 15 ns (66Mhz)
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parameter flash_read_cycles = 7; // elqv/Tclk = 95 / 15 ns (66MHz)
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parameter cfi_engine = "ENABLED";
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inout [flash_dq_width-1:0] flash_dq_io;
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output [flash_adr_width-1:0] flash_adr_o;
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output flash_adv_n_o;
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output flash_ce_n_o;
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output flash_clk_o;
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output flash_oe_n_o;
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output flash_rst_n_o;
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input flash_wait_i;
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output flash_we_n_o;
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output flash_wp_n_o;
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input wb_clk_i, wb_rst_i;
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input [31:0] wb_dat_i, wb_adr_i;
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input wb_stb_i, wb_cyc_i,
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wb_we_i;
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input [3:0] wb_sel_i;
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output reg [31:0] wb_dat_o;
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output reg wb_ack_o;
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output wb_err_o, wb_rty_o;
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reg [3:0] wb_state;
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generate
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if (cfi_engine == "ENABLED") begin : cfi_engine_gen
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wire do_rst, do_init, do_readstatus;
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wire do_clearstatus, do_eraseblock, do_write,
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do_read, do_unlockblock;
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/* Track when we have new bus accesses and are currently serving them */
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reg wb_req_in_progress;
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wire wb_req_new;
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always @(posedge wb_clk_i)
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if (wb_rst_i)
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wb_req_in_progress <= 0;
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else if (wb_req_new)
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wb_req_in_progress <= 1'b1;
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else if (wb_ack_o)
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wb_req_in_progress <= 0;
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assign wb_req_new = (wb_stb_i & wb_cyc_i) & !wb_req_in_progress;
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/* Registers for interfacing with the CFI controller */
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reg [15:0] cfi_bus_dat_i;
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wire [15:0] cfi_bus_dat_o;
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reg [23:0] cfi_bus_adr_i;
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wire cfi_bus_ack_o;
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wire cfi_bus_busy_o;
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wire cfi_rw_sel;
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wire cfi_unlock_sel;
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wire cfi_erase_sel;
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wire cfi_scr_sel;
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wire cfi_readstatus_sel;
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wire cfi_clearstatus_sel;
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wire cfi_rst_sel;
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wire cfi_busy_sel;
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wire cfi_readdeviceident_sel;
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wire cfi_cfiquery_sel;
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reg cfi_bus_go;
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reg cfi_first_of_two_accesses;
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assign cfi_rw_sel = wb_adr_i[27:26]==2'b00;
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assign cfi_unlock_sel = wb_adr_i[27:26]==2'b01 && wb_we_i;
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assign cfi_erase_sel = wb_adr_i[27:26]==2'b10 && wb_we_i;
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assign cfi_scr_sel = wb_adr_i[27:26]==2'b11 && wb_adr_i[25:0]==26'd0;
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assign cfi_readstatus_sel = wb_adr_i[27:26]==2'b11 &&
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wb_adr_i[25:0]==26'd4 && !wb_we_i;
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assign cfi_clearstatus_sel = cfi_scr_sel && wb_dat_i[1] && wb_we_i;
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assign cfi_rst_sel = cfi_scr_sel && wb_dat_i[2] && wb_we_i;
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assign cfi_busy_sel = cfi_scr_sel & !wb_we_i;
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assign cfi_readdeviceident_sel = wb_adr_i[27:26]==2'b11 &&
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wb_adr_i[25]==1'b1 && !wb_adr_i[16]==1'b1 &&
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!wb_we_i;
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assign cfi_cfiquery_sel = wb_adr_i[27:26]==2'b11 &&
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wb_adr_i[25]==1'b1 && wb_adr_i[16]==1'b1 &&
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!wb_we_i;
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assign do_rst = cfi_rst_sel & cfi_bus_go;
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assign do_init = 0;
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assign do_readstatus = cfi_readstatus_sel & cfi_bus_go;
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assign do_clearstatus = cfi_clearstatus_sel & cfi_bus_go;
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assign do_eraseblock = cfi_erase_sel & cfi_bus_go;
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assign do_write = cfi_rw_sel & wb_we_i & cfi_bus_go ;
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assign do_read = cfi_rw_sel & !wb_we_i & cfi_bus_go ;
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assign do_unlockblock = cfi_unlock_sel & cfi_bus_go ;
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assign do_readdeviceident = cfi_readdeviceident_sel & cfi_bus_go ;
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assign do_cfiquery = cfi_cfiquery_sel & cfi_bus_go ;
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/* Main statemachine */
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`define WB_FSM_IDLE 0
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`define WB_FSM_CFI_CMD_WAIT 2
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always @(posedge wb_clk_i)
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if (wb_rst_i) begin
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wb_state <= `WB_FSM_IDLE;
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cfi_bus_go <= 0;
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/* Wishbone regs */
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wb_dat_o <= 0;
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wb_ack_o <= 0;
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cfi_first_of_two_accesses <= 0;
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end
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else begin
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case (wb_state)
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`WB_FSM_IDLE: begin
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wb_ack_o <= 0;
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cfi_bus_go <= 0;
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/* Pickup new incoming accesses */
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/* Potentially get into a state where we received a bus request
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but the CFI was still busy so waited. In this case we'll get a
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ACK from the controller and have a new request registered */
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if (wb_req_new) begin
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if (cfi_busy_sel) /* want to read the busy flag */
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begin
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wb_ack_o <= 1;
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wb_dat_o <= {30'd0, cfi_bus_busy_o};
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end
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else if (!cfi_bus_busy_o | (wb_req_in_progress & cfi_bus_ack_o))
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begin
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if (cfi_rw_sel | cfi_unlock_sel | cfi_erase_sel |
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cfi_readstatus_sel | cfi_clearstatus_sel |
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cfi_rst_sel | cfi_readdeviceident_sel |
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cfi_cfiquery_sel)
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begin
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wb_state <= `WB_FSM_CFI_CMD_WAIT;
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cfi_bus_go <= 1;
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if (cfi_rw_sel) begin
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/* Map address onto the 16-bit word bus*/
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/* Reads always do full 32-bits, so adjust
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address accordingly.*/
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/* setup address and number of cycles depending
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on request */
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if (wb_we_i) begin /* Writing */
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/* Only possible to write shorts at a time */
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cfi_bus_dat_i <= wb_sel_i[1:0]==2'b11 ?
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wb_dat_i[15:0] :
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wb_dat_i[31:16];
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cfi_bus_adr_i[23:0] <= wb_adr_i[24:1];
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end
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else begin /* Reading */
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/* Full or part word? */
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if ((&wb_sel_i)) begin /* 32-bits */
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cfi_first_of_two_accesses <= 1;
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cfi_bus_adr_i[23:0] <= {wb_adr_i[24:2],1'b0};
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end
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else begin /*16-bits or byte */
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cfi_bus_adr_i[23:0] <= {wb_adr_i[24:1]};
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end
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end
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end
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if (cfi_unlock_sel | cfi_erase_sel)
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cfi_bus_adr_i[23:0] <= wb_adr_i[24:1];
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if (cfi_readdeviceident_sel)
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cfi_bus_adr_i[23:0] <= {wb_adr_i[24:17],1'b0,
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7'd0,wb_adr_i[9:1]};
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if (cfi_cfiquery_sel)
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cfi_bus_adr_i[23:0] <= {14'd0,wb_adr_i[10:1]};
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end // if (cfi_rw_sel | cfi_unlock_sel | ...
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end // if (!cfi_bus_busy_o | (wb_req_in_progress & ...
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end // if (wb_req_new)
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end // case: `WB_FSM_IDLE
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`WB_FSM_CFI_CMD_WAIT: begin
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cfi_bus_go <= 0;
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/* Wait for the CFI controller to do its thing */
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if (cfi_bus_ack_o) begin
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if (cfi_rw_sel) begin
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/* Is this the first of two accesses? */
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if (cfi_first_of_two_accesses) begin
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cfi_bus_adr_i <= cfi_bus_adr_i+1;
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cfi_first_of_two_accesses <= 0;
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cfi_bus_go <= 1;
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/* Dealing with a read or a write */
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/*
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if (wb_we_i)
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cfi_bus_dat_i <= wb_dat_i[31:16];
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else
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*/
|
| 317 |
|
|
wb_dat_o[31:16] <= cfi_bus_dat_o;
|
| 318 |
|
|
end
|
| 319 |
|
|
else begin
|
| 320 |
|
|
wb_state <= `WB_FSM_IDLE;
|
| 321 |
|
|
wb_ack_o <= 1'b1;
|
| 322 |
|
|
if (!wb_we_i) begin
|
| 323 |
|
|
if (&wb_sel_i)
|
| 324 |
|
|
wb_dat_o[15:0] <= cfi_bus_dat_o;
|
| 325 |
|
|
else begin
|
| 326 |
|
|
case (wb_sel_i)
|
| 327 |
|
|
4'b0001 :
|
| 328 |
|
|
wb_dat_o[31:0] <= {4{cfi_bus_dat_o[7:0]}};
|
| 329 |
|
|
4'b0010:
|
| 330 |
|
|
wb_dat_o[31:0] <= {4{cfi_bus_dat_o[15:8]}};
|
| 331 |
|
|
4'b0011 :
|
| 332 |
|
|
wb_dat_o[31:0] <= {cfi_bus_dat_o,cfi_bus_dat_o};
|
| 333 |
|
|
4'b0100 :
|
| 334 |
|
|
wb_dat_o[31:0] <= {4{cfi_bus_dat_o[7:0]}};
|
| 335 |
|
|
4'b1100 :
|
| 336 |
|
|
wb_dat_o[31:0] <= {cfi_bus_dat_o,cfi_bus_dat_o};
|
| 337 |
|
|
4'b1000 :
|
| 338 |
|
|
wb_dat_o[31:0] <= {4{cfi_bus_dat_o[15:8]}};
|
| 339 |
|
|
endcase // case (wb_sel_i)
|
| 340 |
|
|
end
|
| 341 |
|
|
|
| 342 |
|
|
|
| 343 |
|
|
end
|
| 344 |
|
|
end // else: !if(cfi_first_of_two_accesses)
|
| 345 |
|
|
end // if (cfi_rw_sel)
|
| 346 |
|
|
else begin
|
| 347 |
|
|
/* All other accesses should be a single go of the CFI
|
| 348 |
|
|
controller */
|
| 349 |
|
|
wb_state <= `WB_FSM_IDLE;
|
| 350 |
|
|
wb_ack_o <= 1'b1;
|
| 351 |
|
|
/* Get the read status data out */
|
| 352 |
|
|
if (cfi_readstatus_sel)
|
| 353 |
|
|
wb_dat_o <= {4{cfi_bus_dat_o[7:0]}};
|
| 354 |
|
|
if (cfi_readdeviceident_sel | cfi_cfiquery_sel)
|
| 355 |
|
|
wb_dat_o <= {2{cfi_bus_dat_o[15:0]}};
|
| 356 |
|
|
end
|
| 357 |
|
|
end // if (cfi_bus_ack_o)
|
| 358 |
|
|
else if (cfi_rst_sel)begin
|
| 359 |
|
|
/* The reset command won't ACK back over the bus, incase
|
| 360 |
|
|
the FSM hung and it actually reset all of its internals */
|
| 361 |
|
|
wb_state <= `WB_FSM_IDLE;
|
| 362 |
|
|
wb_ack_o <= 1'b1;
|
| 363 |
|
|
end
|
| 364 |
|
|
end // case: `WB_FSM_CFI_CMD_WAIT
|
| 365 |
|
|
endcase // case (wb_state)
|
| 366 |
|
|
end // else: !if(wb_rst_i)
|
| 367 |
|
|
|
| 368 |
|
|
assign wb_err_o = 0;
|
| 369 |
|
|
assign wb_rty_o = 0;
|
| 370 |
|
|
|
| 371 |
|
|
cfi_ctrl_engine
|
| 372 |
|
|
# (.cfi_part_wlwh_cycles(flash_write_cycles),
|
| 373 |
|
|
.cfi_part_elqv_cycles(flash_read_cycles)
|
| 374 |
|
|
)
|
| 375 |
|
|
cfi_ctrl_engine0
|
| 376 |
|
|
(
|
| 377 |
|
|
.clk_i(wb_clk_i),
|
| 378 |
|
|
.rst_i(wb_rst_i),
|
| 379 |
|
|
|
| 380 |
|
|
.do_rst_i(do_rst),
|
| 381 |
|
|
.do_init_i(do_init),
|
| 382 |
|
|
.do_readstatus_i(do_readstatus),
|
| 383 |
|
|
.do_clearstatus_i(do_clearstatus),
|
| 384 |
|
|
.do_eraseblock_i(do_eraseblock),
|
| 385 |
|
|
.do_unlockblock_i(do_unlockblock),
|
| 386 |
|
|
.do_write_i(do_write),
|
| 387 |
|
|
.do_read_i(do_read),
|
| 388 |
|
|
.do_readdeviceident_i(do_readdeviceident),
|
| 389 |
|
|
.do_cfiquery_i(do_cfiquery),
|
| 390 |
|
|
|
| 391 |
|
|
.bus_dat_o(cfi_bus_dat_o),
|
| 392 |
|
|
.bus_dat_i(cfi_bus_dat_i),
|
| 393 |
|
|
.bus_adr_i(cfi_bus_adr_i),
|
| 394 |
|
|
.bus_req_done_o(cfi_bus_ack_o),
|
| 395 |
|
|
.bus_busy_o(cfi_bus_busy_o),
|
| 396 |
|
|
|
| 397 |
|
|
.flash_dq_io(flash_dq_io),
|
| 398 |
|
|
.flash_adr_o(flash_adr_o),
|
| 399 |
|
|
.flash_adv_n_o(flash_adv_n_o),
|
| 400 |
|
|
.flash_ce_n_o(flash_ce_n_o),
|
| 401 |
|
|
.flash_clk_o(flash_clk_o),
|
| 402 |
|
|
.flash_oe_n_o(flash_oe_n_o),
|
| 403 |
|
|
.flash_rst_n_o(flash_rst_n_o),
|
| 404 |
|
|
.flash_wait_i(flash_wait_i),
|
| 405 |
|
|
.flash_we_n_o(flash_we_n_o),
|
| 406 |
|
|
.flash_wp_n_o(flash_wp_n_o)
|
| 407 |
|
|
|
| 408 |
|
|
);
|
| 409 |
|
|
end // if (cfi_engine == "ENABLED")
|
| 410 |
|
|
else begin : cfi_simple
|
| 411 |
|
|
|
| 412 |
|
|
reg long_read;
|
| 413 |
|
|
reg [4:0] flash_ctr;
|
| 414 |
|
|
reg [3:0] wb_state;
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
|
|
reg [flash_dq_width-1:0] flash_dq_o_r;
|
| 418 |
|
|
reg [flash_adr_width-1:0] flash_adr_o_r;
|
| 419 |
|
|
reg flash_oe_n_o_r;
|
| 420 |
|
|
reg flash_we_n_o_r;
|
| 421 |
|
|
reg flash_rst_n_o_r;
|
| 422 |
|
|
wire our_flash_oe;
|
| 423 |
|
|
|
| 424 |
|
|
assign flash_ce_n_o = 0;
|
| 425 |
|
|
assign flash_clk_o = 1;
|
| 426 |
|
|
assign flash_rst_n_o = flash_rst_n_o_r;
|
| 427 |
|
|
assign flash_wp_n_o = 1;
|
| 428 |
|
|
assign flash_adv_n_o = 0;
|
| 429 |
|
|
assign flash_dq_io = (our_flash_oe) ? flash_dq_o_r :
|
| 430 |
|
|
{flash_dq_width{1'bz}};
|
| 431 |
|
|
assign flash_adr_o = flash_adr_o_r;
|
| 432 |
|
|
assign flash_oe_n_o = flash_oe_n_o_r;
|
| 433 |
|
|
assign flash_we_n_o = flash_we_n_o_r;
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
`define WB_STATE_IDLE 0
|
| 437 |
|
|
`define WB_STATE_WAIT 1
|
| 438 |
|
|
|
| 439 |
|
|
assign our_flash_oe = (wb_state == `WB_STATE_WAIT ||
|
| 440 |
|
|
wb_ack_o) & wb_we_i;
|
| 441 |
|
|
|
| 442 |
|
|
always @(posedge wb_clk_i)
|
| 443 |
|
|
if (wb_rst_i)
|
| 444 |
|
|
begin
|
| 445 |
|
|
wb_ack_o <= 0;
|
| 446 |
|
|
wb_dat_o <= 0;
|
| 447 |
|
|
wb_state <= `WB_STATE_IDLE;
|
| 448 |
|
|
flash_dq_o_r <= 0;
|
| 449 |
|
|
flash_adr_o_r <= 0;
|
| 450 |
|
|
flash_oe_n_o_r <= 1;
|
| 451 |
|
|
flash_we_n_o_r <= 1;
|
| 452 |
|
|
flash_rst_n_o_r <= 0; /* active */
|
| 453 |
|
|
long_read <= 0;
|
| 454 |
|
|
flash_ctr <= 0;
|
| 455 |
|
|
|
| 456 |
|
|
end
|
| 457 |
|
|
else begin
|
| 458 |
|
|
if (|flash_ctr)
|
| 459 |
|
|
flash_ctr <= flash_ctr - 1;
|
| 460 |
|
|
|
| 461 |
|
|
case(wb_state)
|
| 462 |
|
|
`WB_STATE_IDLE: begin
|
| 463 |
|
|
/* reset some signals to NOP status */
|
| 464 |
|
|
wb_ack_o <= 0;
|
| 465 |
|
|
flash_oe_n_o_r <= 1;
|
| 466 |
|
|
flash_we_n_o_r <= 1;
|
| 467 |
|
|
flash_rst_n_o_r <= 1;
|
| 468 |
|
|
|
| 469 |
|
|
if (wb_stb_i & wb_cyc_i & !wb_ack_o) begin
|
| 470 |
|
|
flash_adr_o_r <= wb_adr_i[flash_adr_width:1];
|
| 471 |
|
|
wb_state <= `WB_STATE_WAIT;
|
| 472 |
|
|
if (wb_adr_i[27]) begin
|
| 473 |
|
|
/* Reset the flash, no matter the access */
|
| 474 |
|
|
flash_rst_n_o_r <= 0;
|
| 475 |
|
|
flash_ctr <= 5'd16;
|
| 476 |
|
|
end
|
| 477 |
|
|
else if (wb_we_i) begin
|
| 478 |
|
|
/* load counter with write cycle counter */
|
| 479 |
|
|
flash_ctr <= flash_write_cycles - 1;
|
| 480 |
|
|
/* flash bus write command */
|
| 481 |
|
|
flash_we_n_o_r <= 0;
|
| 482 |
|
|
flash_dq_o_r <= (|wb_sel_i[3:2]) ? wb_dat_i[31:16] :
|
| 483 |
|
|
wb_dat_i[15:0];
|
| 484 |
|
|
end
|
| 485 |
|
|
else begin
|
| 486 |
|
|
/* load counter with write cycle counter */
|
| 487 |
|
|
flash_ctr <= flash_read_cycles - 1;
|
| 488 |
|
|
if (&wb_sel_i)
|
| 489 |
|
|
long_read <= 1; // Full 32-bit read, 2 read cycles
|
| 490 |
|
|
flash_oe_n_o_r <= 0;
|
| 491 |
|
|
end // else: !if(wb_we_i)
|
| 492 |
|
|
end // if (wb_stb_i & wb_cyc_i)
|
| 493 |
|
|
|
| 494 |
|
|
end
|
| 495 |
|
|
`WB_STATE_WAIT: begin
|
| 496 |
|
|
if (!(|flash_ctr)) begin
|
| 497 |
|
|
if (wb_we_i) begin
|
| 498 |
|
|
/* write finished */
|
| 499 |
|
|
wb_ack_o <= 1;
|
| 500 |
|
|
wb_state <= `WB_STATE_IDLE;
|
| 501 |
|
|
flash_we_n_o_r <= 1;
|
| 502 |
|
|
end
|
| 503 |
|
|
else begin
|
| 504 |
|
|
/* read finished */
|
| 505 |
|
|
if (!(&wb_sel_i)) /* short or byte read */ begin
|
| 506 |
|
|
case (wb_sel_i)
|
| 507 |
|
|
4'b0001,
|
| 508 |
|
|
4'b0100:
|
| 509 |
|
|
wb_dat_o <= {4{flash_dq_io[7:0]}};
|
| 510 |
|
|
4'b1000,
|
| 511 |
|
|
4'b0010:
|
| 512 |
|
|
wb_dat_o <= {4{flash_dq_io[15:8]}};
|
| 513 |
|
|
default:
|
| 514 |
|
|
wb_dat_o <= {2{flash_dq_io}};
|
| 515 |
|
|
endcase // case (wb_sel_i)
|
| 516 |
|
|
wb_state <= `WB_STATE_IDLE;
|
| 517 |
|
|
wb_ack_o <= 1;
|
| 518 |
|
|
flash_oe_n_o_r <= 1;
|
| 519 |
|
|
end
|
| 520 |
|
|
else if (long_read) begin
|
| 521 |
|
|
/* now go on to read next word */
|
| 522 |
|
|
wb_dat_o[31:16] <= flash_dq_io;
|
| 523 |
|
|
long_read <= 0;
|
| 524 |
|
|
flash_ctr <= flash_read_cycles;
|
| 525 |
|
|
flash_adr_o_r <= flash_adr_o_r + 1;
|
| 526 |
|
|
end
|
| 527 |
|
|
else begin
|
| 528 |
|
|
/* finished two-part read */
|
| 529 |
|
|
wb_dat_o[15:0] <= flash_dq_io;
|
| 530 |
|
|
wb_state <= `WB_STATE_IDLE;
|
| 531 |
|
|
wb_ack_o <= 1;
|
| 532 |
|
|
flash_oe_n_o_r <= 1;
|
| 533 |
|
|
end
|
| 534 |
|
|
end
|
| 535 |
|
|
end
|
| 536 |
|
|
end
|
| 537 |
|
|
|
| 538 |
|
|
default:
|
| 539 |
|
|
wb_state <= `WB_STATE_IDLE;
|
| 540 |
|
|
endcase // case (wb_state)
|
| 541 |
|
|
end // else: !if(wb_rst_i)
|
| 542 |
|
|
|
| 543 |
|
|
end // block: cfi_simple
|
| 544 |
|
|
endgenerate
|
| 545 |
|
|
|
| 546 |
|
|
endmodule // cfi_ctrl
|
| 547 |
|
|
|
