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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [clkgen/] [README] - Blame information for rev 534

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Line No. Rev Author Line
1 361 julius
Clock and reset generation module
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This module should be used as the main reset and clock generation module. It
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should have the asynchronous resets and unbuffered clock lines coming in, and
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depending on defines in the main design file, generate the appropriate clocks
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and clock-synchronous resets.
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Currently Actel and Xilinx technlogies are supported. It is unclear if the way
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it is handling clock-configurations depending on boards is ideal, potentially
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it could become very cluttered if further board support is added and this would
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need to be looked at.
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The technology-dependent modules (PLLs, buffers) instantiated here should be
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located under the backend/vendor/rtl paths.
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As mentioned previously, it is unclear if this is the best way to manage the
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task of clock and reset generation, particularly if further specialised clock
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domains wish to be added, however there is some benefit in that it is all
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managed in one place and with the strict rules that all clocks and resets come
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to this module to be generated.

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