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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [clkgen/] [clkgen.v] - Blame information for rev 361

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1 361 julius
//////////////////////////////////////////////////////////////////////
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//
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// clkgen
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//
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// Handles clock and reset generation for rest of design
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//
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//
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// A simple implementation for the main generic ORPSoC simulations
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//
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`include "timescale.v"
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`include "orpsoc-defines.v"
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module clkgen
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  (
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   // Main clocks in, depending on board
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   clk_pad_i,
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   // Wishbone clock and reset out  
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   wb_clk_o,
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   wb_rst_o,
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   // JTAG clock
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`ifdef JTAG_DEBUG
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   tck_pad_i,
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   dbg_tck_o,
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`endif
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   // Asynchronous, active low reset in
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   rst_n_pad_i
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   );
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   input clk_pad_i;
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   output wb_rst_o;
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   output wb_clk_o;
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`ifdef JTAG_DEBUG
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   input  tck_pad_i;
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   output dbg_tck_o;
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`endif
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   // Asynchronous, active low reset (pushbutton, typically)
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   input  rst_n_pad_i;
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   // First, deal with the asychronous reset
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   wire   async_rst;
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   wire   async_rst_n;
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   // An input buffer is usually instantiated here
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   assign async_rst_n = rst_n_pad_i;
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   // Everyone likes active-high reset signals...
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   assign async_rst = ~async_rst_n;
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`ifdef JTAG_DEBUG
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   assign dbg_tck_o = tck_pad_i;
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`endif
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   //
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   // Declare synchronous reset wires here
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   //
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   // An active-low synchronous reset signal (usually a PLL lock signal)
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   wire   sync_rst_n;
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   // An active-low synchronous reset from ethernet PLL
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   wire   sync_eth_rst_n;
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   // Here we just assign "board" clock (really test) to wishbone clock
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   assign wb_clk_o = clk_pad_i;
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   //
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   // Reset generation
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   //
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   //
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   // Reset generation for wishbone
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   reg [15:0]       wb_rst_shr;
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   always @(posedge wb_clk_o or posedge async_rst)
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     if (async_rst)
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       wb_rst_shr <= 16'hffff;
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     else
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       wb_rst_shr <= {wb_rst_shr[14:0], ~(sync_rst_n)};
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   assign wb_rst_o = wb_rst_shr[15];
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endmodule // clkgen

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