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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu.v                                                   ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
// Top module
module dbg_cpu(
                // JTAG signals
                tck_i,
                tdi_i,
                tdo_o,
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
 
                cpu_ce_i,
                crc_match_i,
                crc_en_o,
                shift_crc_o,
                rst_i,
 
                // CPU
                cpu_clk_i,
                cpu_addr_o, cpu_data_i, cpu_data_o, cpu_bp_i, cpu_stall_o,
                cpu_stb_o,
                cpu_we_o, cpu_ack_i, cpu_rst_o
 
              );
 
// JTAG signals
input         tck_i;
input         tdi_i;
output        tdo_o;
 
// TAP states
input         shift_dr_i;
input         pause_dr_i;
input         update_dr_i;
 
input         cpu_ce_i;
input         crc_match_i;
output        crc_en_o;
output        shift_crc_o;
input         rst_i;
 
// CPU
input         cpu_clk_i;
output [31:0] cpu_addr_o;
output [31:0] cpu_data_o;
input         cpu_bp_i;
output        cpu_stall_o;
input  [31:0] cpu_data_i;
output        cpu_stb_o;
output        cpu_we_o;
input         cpu_ack_i;
output        cpu_rst_o;
 
reg           cpu_stb_o;
wire          cpu_reg_stall;
reg           tdo_o;
reg           cpu_ack_q;
reg           cpu_ack_csff;
reg           cpu_ack_tck;
 
reg    [31:0] cpu_dat_tmp, cpu_data_dsff;
reg    [31:0] cpu_addr_dsff;
reg           cpu_we_dsff;
reg    [`DBG_CPU_DR_LEN -1 :0] dr;
wire          enable;
wire          cmd_cnt_en;
reg     [`DBG_CPU_CMD_CNT_WIDTH -1:0] cmd_cnt;
wire          cmd_cnt_end;
reg           cmd_cnt_end_q;
reg           addr_len_cnt_en;
reg     [5:0] addr_len_cnt;
wire          addr_len_cnt_end;
reg           addr_len_cnt_end_q;
reg           crc_cnt_en;
reg     [`DBG_CPU_CRC_CNT_WIDTH -1:0] crc_cnt;
wire          crc_cnt_end;
reg           crc_cnt_end_q;
reg           data_cnt_en;
reg    [`DBG_CPU_DATA_CNT_WIDTH:0] data_cnt;
reg    [`DBG_CPU_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
wire          data_cnt_end;
reg           data_cnt_end_q;
reg           crc_match_reg;
 
reg    [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
reg    [`DBG_CPU_ADR_LEN -1:0] adr;
reg    [`DBG_CPU_LEN_LEN -1:0] len;
reg    [`DBG_CPU_LEN_LEN:0]    len_var;
wire   [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg;
reg           start_rd_tck;
reg           rd_tck_started;
reg           start_rd_csff;
reg           start_cpu_rd;
reg           start_cpu_rd_q;
reg           start_wr_tck;
reg           start_wr_csff;
reg           start_cpu_wr;
reg           start_cpu_wr_q;
 
reg           status_cnt_en;
wire          status_cnt_end;
 
wire          half, long;
reg           half_q, long_q;
 
reg [`DBG_CPU_STATUS_CNT_WIDTH -1:0] status_cnt;
 
reg [`DBG_CPU_STATUS_LEN -1:0] status;
 
reg           cpu_overrun, cpu_overrun_csff, cpu_overrun_tck;
reg           underrun_tck;
 
reg           busy_cpu;
reg           busy_tck;
reg           cpu_end;
reg           cpu_end_rst;
reg           cpu_end_rst_csff;
reg           cpu_end_csff;
reg           cpu_end_tck, cpu_end_tck_q;
reg           busy_csff;
reg           latch_data;
reg           update_dr_csff, update_dr_cpu;
wire [`DBG_CPU_CTRL_LEN -1:0] cpu_reg_data_i;
wire                          cpu_reg_we;
 
reg           set_addr, set_addr_csff, set_addr_cpu, set_addr_cpu_q;
wire   [31:0] input_data;
 
wire          len_eq_0;
wire          crc_cnt_31;
 
reg           fifo_full;
reg     [7:0] mem [0:3];
reg           cpu_ce_csff;
reg           mem_ptr_init;
reg [`DBG_CPU_CMD_LEN -1: 0] curr_cmd;
wire          curr_cmd_go;
reg           curr_cmd_go_q;
wire          curr_cmd_wr_comm;
wire          curr_cmd_wr_ctrl;
wire          curr_cmd_rd_comm;
wire          curr_cmd_rd_ctrl;
wire          acc_type_read;
wire          acc_type_write;
 
 
assign enable = cpu_ce_i & shift_dr_i;
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
 
assign curr_cmd_go      = (curr_cmd == `DBG_CPU_GO) && cmd_cnt_end;
assign curr_cmd_wr_comm = (curr_cmd == `DBG_CPU_WR_COMM) && cmd_cnt_end;
assign curr_cmd_wr_ctrl = (curr_cmd == `DBG_CPU_WR_CTRL) && cmd_cnt_end;
assign curr_cmd_rd_comm = (curr_cmd == `DBG_CPU_RD_COMM) && cmd_cnt_end;
assign curr_cmd_rd_ctrl = (curr_cmd == `DBG_CPU_RD_CTRL) && cmd_cnt_end;
 
assign acc_type_read    = (acc_type == `DBG_CPU_READ);
assign acc_type_write   = (acc_type == `DBG_CPU_WRITE);
 
 
 
// Shift register for shifting in and out the data
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      latch_data <=  1'b0;
      dr <=  {`DBG_CPU_DR_LEN{1'b0}};
    end
  else if (curr_cmd_rd_comm && crc_cnt_31)  // Latching data (from internal regs)
    begin
      dr[`DBG_CPU_DR_LEN -1:0] <=  {acc_type, adr, len};
    end
  else if (curr_cmd_rd_ctrl && crc_cnt_31)  // Latching data (from control regs)
    begin
      dr[`DBG_CPU_DR_LEN -1:0] <=  {ctrl_reg, {`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN{1'b0}}};
    end
  else if (acc_type_read && curr_cmd_go && crc_cnt_31)  // Latchind first data (from WB)
    begin
      dr[31:0] <=  input_data[31:0];
      latch_data <=  1'b1;
    end
  else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)
    begin
      case (acc_type)  // synthesis parallel_case full_case
        `DBG_CPU_READ: begin
                      if(long & (~long_q))
                        begin
                          dr[31:0] <=  input_data[31:0];
                          latch_data <=  1'b1;
                        end
                      else if (enable)
                        begin
                          dr[31:0] <=  {dr[30:0], 1'b0};
                          latch_data <=  1'b0;
                        end
        end
        default: begin
 
        end
      endcase
    end
  else if (enable && (!addr_len_cnt_end))
    begin
      dr <=  {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
    end
end
 
 
 
assign cmd_cnt_en = enable & (~cmd_cnt_end);
 
 
// Command counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cmd_cnt <=  {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
  else if (update_dr_i)
    cmd_cnt <=  {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
  else if (cmd_cnt_en)
    cmd_cnt <=  cmd_cnt + 1;
end
 
 
// Assigning current command
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    curr_cmd <=  {`DBG_CPU_CMD_LEN{1'b0}};
  else if (update_dr_i)
    curr_cmd <=  {`DBG_CPU_CMD_LEN{1'b0}};
  else if (cmd_cnt == (`DBG_CPU_CMD_LEN -1))
    curr_cmd <=  {dr[`DBG_CPU_CMD_LEN-2 :0], tdi_i};
end
 
 
// Assigning current command
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    curr_cmd_go_q <=  1'b0;
  else
    curr_cmd_go_q <=  curr_cmd_go;
end
 
 
always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_rd_comm or curr_cmd_rd_ctrl or crc_cnt_end)
begin
  if (enable && (!addr_len_cnt_end))
    begin
      if (cmd_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
        addr_len_cnt_en = 1'b1;
      else if (crc_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
        addr_len_cnt_en = 1'b1;
      else
        addr_len_cnt_en = 1'b0;
    end
  else
    addr_len_cnt_en = 1'b0;
end
 
 
// Address/length counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    addr_len_cnt <=  6'h0;
  else if (update_dr_i)
    addr_len_cnt <=  6'h0;
  else if (addr_len_cnt_en)
    addr_len_cnt <=  addr_len_cnt + 1;
end
 
 
always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
begin
  if (enable && (!data_cnt_end))
    begin
      if (cmd_cnt_end && curr_cmd_go && acc_type_write)
        data_cnt_en = 1'b1;
      else if (crc_cnt_end && curr_cmd_go && acc_type_read)
        data_cnt_en = 1'b1;
      else
        data_cnt_en = 1'b0;
    end
  else
    data_cnt_en = 1'b0;
end
 
 
// Data counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt <=  {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
  else if (update_dr_i)
    data_cnt <=  {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
  else if (data_cnt_en)
    data_cnt <=  data_cnt + 1;
end
 
 
 
// Upper limit. Data counter counts until this value is reached.
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    data_cnt_limit <=  {`DBG_CPU_DATA_CNT_LIM_WIDTH+1{1'b0}};
  else if (update_dr_i)
    data_cnt_limit <=  len + 1;
end
 
 
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
begin
  if (enable && (!crc_cnt_end) && cmd_cnt_end)
    begin
      if (addr_len_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
        crc_cnt_en = 1'b1;
      else if (data_cnt_end && curr_cmd_go && acc_type_write)
        crc_cnt_en = 1'b1;
      else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm || curr_cmd_rd_ctrl))
        crc_cnt_en = 1'b1;
      else
        crc_cnt_en = 1'b0;
    end
  else
    crc_cnt_en = 1'b0;
end
 
 
// crc counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_cnt <=  {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
  else if(crc_cnt_en)
    crc_cnt <=  crc_cnt + 1;
  else if (update_dr_i)
    crc_cnt <=  {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
end
 
assign cmd_cnt_end      = cmd_cnt      == `DBG_CPU_CMD_LEN;
assign addr_len_cnt_end = addr_len_cnt == `DBG_CPU_DR_LEN;
assign crc_cnt_end      = crc_cnt      == `DBG_CPU_CRC_CNT_WIDTH'd32;
assign crc_cnt_31       = crc_cnt      == `DBG_CPU_CRC_CNT_WIDTH'd31;
assign data_cnt_end     = (data_cnt    == {data_cnt_limit, 3'b000});
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      crc_cnt_end_q       <=  1'b0;
      cmd_cnt_end_q       <=  1'b0;
      data_cnt_end_q      <=  1'b0;
      addr_len_cnt_end_q  <=  1'b0;
    end
  else
    begin
      crc_cnt_end_q       <=  crc_cnt_end;
      cmd_cnt_end_q       <=  cmd_cnt_end;
      data_cnt_end_q      <=  data_cnt_end;
      addr_len_cnt_end_q  <=  addr_len_cnt_end;
    end
end
 
 
// Status counter is made of 4 serialy connected registers
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    status_cnt <=  {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
  else if (update_dr_i)
    status_cnt <=  {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
  else if (status_cnt_en)
    status_cnt <=  status_cnt + 1;
end
 
 
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or
          curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or
          acc_type_read or data_cnt_end or addr_len_cnt_end)
begin
  if (enable && (!status_cnt_end))
    begin
      if (crc_cnt_end && (curr_cmd_wr_comm || curr_cmd_wr_ctrl))
        status_cnt_en = 1'b1;
      else if (crc_cnt_end && curr_cmd_go && acc_type_write)
        status_cnt_en = 1'b1;
      else if (data_cnt_end && curr_cmd_go && acc_type_read)
        status_cnt_en = 1'b1;
      else if (addr_len_cnt_end && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
        status_cnt_en = 1'b1;
      else
        status_cnt_en = 1'b0;
    end
  else
    status_cnt_en = 1'b0;
end
 
 
assign status_cnt_end = status_cnt == `DBG_CPU_STATUS_LEN;
 
 
// Latching acc_type, address and length
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      acc_type  <=  {`DBG_CPU_ACC_TYPE_LEN{1'b0}};
      adr       <=  {`DBG_CPU_ADR_LEN{1'b0}};
      len       <=  {`DBG_CPU_LEN_LEN{1'b0}};
      set_addr  <=  1'b0;
    end
  else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
    begin
      acc_type  <=  dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN];
      adr       <=  dr[`DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_LEN_LEN];
      len       <=  dr[`DBG_CPU_LEN_LEN -1:0];
      set_addr  <=  1'b1;
    end
  else if(cpu_end_tck)               // Writing back the address
    begin
      adr  <=  cpu_addr_dsff;
    end
  else
    set_addr <=  1'b0;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    crc_match_reg <=  1'b0;
  else if(crc_cnt_end & (~crc_cnt_end_q))
    crc_match_reg <=  crc_match_i;
end
 
 
// Length counter
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    len_var <=  {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
  else if(update_dr_i)
    len_var <=  len + 'd1;
  else if (start_rd_tck)
    begin
      if (len_var > 4)
        len_var <=  len_var - 'd4;
      else
        len_var <=  {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
    end
end
 
 
assign len_eq_0 = len_var == 'h0;
 
 
assign half = data_cnt[3:0] == 4'd15;
assign long = data_cnt[4:0] == 5'd31;
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      half_q <=   1'b0;
      long_q <=   1'b0;
    end
  else
    begin
      half_q <=  half;
      long_q <=  long;
    end
end
 
 
// Start cpu write cycle
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      start_wr_tck <=  1'b0;
      cpu_dat_tmp <=  32'd0;
    end
  else if (curr_cmd_go && acc_type_write)
    begin
      if (long_q)
        begin
          start_wr_tck <=  1'b1;
          cpu_dat_tmp <=  dr[31:0];
        end
      else
        begin
          start_wr_tck <=  1'b0;
        end
    end
  else
    start_wr_tck <=  1'b0;
end
 
 
// cpu_data_o in WB clk domain
always @ (posedge cpu_clk_i)
begin
  cpu_data_dsff <=  cpu_dat_tmp;
end
 
assign cpu_data_o = cpu_data_dsff;
 
 
// Start cpu read cycle
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    start_rd_tck <=  1'b0;
  else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read)              // First read after cmd is entered
    start_rd_tck <=  1'b1;
  else if ((!start_rd_tck) && curr_cmd_go && acc_type_read  && (!len_eq_0) && (!fifo_full) && (!rd_tck_started) && (!cpu_ack_tck))
    start_rd_tck <=  1'b1;
  else
    start_rd_tck <=  1'b0;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    rd_tck_started <=  1'b0;
  else if (update_dr_i || cpu_end_tck && (!cpu_end_tck_q))
    rd_tck_started <=  1'b0;
  else if (start_rd_tck)
    rd_tck_started <=  1'b1;
end
 
 
 
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      start_rd_csff   <=  1'b0;
      start_cpu_rd    <=  1'b0;
      start_cpu_rd_q  <=  1'b0;
 
      start_wr_csff   <=  1'b0;
      start_cpu_wr    <=  1'b0;
      start_cpu_wr_q  <=  1'b0;
 
      set_addr_csff   <=  1'b0;
      set_addr_cpu    <=  1'b0;
      set_addr_cpu_q  <=  1'b0;
 
      cpu_ack_q       <=  1'b0;
    end
  else
    begin
      start_rd_csff   <=  start_rd_tck;
      start_cpu_rd    <=  start_rd_csff;
      start_cpu_rd_q  <=  start_cpu_rd;
 
      start_wr_csff   <=  start_wr_tck;
      start_cpu_wr    <=  start_wr_csff;
      start_cpu_wr_q  <=  start_cpu_wr;
 
      set_addr_csff   <=  set_addr;
      set_addr_cpu    <=  set_addr_csff;
      set_addr_cpu_q  <=  set_addr_cpu;
 
      cpu_ack_q       <=  cpu_ack_i;
    end
end
 
 
// cpu_stb_o
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    cpu_stb_o <=  1'b0;
  else if (cpu_ack_i)
    cpu_stb_o <=  1'b0;
  else if ((start_cpu_wr && (!start_cpu_wr_q)) || (start_cpu_rd && (!start_cpu_rd_q)))
    cpu_stb_o <=  1'b1;
end
 
 
assign cpu_stall_o = cpu_stb_o | cpu_reg_stall;
 
 
// cpu_addr_o logic
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    cpu_addr_dsff <=  32'h0;
  else if (set_addr_cpu && (!set_addr_cpu_q)) // Setting starting address
    cpu_addr_dsff <=  adr;
  else if (cpu_ack_i && (!cpu_ack_q))
    //cpu_addr_dsff <=  cpu_addr_dsff + 3'd4;
    // Increment by just 1, to allow block reading -- jb 090901
    cpu_addr_dsff <=  cpu_addr_dsff + 'd1;
end
 
 
assign cpu_addr_o = cpu_addr_dsff;
 
 
always @ (posedge cpu_clk_i)
begin
  cpu_we_dsff <=  curr_cmd_go && acc_type_write;
end
 
 
assign cpu_we_o = cpu_we_dsff;
 
 
 
// Logic for detecting end of transaction
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    cpu_end <=  1'b0;
  else if (cpu_ack_i && (!cpu_ack_q))
    cpu_end <=  1'b1;
  else if (cpu_end_rst)
    cpu_end <=  1'b0;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_end_csff  <=  1'b0;
      cpu_end_tck   <=  1'b0;
      cpu_end_tck_q <=  1'b0;
    end
  else
    begin
      cpu_end_csff  <=  cpu_end;
      cpu_end_tck   <=  cpu_end_csff;
      cpu_end_tck_q <=  cpu_end_tck;
    end
end
 
 
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_end_rst_csff <=  1'b0;
      cpu_end_rst      <=  1'b0;
    end
  else
    begin
      cpu_end_rst_csff <=  cpu_end_tck;
      cpu_end_rst      <=  cpu_end_rst_csff;
    end
end
 
 
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    busy_cpu <=  1'b0;
  else if (cpu_end_rst)
    busy_cpu <=  1'b0;
  else if (cpu_stb_o)
    busy_cpu <=  1'b1;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      busy_csff       <=  1'b0;
      busy_tck        <=  1'b0;
 
      update_dr_csff  <=  1'b0;
      update_dr_cpu   <=  1'b0;
    end
  else
    begin
      busy_csff       <=  busy_cpu;
      busy_tck        <=  busy_csff;
 
      update_dr_csff  <=  update_dr_i;
      update_dr_cpu   <=  update_dr_csff;
    end
end
 
 
// Detecting overrun when write operation.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    cpu_overrun <=  1'b0;
  else if(start_cpu_wr && (!start_cpu_wr_q) && cpu_ack_i)
    cpu_overrun <=  1'b1;
  else if(update_dr_cpu) // error remains active until update_dr arrives
    cpu_overrun <=  1'b0;
end
 
 
// Detecting underrun when read operation
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    underrun_tck <=  1'b0;
  else if(latch_data && (!fifo_full) && (!data_cnt_end))
    underrun_tck <=  1'b1;
  else if(update_dr_i) // error remains active until update_dr arrives
    underrun_tck <=  1'b0;
end
 
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_overrun_csff <=  1'b0;
      cpu_overrun_tck  <=  1'b0;
 
      cpu_ack_csff     <=  1'b0;
      cpu_ack_tck      <=  1'b0;
    end
  else
    begin
      cpu_overrun_csff <=  cpu_overrun;
      cpu_overrun_tck  <=  cpu_overrun_csff;
 
      cpu_ack_csff     <=  cpu_ack_i;
      cpu_ack_tck      <=  cpu_ack_csff;
    end
end
 
 
 
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_ce_csff  <=  1'b0;
      mem_ptr_init      <=  1'b0;
    end
  else
    begin
      cpu_ce_csff  <=   cpu_ce_i;
      mem_ptr_init      <=  ~cpu_ce_csff;
    end
end
 
 
// Logic for latching data that is read from cpu
always @ (posedge cpu_clk_i)
begin
  if (cpu_ack_i && (!cpu_ack_q))
    begin
      mem[0] <=  cpu_data_i[31:24];
      mem[1] <=  cpu_data_i[23:16];
      mem[2] <=  cpu_data_i[15:08];
      mem[3] <=  cpu_data_i[07:00];
    end
end
 
 
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
 
 
// Fifo counter and empty/full detection
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    fifo_full <=  1'h0;
  else if (update_dr_i)
    fifo_full <=  1'h0;
  else if (cpu_end_tck && (!cpu_end_tck_q) && (!latch_data) && (!fifo_full))  // incrementing
    fifo_full <=  1'b1;
  else if (!(cpu_end_tck && (!cpu_end_tck_q)) && latch_data && (fifo_full))  // decrementing
    fifo_full <=  1'h0;
end
 
 
 
// TDO multiplexer
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status or addr_len_cnt_end or addr_len_cnt_end_q or curr_cmd_rd_comm or curr_cmd_rd_ctrl)
begin
  if (pause_dr_i)
    begin
    tdo_o = busy_tck;
    end
  else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_wr_ctrl || curr_cmd_go && acc_type_write ))
    begin
      tdo_o = ~crc_match_i;
    end
  else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
    begin
      tdo_o = dr[31];
    end
  else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
    begin
      tdo_o = ~crc_match_reg;
    end
  else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && addr_len_cnt_end && (!addr_len_cnt_end_q))
    begin
      tdo_o = ~crc_match_reg;
    end
  else if ((curr_cmd_rd_comm || curr_cmd_rd_ctrl) && crc_cnt_end && (!addr_len_cnt_end))
    begin
      tdo_o = dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1];
    end
  else if (status_cnt_en)
    begin
      tdo_o = status[3];
    end
  else
    begin
      tdo_o = 1'b0;
    end
end
 
 
// Status register
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
    status <=  {`DBG_CPU_STATUS_LEN{1'b0}};
    end
  else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
    begin
    status <=  {1'b0, 1'b0, cpu_overrun_tck, crc_match_i};
    end
  else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
    begin
    status <=  {1'b0, 1'b0, underrun_tck, crc_match_reg};
    end
  else if (addr_len_cnt_end && (!addr_len_cnt_end) && (curr_cmd_rd_comm || curr_cmd_rd_ctrl))
    begin
    status <=  {1'b0, 1'b0, 1'b0, crc_match_reg};
    end
  else if (shift_dr_i && (!status_cnt_end))
    begin
    status <=  {status[`DBG_CPU_STATUS_LEN -2:0], status[`DBG_CPU_STATUS_LEN -1]};
    end
end
// Following status is shifted out (MSB first):
// 3. bit:          1 if crc is OK, else 0
// 2. bit:          1'b0
// 1. bit:          0
// 0. bit:          1 if overrun occured during write (data couldn't be written fast enough)
//                    or underrun occured during read (data couldn't be read fast enough)
 
 
 
// Connecting cpu registers
assign cpu_reg_we = crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_ctrl;
assign cpu_reg_data_i = dr[`DBG_CPU_DR_LEN -1:`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN];
 
dbg_cpu_registers i_dbg_cpu_registers
  (
    .data_i          (cpu_reg_data_i),
    .we_i            (cpu_reg_we),
    .tck_i           (tck_i),
    .bp_i            (cpu_bp_i),
    .rst_i           (rst_i),
    .cpu_clk_i       (cpu_clk_i),
    .ctrl_reg_o      (ctrl_reg),
    .cpu_stall_o     (cpu_reg_stall),
    .cpu_rst_o       (cpu_rst_o)
  );
 
 
 
 
 
endmodule
 

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Debug Interface. ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42	363	julius
43	6	julius	`// synopsys translate_off`
44			`include "timescale.v"
45			`// synopsys translate_on`
46			`include "dbg_cpu_defines.v"
47
48			`// Top module`
49			`module dbg_cpu(`
50			`// JTAG signals`
51			`tck_i,`
52			`tdi_i,`
53			`tdo_o,`
54
55			`// TAP states`
56			`shift_dr_i,`
57			`pause_dr_i,`
58			`update_dr_i,`
59
60			`cpu_ce_i,`
61			`crc_match_i,`
62			`crc_en_o,`
63			`shift_crc_o,`
64			`rst_i,`
65
66			`// CPU`
67			`cpu_clk_i,`
68			`cpu_addr_o, cpu_data_i, cpu_data_o, cpu_bp_i, cpu_stall_o,`
69			`cpu_stb_o,`
70			`cpu_we_o, cpu_ack_i, cpu_rst_o`
71
72			`);`
73
74			`// JTAG signals`
75			`input tck_i;`
76			`input tdi_i;`
77			`output tdo_o;`
78
79			`// TAP states`
80			`input shift_dr_i;`
81			`input pause_dr_i;`
82			`input update_dr_i;`
83
84			`input cpu_ce_i;`
85			`input crc_match_i;`
86			`output crc_en_o;`
87			`output shift_crc_o;`
88			`input rst_i;`
89
90			`// CPU`
91			`input cpu_clk_i;`
92			`output [31:0] cpu_addr_o;`
93			`output [31:0] cpu_data_o;`
94			`input cpu_bp_i;`
95			`output cpu_stall_o;`
96			`input [31:0] cpu_data_i;`
97			`output cpu_stb_o;`
98			`output cpu_we_o;`
99			`input cpu_ack_i;`
100			`output cpu_rst_o;`
101
102			`reg cpu_stb_o;`
103			`wire cpu_reg_stall;`
104			`reg tdo_o;`
105			`reg cpu_ack_q;`
106			`reg cpu_ack_csff;`
107			`reg cpu_ack_tck;`
108
109			`reg [31:0] cpu_dat_tmp, cpu_data_dsff;`
110			`reg [31:0] cpu_addr_dsff;`
111			`reg cpu_we_dsff;`
112			reg [`DBG_CPU_DR_LEN -1 :0] dr;
113			`wire enable;`
114			`wire cmd_cnt_en;`
115			reg [`DBG_CPU_CMD_CNT_WIDTH -1:0] cmd_cnt;
116			`wire cmd_cnt_end;`
117			`reg cmd_cnt_end_q;`
118			`reg addr_len_cnt_en;`
119			`reg [5:0] addr_len_cnt;`
120			`wire addr_len_cnt_end;`
121			`reg addr_len_cnt_end_q;`
122			`reg crc_cnt_en;`
123			reg [`DBG_CPU_CRC_CNT_WIDTH -1:0] crc_cnt;
124			`wire crc_cnt_end;`
125			`reg crc_cnt_end_q;`
126			`reg data_cnt_en;`
127			reg [`DBG_CPU_DATA_CNT_WIDTH:0] data_cnt;
128			reg [`DBG_CPU_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
129			`wire data_cnt_end;`
130			`reg data_cnt_end_q;`
131			`reg crc_match_reg;`
132
133			reg [`DBG_CPU_ACC_TYPE_LEN -1:0] acc_type;
134			reg [`DBG_CPU_ADR_LEN -1:0] adr;
135			reg [`DBG_CPU_LEN_LEN -1:0] len;
136			reg [`DBG_CPU_LEN_LEN:0] len_var;
137			wire [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg;
138			`reg start_rd_tck;`
139			`reg rd_tck_started;`
140			`reg start_rd_csff;`
141			`reg start_cpu_rd;`
142			`reg start_cpu_rd_q;`
143			`reg start_wr_tck;`
144			`reg start_wr_csff;`
145			`reg start_cpu_wr;`
146			`reg start_cpu_wr_q;`
147
148			`reg status_cnt_en;`
149			`wire status_cnt_end;`
150
151			`wire half, long;`
152			`reg half_q, long_q;`
153
154			reg [`DBG_CPU_STATUS_CNT_WIDTH -1:0] status_cnt;
155
156			reg [`DBG_CPU_STATUS_LEN -1:0] status;
157
158			`reg cpu_overrun, cpu_overrun_csff, cpu_overrun_tck;`
159			`reg underrun_tck;`
160
161			`reg busy_cpu;`
162			`reg busy_tck;`
163			`reg cpu_end;`
164			`reg cpu_end_rst;`
165			`reg cpu_end_rst_csff;`
166			`reg cpu_end_csff;`
167			`reg cpu_end_tck, cpu_end_tck_q;`
168			`reg busy_csff;`
169			`reg latch_data;`
170			`reg update_dr_csff, update_dr_cpu;`
171			wire [`DBG_CPU_CTRL_LEN -1:0] cpu_reg_data_i;
172			`wire cpu_reg_we;`
173
174			`reg set_addr, set_addr_csff, set_addr_cpu, set_addr_cpu_q;`
175			`wire [31:0] input_data;`
176
177			`wire len_eq_0;`
178			`wire crc_cnt_31;`
179
180			`reg fifo_full;`
181			`reg [7:0] mem [0:3];`
182			`reg cpu_ce_csff;`
183			`reg mem_ptr_init;`
184			reg [`DBG_CPU_CMD_LEN -1: 0] curr_cmd;
185			`wire curr_cmd_go;`
186			`reg curr_cmd_go_q;`
187			`wire curr_cmd_wr_comm;`
188			`wire curr_cmd_wr_ctrl;`
189			`wire curr_cmd_rd_comm;`
190			`wire curr_cmd_rd_ctrl;`
191			`wire acc_type_read;`
192			`wire acc_type_write;`
193
194
195			`assign enable = cpu_ce_i & shift_dr_i;`
196			`assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);`
197			`assign shift_crc_o = enable & status_cnt_end; // Signals dbg module to shift out the CRC`
198
199			assign curr_cmd_go = (curr_cmd == `DBG_CPU_GO) && cmd_cnt_end;
200			assign curr_cmd_wr_comm = (curr_cmd == `DBG_CPU_WR_COMM) && cmd_cnt_end;
201			assign curr_cmd_wr_ctrl = (curr_cmd == `DBG_CPU_WR_CTRL) && cmd_cnt_end;
202			assign curr_cmd_rd_comm = (curr_cmd == `DBG_CPU_RD_COMM) && cmd_cnt_end;
203			assign curr_cmd_rd_ctrl = (curr_cmd == `DBG_CPU_RD_CTRL) && cmd_cnt_end;
204
205			assign acc_type_read = (acc_type == `DBG_CPU_READ);
206			assign acc_type_write = (acc_type == `DBG_CPU_WRITE);
207
208
209
210			`// Shift register for shifting in and out the data`
211			`always @ (posedge tck_i or posedge rst_i)`
212			`begin`
213			`if (rst_i)`
214			`begin`
215	360	julius	`latch_data <= 1'b0;`
216			dr <= {`DBG_CPU_DR_LEN{1'b0}};
217	6	julius	`end`
218			`else if (curr_cmd_rd_comm && crc_cnt_31) // Latching data (from internal regs)`
219			`begin`
220	360	julius	dr[`DBG_CPU_DR_LEN -1:0] <= {acc_type, adr, len};
221	6	julius	`end`
222			`else if (curr_cmd_rd_ctrl && crc_cnt_31) // Latching data (from control regs)`
223			`begin`
224	360	julius	dr[`DBG_CPU_DR_LEN -1:0] <= {ctrl_reg, {`DBG_CPU_DR_LEN -`DBG_CPU_CTRL_LEN{1'b0}}};
225	6	julius	`end`
226			`else if (acc_type_read && curr_cmd_go && crc_cnt_31) // Latchind first data (from WB)`
227			`begin`
228	360	julius	`dr[31:0] <= input_data[31:0];`
229			`latch_data <= 1'b1;`
230	6	julius	`end`
231			`else if (acc_type_read && curr_cmd_go && crc_cnt_end) // Latching data (from WB)`
232			`begin`
233			`case (acc_type) // synthesis parallel_case full_case`
234			`DBG_CPU_READ: begin
235			`if(long & (~long_q))`
236			`begin`
237	360	julius	`dr[31:0] <= input_data[31:0];`
238			`latch_data <= 1'b1;`
239	6	julius	`end`
240	63	julius	`else if (enable)`
241	6	julius	`begin`
242	360	julius	`dr[31:0] <= {dr[30:0], 1'b0};`
243			`latch_data <= 1'b0;`
244	6	julius	`end`
245	363	julius	`end`
246			`default: begin`
247
248			`end`
249	6	julius	`endcase`
250			`end`
251			`else if (enable && (!addr_len_cnt_end))`
252			`begin`
253	360	julius	dr <= {dr[`DBG_CPU_DR_LEN -2:0], tdi_i};
254	6	julius	`end`
255			`end`
256
257
258
259			`assign cmd_cnt_en = enable & (~cmd_cnt_end);`
260
261
262			`// Command counter`
263			`always @ (posedge tck_i or posedge rst_i)`
264			`begin`
265			`if (rst_i)`
266	360	julius	cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
267	6	julius	`else if (update_dr_i)`
268	360	julius	cmd_cnt <= {`DBG_CPU_CMD_CNT_WIDTH{1'b0}};
269	6	julius	`else if (cmd_cnt_en)`
270	363	julius	`cmd_cnt <= cmd_cnt + 1;`
271	6	julius	`end`
272
273
274			`// Assigning current command`
275			`always @ (posedge tck_i or posedge rst_i)`
276			`begin`
277			`if (rst_i)`
278	360	julius	curr_cmd <= {`DBG_CPU_CMD_LEN{1'b0}};
279	6	julius	`else if (update_dr_i)`
280	360	julius	curr_cmd <= {`DBG_CPU_CMD_LEN{1'b0}};
281	6	julius	else if (cmd_cnt == (`DBG_CPU_CMD_LEN -1))
282	360	julius	curr_cmd <= {dr[`DBG_CPU_CMD_LEN-2 :0], tdi_i};
283	6	julius	`end`
284
285
286			`// Assigning current command`
287			`always @ (posedge tck_i or posedge rst_i)`
288			`begin`
289			`if (rst_i)`
290	360	julius	`curr_cmd_go_q <= 1'b0;`
291	6	julius	`else`
292	360	julius	`curr_cmd_go_q <= curr_cmd_go;`
293	6	julius	`end`
294
295
296			`always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_rd_comm or curr_cmd_rd_ctrl or crc_cnt_end)`
297			`begin`
298			`if (enable && (!addr_len_cnt_end))`
299			`begin`
300			`if (cmd_cnt_end && (curr_cmd_wr_comm \|\| curr_cmd_wr_ctrl))`
301			`addr_len_cnt_en = 1'b1;`
302			`else if (crc_cnt_end && (curr_cmd_rd_comm \|\| curr_cmd_rd_ctrl))`
303			`addr_len_cnt_en = 1'b1;`
304			`else`
305			`addr_len_cnt_en = 1'b0;`
306			`end`
307			`else`
308			`addr_len_cnt_en = 1'b0;`
309			`end`
310
311
312			`// Address/length counter`
313			`always @ (posedge tck_i or posedge rst_i)`
314			`begin`
315			`if (rst_i)`
316	360	julius	`addr_len_cnt <= 6'h0;`
317	6	julius	`else if (update_dr_i)`
318	360	julius	`addr_len_cnt <= 6'h0;`
319	6	julius	`else if (addr_len_cnt_en)`
320	363	julius	`addr_len_cnt <= addr_len_cnt + 1;`
321	6	julius	`end`
322
323
324			`always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)`
325			`begin`
326			`if (enable && (!data_cnt_end))`
327			`begin`
328			`if (cmd_cnt_end && curr_cmd_go && acc_type_write)`
329			`data_cnt_en = 1'b1;`
330			`else if (crc_cnt_end && curr_cmd_go && acc_type_read)`
331			`data_cnt_en = 1'b1;`
332			`else`
333			`data_cnt_en = 1'b0;`
334			`end`
335			`else`
336			`data_cnt_en = 1'b0;`
337			`end`
338
339
340			`// Data counter`
341			`always @ (posedge tck_i or posedge rst_i)`
342			`begin`
343			`if (rst_i)`
344	363	julius	data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
345	6	julius	`else if (update_dr_i)`
346	363	julius	data_cnt <= {`DBG_CPU_DATA_CNT_WIDTH+1{1'b0}};
347	6	julius	`else if (data_cnt_en)`
348	363	julius	`data_cnt <= data_cnt + 1;`
349	6	julius	`end`
350
351
352
353			`// Upper limit. Data counter counts until this value is reached.`
354			`always @ (posedge tck_i or posedge rst_i)`
355			`begin`
356			`if (rst_i)`
357	363	julius	data_cnt_limit <= {`DBG_CPU_DATA_CNT_LIM_WIDTH+1{1'b0}};
358	6	julius	`else if (update_dr_i)`
359	363	julius	`data_cnt_limit <= len + 1;`
360	6	julius	`end`
361
362
363			`always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)`
364			`begin`
365			`if (enable && (!crc_cnt_end) && cmd_cnt_end)`
366			`begin`
367			`if (addr_len_cnt_end && (curr_cmd_wr_comm \|\| curr_cmd_wr_ctrl))`
368			`crc_cnt_en = 1'b1;`
369			`else if (data_cnt_end && curr_cmd_go && acc_type_write)`
370			`crc_cnt_en = 1'b1;`
371			`else if (cmd_cnt_end && (curr_cmd_go && acc_type_read \|\| curr_cmd_rd_comm \|\| curr_cmd_rd_ctrl))`
372			`crc_cnt_en = 1'b1;`
373			`else`
374			`crc_cnt_en = 1'b0;`
375			`end`
376			`else`
377			`crc_cnt_en = 1'b0;`
378			`end`
379
380
381			`// crc counter`
382			`always @ (posedge tck_i or posedge rst_i)`
383			`begin`
384			`if (rst_i)`
385	360	julius	crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
386	6	julius	`else if(crc_cnt_en)`
387	363	julius	`crc_cnt <= crc_cnt + 1;`
388	6	julius	`else if (update_dr_i)`
389	360	julius	crc_cnt <= {`DBG_CPU_CRC_CNT_WIDTH{1'b0}};
390	6	julius	`end`
391
392			assign cmd_cnt_end = cmd_cnt == `DBG_CPU_CMD_LEN;
393			assign addr_len_cnt_end = addr_len_cnt == `DBG_CPU_DR_LEN;
394			assign crc_cnt_end = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd32;
395			assign crc_cnt_31 = crc_cnt == `DBG_CPU_CRC_CNT_WIDTH'd31;
396			`assign data_cnt_end = (data_cnt == {data_cnt_limit, 3'b000});`
397
398			`always @ (posedge tck_i or posedge rst_i)`
399			`begin`
400			`if (rst_i)`
401			`begin`
402	360	julius	`crc_cnt_end_q <= 1'b0;`
403			`cmd_cnt_end_q <= 1'b0;`
404			`data_cnt_end_q <= 1'b0;`
405			`addr_len_cnt_end_q <= 1'b0;`
406	6	julius	`end`
407			`else`
408			`begin`
409	360	julius	`crc_cnt_end_q <= crc_cnt_end;`
410			`cmd_cnt_end_q <= cmd_cnt_end;`
411			`data_cnt_end_q <= data_cnt_end;`
412			`addr_len_cnt_end_q <= addr_len_cnt_end;`
413	6	julius	`end`
414			`end`
415
416
417			`// Status counter is made of 4 serialy connected registers`
418			`always @ (posedge tck_i or posedge rst_i)`
419			`begin`
420			`if (rst_i)`
421	360	julius	status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
422	6	julius	`else if (update_dr_i)`
423	360	julius	status_cnt <= {`DBG_CPU_STATUS_CNT_WIDTH{1'b0}};
424	6	julius	`else if (status_cnt_en)`
425	363	julius	`status_cnt <= status_cnt + 1;`
426	6	julius	`end`
427
428
429			`always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_rd_ctrl or`
430			`curr_cmd_wr_comm or curr_cmd_wr_ctrl or curr_cmd_go or acc_type_write or`
431			`acc_type_read or data_cnt_end or addr_len_cnt_end)`
432			`begin`
433			`if (enable && (!status_cnt_end))`
434			`begin`
435			`if (crc_cnt_end && (curr_cmd_wr_comm \|\| curr_cmd_wr_ctrl))`
436			`status_cnt_en = 1'b1;`
437			`else if (crc_cnt_end && curr_cmd_go && acc_type_write)`
438			`status_cnt_en = 1'b1;`
439			`else if (data_cnt_end && curr_cmd_go && acc_type_read)`
440			`status_cnt_en = 1'b1;`
441			`else if (addr_len_cnt_end && (curr_cmd_rd_comm \|\| curr_cmd_rd_ctrl))`
442			`status_cnt_en = 1'b1;`
443			`else`
444			`status_cnt_en = 1'b0;`
445			`end`
446			`else`
447			`status_cnt_en = 1'b0;`
448			`end`
449
450
451			assign status_cnt_end = status_cnt == `DBG_CPU_STATUS_LEN;
452
453
454			`// Latching acc_type, address and length`
455			`always @ (posedge tck_i or posedge rst_i)`
456			`begin`
457			`if (rst_i)`
458			`begin`
459	360	julius	acc_type <= {`DBG_CPU_ACC_TYPE_LEN{1'b0}};
460			adr <= {`DBG_CPU_ADR_LEN{1'b0}};
461			len <= {`DBG_CPU_LEN_LEN{1'b0}};
462			`set_addr <= 1'b0;`
463	6	julius	`end`
464			`else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)`
465			`begin`
466	360	julius	acc_type <= dr[`DBG_CPU_ACC_TYPE_LEN + `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN];
467			adr <= dr[`DBG_CPU_ADR_LEN + `DBG_CPU_LEN_LEN -1 : `DBG_CPU_LEN_LEN];
468			len <= dr[`DBG_CPU_LEN_LEN -1:0];
469			`set_addr <= 1'b1;`
470	6	julius	`end`
471			`else if(cpu_end_tck) // Writing back the address`
472			`begin`
473	360	julius	`adr <= cpu_addr_dsff;`
474	6	julius	`end`
475			`else`
476	360	julius	`set_addr <= 1'b0;`
477	6	julius	`end`
478
479
480			`always @ (posedge tck_i or posedge rst_i)`
481			`begin`
482			`if (rst_i)`
483	360	julius	`crc_match_reg <= 1'b0;`
484	6	julius	`else if(crc_cnt_end & (~crc_cnt_end_q))`
485	360	julius	`crc_match_reg <= crc_match_i;`
486	6	julius	`end`
487
488
489			`// Length counter`
490			`always @ (posedge tck_i or posedge rst_i)`
491			`begin`
492			`if (rst_i)`
493	360	julius	len_var <= {1'b0, {`DBG_CPU_LEN_LEN{1'b0}}};
494	6	julius	`else if(update_dr_i)`
495	363	julius	`len_var <= len + 'd1;`
496	6	julius	`else if (start_rd_tck)`
497			`begin`
498	363	julius	`if (len_var > 4)`
499			`len_var <= len_var - 'd4;`
500	6	julius	`else`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_cpu.v] - Blame information for rev 805