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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_cpu_registers.v] - Blame information for rev 820

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  dbg_cpu_registers.v                                         ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Debug Interface.               ////
////  http://www.opencores.org/projects/DebugInterface/           ////
////                                                              ////
////  Author(s):                                                  ////
////       Igor Mohor (igorm@opencores.org)                       ////
////                                                              ////
////                                                              ////
////  All additional information is avaliable in the README.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 - 2004 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: dbg_cpu_registers.v,v $
// Revision 1.6  2004/03/28 20:27:02  igorm
// New release of the debug interface (3rd. release).
//
// Revision 1.5  2004/03/22 16:35:46  igorm
// Temp version before changing dbg interface.
//
// Revision 1.4  2004/01/25 14:04:18  mohor
// All flipflops are reset.
//
// Revision 1.3  2004/01/22 10:16:08  mohor
// cpu_stall_o activated as soon as bp occurs.
//
// Revision 1.2  2004/01/17 17:01:14  mohor
// Almost finished.
//
// Revision 1.1  2004/01/16 14:53:33  mohor
// *** empty log message ***
//
//
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "dbg_cpu_defines.v"
 
module dbg_cpu_registers  (
                            data_i,
                            we_i,
                            tck_i,
                            bp_i,
                            rst_i,
                            cpu_clk_i,
                            ctrl_reg_o,
                            cpu_stall_o,
                            cpu_rst_o
                          );
 
 
input  [`DBG_CPU_CTRL_LEN -1:0] data_i;
input                   we_i;
input                   tck_i;
input                   bp_i;
input                   rst_i;
input                   cpu_clk_i;
 
output [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg_o;
output                  cpu_stall_o;
output                  cpu_rst_o;
 
reg                     cpu_reset;
wire             [2:1]  cpu_op_out;
 
reg                     stall_bp, stall_bp_csff, stall_bp_tck;
reg                     stall_reg, stall_reg_csff, stall_reg_cpu;
reg                     cpu_reset_csff;
reg                     cpu_rst_o;
 
 
 
// Breakpoint is latched and synchronized. Stall is set and latched.
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if(rst_i)
    stall_bp <=  1'b0;
  else if(bp_i)
    stall_bp <=  1'b1;
  else if(stall_reg_cpu)
    stall_bp <=  1'b0;
end
 
 
// Synchronizing
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    begin
      stall_bp_csff <=  1'b0;
      stall_bp_tck  <=  1'b0;
    end
  else
    begin
      stall_bp_csff <=  stall_bp;
      stall_bp_tck  <=  stall_bp_csff;
    end
end
 
 
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      stall_reg_csff <=  1'b0;
      stall_reg_cpu  <=  1'b0;
    end
  else
    begin
      stall_reg_csff <=  stall_reg;
      stall_reg_cpu  <=  stall_reg_csff;
    end
end
 
 
assign cpu_stall_o = bp_i | stall_bp | stall_reg_cpu;
 
 
// Writing data to the control registers (stall)
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    stall_reg <=  1'b0;
  else if (stall_bp_tck)
    stall_reg <=  1'b1;
  else if (we_i)
    stall_reg <=  data_i[0];
end
 
 
// Writing data to the control registers (reset)
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    cpu_reset  <=  1'b0;
  else if(we_i)
    cpu_reset  <=  data_i[1];
end
 
 
// Synchronizing signals from registers
always @ (posedge cpu_clk_i or posedge rst_i)
begin
  if (rst_i)
    begin
      cpu_reset_csff      <=  1'b0;
      cpu_rst_o           <=  1'b0;
    end
  else
    begin
      cpu_reset_csff      <=  cpu_reset;
      cpu_rst_o           <=  cpu_reset_csff;
    end
end
 
 
 
// Value for read back
assign ctrl_reg_o = {cpu_reset, stall_reg};
 
 
endmodule
 

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// dbg_cpu_registers.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Debug Interface. ////`
7			`//// http://www.opencores.org/projects/DebugInterface/ ////`
8			`//// ////`
9			`//// Author(s): ////`
10			`//// Igor Mohor (igorm@opencores.org) ////`
11			`//// ////`
12			`//// ////`
13			`//// All additional information is avaliable in the README.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2000 - 2004 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42			`//`
43			`// CVS Revision History`
44			`//`
45			`// $Log: dbg_cpu_registers.v,v $`
46			`// Revision 1.6 2004/03/28 20:27:02 igorm`
47			`// New release of the debug interface (3rd. release).`
48			`//`
49			`// Revision 1.5 2004/03/22 16:35:46 igorm`
50			`// Temp version before changing dbg interface.`
51			`//`
52			`// Revision 1.4 2004/01/25 14:04:18 mohor`
53			`// All flipflops are reset.`
54			`//`
55			`// Revision 1.3 2004/01/22 10:16:08 mohor`
56			`// cpu_stall_o activated as soon as bp occurs.`
57			`//`
58			`// Revision 1.2 2004/01/17 17:01:14 mohor`
59			`// Almost finished.`
60			`//`
61			`// Revision 1.1 2004/01/16 14:53:33 mohor`
62			`// * empty log message *`
63			`//`
64			`//`
65			`//`
66
67			`// synopsys translate_off`
68			`include "timescale.v"
69			`// synopsys translate_on`
70			`include "dbg_cpu_defines.v"
71
72			`module dbg_cpu_registers (`
73			`data_i,`
74			`we_i,`
75			`tck_i,`
76			`bp_i,`
77			`rst_i,`
78			`cpu_clk_i,`
79			`ctrl_reg_o,`
80			`cpu_stall_o,`
81			`cpu_rst_o`
82			`);`
83
84
85			input [`DBG_CPU_CTRL_LEN -1:0] data_i;
86			`input we_i;`
87			`input tck_i;`
88			`input bp_i;`
89			`input rst_i;`
90			`input cpu_clk_i;`
91
92			output [`DBG_CPU_CTRL_LEN -1:0]ctrl_reg_o;
93			`output cpu_stall_o;`
94			`output cpu_rst_o;`
95
96			`reg cpu_reset;`
97			`wire [2:1] cpu_op_out;`
98
99			`reg stall_bp, stall_bp_csff, stall_bp_tck;`
100			`reg stall_reg, stall_reg_csff, stall_reg_cpu;`
101			`reg cpu_reset_csff;`
102			`reg cpu_rst_o;`
103
104
105
106			`// Breakpoint is latched and synchronized. Stall is set and latched.`
107			`always @ (posedge cpu_clk_i or posedge rst_i)`
108			`begin`
109			`if(rst_i)`
110	360	julius	`stall_bp <= 1'b0;`
111	6	julius	`else if(bp_i)`
112	360	julius	`stall_bp <= 1'b1;`
113	6	julius	`else if(stall_reg_cpu)`
114	360	julius	`stall_bp <= 1'b0;`
115	6	julius	`end`
116
117
118			`// Synchronizing`
119			`always @ (posedge tck_i or posedge rst_i)`
120			`begin`
121			`if (rst_i)`
122			`begin`
123	360	julius	`stall_bp_csff <= 1'b0;`
124			`stall_bp_tck <= 1'b0;`
125	6	julius	`end`
126			`else`
127			`begin`
128	360	julius	`stall_bp_csff <= stall_bp;`
129			`stall_bp_tck <= stall_bp_csff;`
130	6	julius	`end`
131			`end`
132
133
134			`always @ (posedge cpu_clk_i or posedge rst_i)`
135			`begin`
136			`if (rst_i)`
137			`begin`
138	360	julius	`stall_reg_csff <= 1'b0;`
139			`stall_reg_cpu <= 1'b0;`
140	6	julius	`end`
141			`else`
142			`begin`
143	360	julius	`stall_reg_csff <= stall_reg;`
144			`stall_reg_cpu <= stall_reg_csff;`
145	6	julius	`end`
146			`end`
147
148
149			`assign cpu_stall_o = bp_i \| stall_bp \| stall_reg_cpu;`
150
151
152			`// Writing data to the control registers (stall)`
153			`always @ (posedge tck_i or posedge rst_i)`
154			`begin`
155			`if (rst_i)`
156	360	julius	`stall_reg <= 1'b0;`
157	6	julius	`else if (stall_bp_tck)`
158	360	julius	`stall_reg <= 1'b1;`
159	6	julius	`else if (we_i)`
160	360	julius	`stall_reg <= data_i[0];`
161	6	julius	`end`
162
163
164			`// Writing data to the control registers (reset)`
165			`always @ (posedge tck_i or posedge rst_i)`
166			`begin`
167			`if (rst_i)`
168	360	julius	`cpu_reset <= 1'b0;`
169	6	julius	`else if(we_i)`
170	360	julius	`cpu_reset <= data_i[1];`
171	6	julius	`end`
172
173
174			`// Synchronizing signals from registers`
175			`always @ (posedge cpu_clk_i or posedge rst_i)`
176			`begin`
177			`if (rst_i)`
178			`begin`
179	360	julius	`cpu_reset_csff <= 1'b0;`
180			`cpu_rst_o <= 1'b0;`
181	6	julius	`end`
182			`else`
183			`begin`
184	360	julius	`cpu_reset_csff <= cpu_reset;`
185			`cpu_rst_o <= cpu_reset_csff;`
186	6	julius	`end`
187			`end`
188
189
190
191			`// Value for read back`
192			`assign ctrl_reg_o = {cpu_reset, stall_reg};`
193
194
195			`endmodule`
196

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_cpu_registers.v] - Blame information for rev 820