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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_if.v] - Blame information for rev 584

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1 6 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  dbg_top.v                                                   ////
4
////                                                              ////
5
////                                                              ////
6
////  This file is part of the SoC Debug Interface.               ////
7
////  http://www.opencores.org/projects/DebugInterface/           ////
8
////                                                              ////
9
////  Author(s):                                                  ////
10
////       Igor Mohor (igorm@opencores.org)                       ////
11
////                                                              ////
12
////                                                              ////
13
////  All additional information is avaliable in the README.txt   ////
14
////  file.                                                       ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2000 - 2004 Authors                            ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
//
43
// CVS Revision History
44
//
45
// $Log: dbg_top.v,v $
46
// Revision 1.45  2004/04/01 11:56:59  igorm
47
// Port names and defines for the supported CPUs changed.
48
//
49
// Revision 1.44  2004/03/28 20:27:02  igorm
50
// New release of the debug interface (3rd. release).
51
//
52
// Revision 1.43  2004/03/22 16:35:46  igorm
53
// Temp version before changing dbg interface.
54
//
55
// Revision 1.42  2004/01/30 10:24:31  mohor
56
// Defines WISHBONE_SUPPORTED and CPU_SUPPORTED added. By default both are
57
// turned on.
58
//
59
// Revision 1.41  2004/01/25 14:04:18  mohor
60
// All flipflops are reset.
61
//
62
// Revision 1.40  2004/01/20 14:23:47  mohor
63
// Define name changed.
64
//
65
// Revision 1.39  2004/01/19 07:32:41  simons
66
// Reset values width added because of FV, a good sentence changed because some tools can not handle it.
67
//
68
// Revision 1.38  2004/01/18 09:22:47  simons
69
// Sensitivity list updated.
70
//
71
// Revision 1.37  2004/01/17 17:01:14  mohor
72
// Almost finished.
73
//
74
// Revision 1.36  2004/01/16 14:51:33  mohor
75
// cpu registers added.
76
//
77
// Revision 1.35  2004/01/14 22:59:16  mohor
78
// Temp version.
79
//
80
// Revision 1.34  2003/12/23 15:07:34  mohor
81
// New directory structure. New version of the debug interface.
82
// Files that are not needed removed.
83
//
84
// Revision 1.33  2003/10/23 16:17:01  mohor
85
// CRC logic changed.
86
//
87
// Revision 1.32  2003/09/18 14:00:47  simons
88
// Lower two address lines must be always zero.
89
//
90
// Revision 1.31  2003/09/17 14:38:57  simons
91
// WB_CNTL register added, some syncronization fixes.
92
//
93
// Revision 1.30  2003/08/28 13:55:22  simons
94
// Three more chains added for cpu debug access.
95
//
96
// Revision 1.29  2003/07/31 12:19:49  simons
97
// Multiple cpu support added.
98
//
99
// Revision 1.28  2002/11/06 14:22:41  mohor
100
// Trst signal is not inverted here any more. Inverted on higher layer !!!.
101
//
102
// Revision 1.27  2002/10/10 02:42:55  mohor
103
// WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). 
104
// Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, 
105
// wb_cyc_o is negated.
106
//
107
// Revision 1.26  2002/05/07 14:43:59  mohor
108
// mon_cntl_o signals that controls monitor mux added.
109
//
110
// Revision 1.25  2002/04/22 12:54:11  mohor
111
// Signal names changed to lower case.
112
//
113
// Revision 1.24  2002/04/17 13:17:01  mohor
114
// Intentional error removed.
115
//
116
// Revision 1.23  2002/04/17 11:16:33  mohor
117
// A block for checking possible simulation/synthesis missmatch added.
118
//
119
// Revision 1.22  2002/03/12 10:31:53  mohor
120
// tap_top and dbg_top modules are put into two separate modules. tap_top
121
// contains only tap state machine and related logic. dbg_top contains all
122
// logic necessery for debugging.
123
//
124
// Revision 1.21  2002/03/08 15:28:16  mohor
125
// Structure changed. Hooks for jtag chain added.
126
//
127
// Revision 1.20  2002/02/06 12:23:09  mohor
128
// latched_jtag_ir used when muxing TDO instead of JTAG_IR.
129
//
130
// Revision 1.19  2002/02/05 13:34:51  mohor
131
// Stupid bug that was entered by previous update fixed.
132
//
133
// Revision 1.18  2002/02/05 12:41:01  mohor
134
// trst synchronization is not needed and was removed.
135
//
136
// Revision 1.17  2002/01/25 07:58:35  mohor
137
// IDCODE bug fixed, chains reused to decreas size of core. Data is shifted-in
138
// not filled-in. Tested in hw.
139
//
140
// Revision 1.16  2001/12/20 11:17:26  mohor
141
// TDO and TDO Enable signal are separated into two signals.
142
//
143
// Revision 1.15  2001/12/05 13:28:21  mohor
144
// trst signal is synchronized to wb_clk_i.
145
//
146
// Revision 1.14  2001/11/28 09:36:15  mohor
147
// Register length fixed.
148
//
149
// Revision 1.13  2001/11/27 13:37:43  mohor
150
// CRC is returned when chain selection data is transmitted.
151
//
152
// Revision 1.12  2001/11/26 10:47:09  mohor
153
// Crc generation is different for read or write commands. Small synthesys fixes.
154
//
155
// Revision 1.11  2001/11/14 10:10:41  mohor
156
// Wishbone data latched on wb_clk_i instead of risc_clk.
157
//
158
// Revision 1.10  2001/11/12 01:11:27  mohor
159
// Reset signals are not combined any more.
160
//
161
// Revision 1.9  2001/10/19 11:40:01  mohor
162
// dbg_timescale.v changed to timescale.v This is done for the simulation of
163
// few different cores in a single project.
164
//
165
// Revision 1.8  2001/10/17 10:39:03  mohor
166
// bs_chain_o added.
167
//
168
// Revision 1.7  2001/10/16 10:09:56  mohor
169
// Signal names changed to lowercase.
170
//
171
//
172
// Revision 1.6  2001/10/15 09:55:47  mohor
173
// Wishbone interface added, few fixes for better performance,
174
// hooks for boundary scan testing added.
175
//
176
// Revision 1.5  2001/09/24 14:06:42  mohor
177
// Changes connected to the OpenRISC access (SPR read, SPR write).
178
//
179
// Revision 1.4  2001/09/20 10:11:25  mohor
180
// Working version. Few bugs fixed, comments added.
181
//
182
// Revision 1.3  2001/09/19 11:55:13  mohor
183
// Asynchronous set/reset not used in trace any more.
184
//
185
// Revision 1.2  2001/09/18 14:13:47  mohor
186
// Trace fixed. Some registers changed, trace simplified.
187
//
188
// Revision 1.1.1.1  2001/09/13 13:49:19  mohor
189
// Initial official release.
190
//
191
// Revision 1.3  2001/06/01 22:22:35  mohor
192
// This is a backup. It is not a fully working version. Not for use, yet.
193
//
194
// Revision 1.2  2001/05/18 13:10:00  mohor
195
// Headers changed. All additional information is now avaliable in the README.txt file.
196
//
197
// Revision 1.1.1.1  2001/05/18 06:35:02  mohor
198
// Initial release
199
//
200
//
201
 
202
// synopsys translate_off
203
`include "timescale.v"
204
// synopsys translate_on
205
`include "dbg_defines.v"
206
`include "dbg_cpu_defines.v"
207
 
208
// Top module
209 360 julius
//module dbg_top(
210
module dbg_if( // Renamed by julius
211 6 julius
                // JTAG signals
212
                tck_i,
213
                tdi_i,
214
                tdo_o,
215
                rst_i,
216
 
217
                // TAP states
218
                shift_dr_i,
219
                pause_dr_i,
220
                update_dr_i,
221
 
222
                // Instructions
223
                debug_select_i
224
 
225
 
226
                `ifdef DBG_WISHBONE_SUPPORTED
227
                // WISHBONE common signals
228
                ,
229
                wb_clk_i,
230
 
231
                // WISHBONE master interface
232
                wb_adr_o,
233
                wb_dat_o,
234
                wb_dat_i,
235
                wb_cyc_o,
236
                wb_stb_o,
237
                wb_sel_o,
238
                wb_we_o,
239
                wb_ack_i,
240
                wb_cab_o,
241
                wb_err_i,
242
                wb_cti_o,
243
                wb_bte_o
244
                `endif
245
 
246
                `ifdef DBG_CPU0_SUPPORTED
247
                // CPU signals
248
                ,
249
                cpu0_clk_i,
250
                cpu0_addr_o,
251
                cpu0_data_i,
252
                cpu0_data_o,
253
                cpu0_bp_i,
254
                cpu0_stall_o,
255
                cpu0_stb_o,
256
                cpu0_we_o,
257
                cpu0_ack_i,
258
                cpu0_rst_o
259
                `endif
260
 
261
                `ifdef DBG_CPU1_SUPPORTED
262
                // CPU signals
263
                ,
264
                cpu1_clk_i,
265
                cpu1_addr_o,
266
                cpu1_data_i,
267
                cpu1_data_o,
268
                cpu1_bp_i,
269
                cpu1_stall_o,
270
                cpu1_stb_o,
271
                cpu1_we_o,
272
                cpu1_ack_i,
273
                cpu1_rst_o
274
                `endif
275
 
276
              );
277
 
278
 
279
// JTAG signals
280
input   tck_i;
281
input   tdi_i;
282
output  tdo_o;
283
input   rst_i;
284
 
285
// TAP states
286
input   shift_dr_i;
287
input   pause_dr_i;
288
input   update_dr_i;
289
 
290
// Instructions
291
input   debug_select_i;
292
 
293
`ifdef DBG_WISHBONE_SUPPORTED
294
input         wb_clk_i;
295
output [31:0] wb_adr_o;
296
output [31:0] wb_dat_o;
297
input  [31:0] wb_dat_i;
298
output        wb_cyc_o;
299
output        wb_stb_o;
300
output  [3:0] wb_sel_o;
301
output        wb_we_o;
302
input         wb_ack_i;
303
output        wb_cab_o;
304
input         wb_err_i;
305
output  [2:0] wb_cti_o;
306
output  [1:0] wb_bte_o;
307
 
308
reg           wishbone_module;
309
reg           wishbone_ce;
310
wire          tdi_wb;
311
wire          tdo_wb;
312
wire          crc_en_wb;
313
wire          shift_crc_wb;
314
`else
315
wire          crc_en_wb = 1'b0;
316
wire          shift_crc_wb = 1'b0;
317
`endif
318
 
319
`ifdef DBG_CPU0_SUPPORTED
320
// CPU signals
321
input         cpu0_clk_i;
322
output [31:0] cpu0_addr_o;
323
input  [31:0] cpu0_data_i;
324
output [31:0] cpu0_data_o;
325
input         cpu0_bp_i;
326
output        cpu0_stall_o;
327
output        cpu0_stb_o;
328
output        cpu0_we_o;
329
input         cpu0_ack_i;
330
output        cpu0_rst_o;
331
 
332
reg           cpu0_debug_module;
333
reg           cpu0_ce;
334
wire          cpu0_tdi;
335
wire          cpu0_tdo;
336
wire          cpu0_crc_en;
337
wire          cpu0_shift_crc;
338
`else
339
wire          cpu0_crc_en = 1'b0;
340
wire          cpu0_shift_crc = 1'b0;
341
`endif
342
 
343
`ifdef DBG_CPU1_SUPPORTED
344
input         cpu1_clk_i;
345
output [31:0] cpu1_addr_o;
346
input  [31:0] cpu1_data_i;
347
output [31:0] cpu1_data_o;
348
input         cpu1_bp_i;
349
output        cpu1_stall_o;
350
output        cpu1_stb_o;
351
output        cpu1_we_o;
352
input         cpu1_ack_i;
353
output        cpu1_rst_o;
354
 
355
reg           cpu1_debug_module;
356
reg           cpu1_ce;
357
wire          cpu1_tdi;
358
wire          cpu1_tdo;
359
wire          cpu1_crc_en;
360
wire          cpu1_shift_crc;
361
`else
362
wire          cpu1_crc_en = 1'b0;
363
wire          cpu1_shift_crc = 1'b0;
364
`endif
365
 
366
 
367
reg [`DBG_TOP_DATA_CNT -1:0]        data_cnt;
368
reg [`DBG_TOP_CRC_CNT -1:0]         crc_cnt;
369
reg [`DBG_TOP_STATUS_CNT_WIDTH -1:0]      status_cnt;
370
reg [`DBG_TOP_MODULE_DATA_LEN -1:0]  module_dr;
371
reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id;
372
 
373
wire module_latch_en;
374
wire data_cnt_end;
375
wire crc_cnt_end;
376
wire status_cnt_end;
377
reg  crc_cnt_end_q;
378
reg  module_select;
379
reg  module_select_error;
380
wire crc_out;
381
wire crc_match;
382
 
383
wire data_shift_en;
384
wire selecting_command;
385
 
386
reg tdo_o;
387
 
388
 
389
 
390
 
391
wire shift_crc;
392
 
393
// data counter
394
always @ (posedge tck_i or posedge rst_i)
395
begin
396
  if (rst_i)
397 360 julius
    data_cnt <=  {`DBG_TOP_DATA_CNT{1'b0}};
398 6 julius
  else if(shift_dr_i & (~data_cnt_end))
399 363 julius
    data_cnt <=  data_cnt + 1;
400 6 julius
  else if (update_dr_i)
401 360 julius
    data_cnt <=  {`DBG_TOP_DATA_CNT{1'b0}};
402 6 julius
end
403
 
404
 
405
assign data_cnt_end = data_cnt == `DBG_TOP_MODULE_DATA_LEN;
406
 
407
 
408
// crc counter
409
always @ (posedge tck_i or posedge rst_i)
410
begin
411
  if (rst_i)
412 360 julius
    crc_cnt <=  {`DBG_TOP_CRC_CNT{1'b0}};
413 6 julius
  else if(shift_dr_i & data_cnt_end & (~crc_cnt_end) & module_select)
414 363 julius
    crc_cnt <=  crc_cnt + 1;
415 6 julius
  else if (update_dr_i)
416 360 julius
    crc_cnt <=  {`DBG_TOP_CRC_CNT{1'b0}};
417 6 julius
end
418
 
419
assign crc_cnt_end = crc_cnt == `DBG_TOP_CRC_LEN;
420
 
421
 
422
always @ (posedge tck_i or posedge rst_i)
423
begin
424
  if (rst_i)
425 360 julius
    crc_cnt_end_q  <=  1'b0;
426 6 julius
  else
427 360 julius
    crc_cnt_end_q  <=  crc_cnt_end;
428 6 julius
end
429
 
430
 
431
// status counter
432
always @ (posedge tck_i or posedge rst_i)
433
begin
434
  if (rst_i)
435 360 julius
    status_cnt <=  {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
436 6 julius
  else if(shift_dr_i & crc_cnt_end & (~status_cnt_end))
437 363 julius
    status_cnt <=  status_cnt + 1;
438 6 julius
  else if (update_dr_i)
439 360 julius
    status_cnt <=  {`DBG_TOP_STATUS_CNT_WIDTH{1'b0}};
440 6 julius
end
441
 
442
assign status_cnt_end = status_cnt == `DBG_TOP_STATUS_LEN;
443
 
444
 
445
assign selecting_command = shift_dr_i & (data_cnt == `DBG_TOP_DATA_CNT'h0) & debug_select_i;
446
 
447
 
448
always @ (posedge tck_i or posedge rst_i)
449
begin
450
  if (rst_i)
451 360 julius
    module_select <=  1'b0;
452 6 julius
  else if(selecting_command & tdi_i)       // Chain select
453 360 julius
    module_select <=  1'b1;
454 6 julius
  else if (update_dr_i)
455 360 julius
    module_select <=  1'b0;
456 6 julius
end
457
 
458
/* verilator lint_off COMBDLY */
459
always @ (module_id)
460
begin
461
  `ifdef DBG_CPU0_SUPPORTED
462 360 julius
  cpu0_debug_module  <=  1'b0;
463 6 julius
  `endif
464
  `ifdef DBG_CPU1_SUPPORTED
465 360 julius
  cpu1_debug_module  <=  1'b0;
466 6 julius
  `endif
467
  `ifdef DBG_WISHBONE_SUPPORTED
468 360 julius
  wishbone_module   <=  1'b0;
469 6 julius
  `endif
470 360 julius
  module_select_error    <=  1'b0;
471 6 julius
 
472
  case (module_id)                /* synthesis parallel_case */
473
    `ifdef DBG_CPU0_SUPPORTED
474 360 julius
      `DBG_TOP_CPU0_DEBUG_MODULE     :   cpu0_debug_module   <=  1'b1;
475 6 julius
    `endif
476
    `ifdef DBG_CPU1_SUPPORTED
477 360 julius
      `DBG_TOP_CPU1_DEBUG_MODULE     :   cpu1_debug_module   <=  1'b1;
478 6 julius
    `endif
479
    `ifdef DBG_WISHBONE_SUPPORTED
480 360 julius
      `DBG_TOP_WISHBONE_DEBUG_MODULE :   wishbone_module     <=  1'b1;
481 6 julius
    `endif
482 360 julius
    default                          :   module_select_error <=  1'b1;
483 6 julius
  endcase
484
end
485
/* verilator lint_on COMBDLY */
486
 
487
assign module_latch_en = module_select & crc_cnt_end & (~crc_cnt_end_q);
488
 
489
 
490
always @ (posedge tck_i or posedge rst_i)
491
begin
492
  if (rst_i)
493
    module_id <= {`DBG_TOP_MODULE_ID_LENGTH{1'b1}};
494
  else if(module_latch_en & crc_match)
495 360 julius
    module_id <=  module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0];
496 6 julius
end
497
 
498
 
499
assign data_shift_en = shift_dr_i & (~data_cnt_end);
500
 
501
 
502
always @ (posedge tck_i or posedge rst_i)
503
begin
504
  if (rst_i)
505 363 julius
    module_dr <=  0;
506 6 julius
  else if (data_shift_en)
507 360 julius
    module_dr[`DBG_TOP_MODULE_DATA_LEN -1:0] <=  {module_dr[`DBG_TOP_MODULE_DATA_LEN -2:0], tdi_i};
508 6 julius
end
509
 
510
 
511
// Calculating crc for input data
512
dbg_crc32_d1 i_dbg_crc32_d1_in
513
             (
514
              .data       (tdi_i),
515
              .enable     (shift_dr_i),
516
              .shift      (1'b0),
517
              .rst        (rst_i),
518
              .sync_rst   (update_dr_i),
519
              .crc_out    (),
520
              .clk        (tck_i),
521
              .crc_match  (crc_match)
522
             );
523
 
524
 
525
reg tdo_module_select;
526
wire crc_en;
527
wire crc_en_dbg;
528
reg crc_started;
529
 
530
assign crc_en = crc_en_dbg | crc_en_wb | cpu1_crc_en | cpu0_crc_en;
531
 
532
assign crc_en_dbg = shift_dr_i & crc_cnt_end & (~status_cnt_end);
533
 
534
always @ (posedge tck_i or posedge rst_i)
535
begin
536
  if (rst_i)
537 360 julius
    crc_started <=  1'b0;
538 6 julius
  else if (crc_en)
539 360 julius
    crc_started <=  1'b1;
540 6 julius
  else if (update_dr_i)
541 360 julius
    crc_started <=  1'b0;
542 6 julius
end
543
 
544
 
545
reg tdo_tmp;
546
 
547
 
548
// Calculating crc for input data
549
dbg_crc32_d1 i_dbg_crc32_d1_out
550
             (
551
              .data       (tdo_tmp),
552
              .enable     (crc_en), // enable has priority
553
//              .shift      (1'b0),
554
              .shift      (shift_dr_i & crc_started & (~crc_en)),
555
              .rst        (rst_i),
556
              .sync_rst   (update_dr_i),
557
              .crc_out    (crc_out),
558
              .clk        (tck_i),
559
              .crc_match  ()
560
             );
561
 
562
// Following status is shifted out: 
563
// 1. bit:          0 if crc is OK, else 1
564
// 2. bit:          0 if existing module_id is selected, 1 if non-existing module_id is selected
565
// 3. bit:          0 (always) 
566
// 4. bit:          0 (always)
567
 
568
 
569
always @ (status_cnt or crc_match or module_select_error or crc_out)
570
begin
571
  case (status_cnt)                   /* synthesis full_case parallel_case */
572
    `DBG_TOP_STATUS_CNT_WIDTH'd0  : begin
573
                        tdo_module_select = ~crc_match;
574
                      end
575
    `DBG_TOP_STATUS_CNT_WIDTH'd1  : begin
576
                        tdo_module_select = module_select_error;
577
                      end
578
    `DBG_TOP_STATUS_CNT_WIDTH'd2  : begin
579
                        tdo_module_select = 1'b0;
580
                      end
581
    `DBG_TOP_STATUS_CNT_WIDTH'd3  : begin
582
                        tdo_module_select = 1'b0;
583
                      end
584
    `DBG_TOP_STATUS_CNT_WIDTH'd4  : begin
585
                        tdo_module_select = crc_out;
586
                      end
587
     default : begin    tdo_module_select = 1'b0; end                   //me added
588
  endcase
589
end
590
 
591
 
592
 
593
 
594
assign shift_crc = shift_crc_wb | cpu1_shift_crc | cpu0_shift_crc;
595
 
596
always @ (shift_crc or crc_out or tdo_module_select
597
`ifdef DBG_WISHBONE_SUPPORTED
598
 or wishbone_ce or tdo_wb
599
`endif
600
`ifdef DBG_CPU0_SUPPORTED
601
 or cpu0_ce or cpu0_tdo
602
`endif
603
`ifdef DBG_CPU1_SUPPORTED
604
 or cpu1_ce or cpu1_tdo
605
`endif
606
         )
607
begin
608
  if (shift_crc)          // shifting crc
609
    tdo_tmp = crc_out;
610
  `ifdef DBG_WISHBONE_SUPPORTED
611
  else if (wishbone_ce)   //  shifting data from wb
612
    tdo_tmp = tdo_wb;
613
  `endif
614
  `ifdef DBG_CPU0_SUPPORTED
615
  else if (cpu0_ce)        // shifting data from cpu
616
    tdo_tmp = cpu0_tdo;
617
  `endif
618
  `ifdef DBG_CPU1_SUPPORTED
619
  else if (cpu1_ce)        // shifting data from cpu
620
    tdo_tmp = cpu1_tdo;
621
  `endif
622
  else
623
    tdo_tmp = tdo_module_select;
624
end
625
 
626
 
627
always @ (negedge tck_i)
628
begin
629 360 julius
  tdo_o <=  tdo_tmp;
630 6 julius
end
631
 
632
 
633
 
634
 
635
// Signals for WISHBONE module
636
 
637
 
638
always @ (posedge tck_i or posedge rst_i)
639
begin
640
  if (rst_i)
641
    begin
642
      `ifdef DBG_WISHBONE_SUPPORTED
643 360 julius
      wishbone_ce <=  1'b0;
644 6 julius
      `endif
645
      `ifdef DBG_CPU0_SUPPORTED
646 360 julius
      cpu0_ce <=  1'b0;
647 6 julius
      `endif
648
      `ifdef DBG_CPU1_SUPPORTED
649 360 julius
      cpu1_ce <=  1'b0;
650 6 julius
      `endif
651
    end
652
  else if(selecting_command & (~tdi_i))
653
    begin
654
      `ifdef DBG_WISHBONE_SUPPORTED
655
      if (wishbone_module)      // wishbone CE
656 360 julius
        wishbone_ce <=  1'b1;
657 6 julius
      `endif
658
      `ifdef DBG_CPU0_SUPPORTED
659
      if (cpu0_debug_module)     // CPU CE
660 360 julius
        cpu0_ce <=  1'b1;
661 6 julius
      `endif
662
      `ifdef DBG_CPU1_SUPPORTED
663
      if (cpu1_debug_module)     // CPU CE
664 360 julius
        cpu1_ce <=  1'b1;
665 6 julius
      `endif
666
    end
667
  else if (update_dr_i)
668
    begin
669
      `ifdef DBG_WISHBONE_SUPPORTED
670 360 julius
      wishbone_ce <=  1'b0;
671 6 julius
      `endif
672
      `ifdef DBG_CPU0_SUPPORTED
673 360 julius
      cpu0_ce <=  1'b0;
674 6 julius
      `endif
675
      `ifdef DBG_CPU1_SUPPORTED
676 360 julius
      cpu1_ce <=  1'b0;
677 6 julius
      `endif
678
    end
679
end
680
 
681
 
682
`ifdef DBG_WISHBONE_SUPPORTED
683
assign tdi_wb  = wishbone_ce & tdi_i;
684
`endif
685
 
686
`ifdef DBG_CPU0_SUPPORTED
687
assign cpu0_tdi = cpu0_ce & tdi_i;
688
`endif
689
`ifdef DBG_CPU1_SUPPORTED
690
assign cpu1_tdi = cpu1_ce & tdi_i;
691
`endif
692
 
693
 
694
`ifdef DBG_WISHBONE_SUPPORTED
695
// Connecting wishbone module
696
dbg_wb i_dbg_wb (
697
                  // JTAG signals
698
                  .tck_i            (tck_i),
699
                  .tdi_i            (tdi_wb),
700
                  .tdo_o            (tdo_wb),
701
 
702
                  // TAP states
703
                  .shift_dr_i       (shift_dr_i),
704
                  .pause_dr_i       (pause_dr_i),
705
                  .update_dr_i      (update_dr_i),
706
 
707
                  .wishbone_ce_i    (wishbone_ce),
708
                  .crc_match_i      (crc_match),
709
                  .crc_en_o         (crc_en_wb),
710
                  .shift_crc_o      (shift_crc_wb),
711
                  .rst_i            (rst_i),
712
 
713
                  // WISHBONE common signals
714
                  .wb_clk_i         (wb_clk_i),
715
 
716
                  // WISHBONE master interface
717
                  .wb_adr_o         (wb_adr_o),
718
                  .wb_dat_o         (wb_dat_o),
719
                  .wb_dat_i         (wb_dat_i),
720
                  .wb_cyc_o         (wb_cyc_o),
721
                  .wb_stb_o         (wb_stb_o),
722
                  .wb_sel_o         (wb_sel_o),
723
                  .wb_we_o          (wb_we_o),
724
                  .wb_ack_i         (wb_ack_i),
725
                  .wb_cab_o         (wb_cab_o),
726
                  .wb_err_i         (wb_err_i),
727
                  .wb_cti_o         (wb_cti_o),
728
                  .wb_bte_o         (wb_bte_o)
729
            );
730
`endif
731
 
732
 
733
 
734
`ifdef DBG_CPU0_SUPPORTED
735
dbg_cpu i_dbg_cpu_or1k (
736
                  // JTAG signals
737
                  .tck_i            (tck_i),
738
                  .tdi_i            (cpu0_tdi),
739
                  .tdo_o            (cpu0_tdo),
740
 
741
                  // TAP states
742
                  .shift_dr_i       (shift_dr_i),
743
                  .pause_dr_i       (pause_dr_i),
744
                  .update_dr_i      (update_dr_i),
745
 
746
                  .cpu_ce_i         (cpu0_ce),
747
                  .crc_match_i      (crc_match),
748
                  .crc_en_o         (cpu0_crc_en),
749
                  .shift_crc_o      (cpu0_shift_crc),
750
                  .rst_i            (rst_i),
751
 
752
                  // CPU signals
753
                  .cpu_clk_i        (cpu0_clk_i),
754
                  .cpu_addr_o       (cpu0_addr_o),
755
                  .cpu_data_i       (cpu0_data_i),
756
                  .cpu_data_o       (cpu0_data_o),
757
                  .cpu_bp_i         (cpu0_bp_i),
758
                  .cpu_stall_o      (cpu0_stall_o),
759
                  .cpu_stb_o        (cpu0_stb_o),
760
                  .cpu_we_o         (cpu0_we_o),
761
                  .cpu_ack_i        (cpu0_ack_i),
762
                  .cpu_rst_o        (cpu0_rst_o)
763
              );
764
 
765
`endif  //  DBG_CPU0_SUPPORTED
766
 
767
 
768
 
769
`ifdef DBG_CPU1_SUPPORTED
770
// Connecting cpu module
771
dbg_cpu i_dbg_cpu_8051 (
772
                  // JTAG signals
773
                  .tck_i            (tck_i),
774
                  .tdi_i            (cpu1_tdi),
775
                  .tdo_o            (cpu1_tdo),
776
 
777
                  // TAP states
778
                  .shift_dr_i       (shift_dr_i),
779
                  .pause_dr_i       (pause_dr_i),
780
                  .update_dr_i      (update_dr_i),
781
 
782
                  .cpu_ce_i         (cpu1_ce),
783
                  .crc_match_i      (crc_match),
784
                  .crc_en_o         (cpu1_crc_en),
785
                  .shift_crc_o      (cpu1_shift_crc),
786
                  .rst_i            (rst_i),
787
 
788
                  // CPU signals
789
                  .cpu_clk_i        (cpu1_clk_i),
790
                  .cpu_addr_o       (cpu1_addr_o),
791
                  .cpu_data_i       (cpu1_data_i),
792
                  .cpu_data_o       (cpu1_data_o),
793
                  .cpu_bp_i         (cpu1_bp_i),
794
                  .cpu_stall_o      (cpu1_stall_o),
795
                  .cpu_stb_o        (cpu1_stb_o),
796
                  .cpu_we_o         (cpu1_we_o),
797
                  .cpu_ack_i        (cpu1_ack_i),
798
                  .cpu_rst_o        (cpu1_rst_o)
799
              );
800
`endif
801
 
802
 
803
endmodule

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