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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_register.v] - Blame information for rev 492

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  dbg_register.v                                              ////
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////                                                              ////
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////                                                              ////
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////  This file is part of the SoC Debug Interface.               ////
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////  http://www.opencores.org/projects/DebugInterface/           ////
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////                                                              ////
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////  Author(s):                                                  ////
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////       Igor Mohor (igorm@opencores.org)                       ////
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////                                                              ////
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////                                                              ////
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////  All additional information is avaliable in the README.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 - 2004 Authors                            ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: dbg_register.v,v $
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// Revision 1.10  2004/03/28 20:27:02  igorm
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// New release of the debug interface (3rd. release).
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//
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// Revision 1.9  2004/01/25 14:04:18  mohor
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// All flipflops are reset.
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//
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// Revision 1.8  2004/01/16 14:53:33  mohor
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// *** empty log message ***
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//
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module dbg_register (
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                      data_in,
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                      data_out,
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                      write,
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                      clk,
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                      reset
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                    );
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parameter WIDTH = 8; // default parameter of the register width
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parameter RESET_VALUE = 0;
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input   [WIDTH-1:0] data_in;
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input               write;
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input               clk;
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input               reset;
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output  [WIDTH-1:0] data_out;
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reg     [WIDTH-1:0] data_out;
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always @ (posedge clk or posedge reset)
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begin
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  if(reset)
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    data_out[WIDTH-1:0] <=  RESET_VALUE;
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  else if(write)
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    data_out[WIDTH-1:0] <=  data_in[WIDTH-1:0];
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end
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endmodule   // Register
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