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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [dbg_if/] [dbg_wb.v] - Blame information for rev 862

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1 6 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  dbg_wb.v                                                    ////
4
////                                                              ////
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////                                                              ////
6
////  This file is part of the SoC Debug Interface.               ////
7
////  http://www.opencores.org/projects/DebugInterface/           ////
8
////                                                              ////
9
////  Author(s):                                                  ////
10
////       Igor Mohor (igorm@opencores.org)                       ////
11
////                                                              ////
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////                                                              ////
13
////  All additional information is avaliable in the README.txt   ////
14
////  file.                                                       ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2000 - 2004 Authors                            ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43
// synopsys translate_off
44
`include "timescale.v"
45
// synopsys translate_on
46
`include "dbg_wb_defines.v"
47
 
48
// Top module
49
module dbg_wb(
50
                // JTAG signals
51
                tck_i,
52
                tdi_i,
53
                tdo_o,
54
 
55
                // TAP states
56
                shift_dr_i,
57
                pause_dr_i,
58
                update_dr_i,
59
 
60
                wishbone_ce_i,
61
                crc_match_i,
62
                crc_en_o,
63
                shift_crc_o,
64
                rst_i,
65
 
66
                // WISHBONE common signals
67
                wb_clk_i,
68
 
69
                // WISHBONE master interface
70
                wb_adr_o, wb_dat_o, wb_dat_i, wb_cyc_o, wb_stb_o, wb_sel_o,
71
                wb_we_o, wb_ack_i, wb_cab_o, wb_err_i, wb_cti_o, wb_bte_o
72
 
73
              );
74
 
75
// JTAG signals
76
input         tck_i;
77
input         tdi_i;
78
output        tdo_o;
79
 
80
// TAP states
81
input         shift_dr_i;
82
input         pause_dr_i;
83
input         update_dr_i;
84
 
85
input         wishbone_ce_i;
86
input         crc_match_i;
87
output        crc_en_o;
88
output        shift_crc_o;
89
input         rst_i;
90
// WISHBONE common signals
91
input         wb_clk_i;
92
 
93
// WISHBONE master interface
94
output [31:0] wb_adr_o;
95
output [31:0] wb_dat_o;
96
input  [31:0] wb_dat_i;
97
output        wb_cyc_o;
98
output        wb_stb_o;
99
output  [3:0] wb_sel_o;
100
output        wb_we_o;
101
input         wb_ack_i;
102
output        wb_cab_o;
103
input         wb_err_i;
104
output  [2:0] wb_cti_o;
105
output  [1:0] wb_bte_o;
106
 
107
reg           wb_cyc_o;
108
 
109
reg           tdo_o;
110
 
111
reg    [31:0] wb_dat_tmp, wb_dat_dsff;
112
reg    [31:0] wb_adr_dsff;
113
reg     [3:0] wb_sel_dsff;
114
reg           wb_we_dsff;
115
reg    [`DBG_WB_DR_LEN -1 :0] dr;
116
wire          enable;
117
wire          cmd_cnt_en;
118
reg     [`DBG_WB_CMD_CNT_WIDTH -1:0] cmd_cnt;
119
wire          cmd_cnt_end;
120
reg           cmd_cnt_end_q;
121
reg           addr_len_cnt_en;
122
reg     [5:0] addr_len_cnt;
123
wire          addr_len_cnt_end;
124
reg           addr_len_cnt_end_q;
125
reg           crc_cnt_en;
126
reg     [`DBG_WB_CRC_CNT_WIDTH -1:0] crc_cnt;
127
wire          crc_cnt_end;
128
reg           crc_cnt_end_q;
129
reg           data_cnt_en;
130
reg    [`DBG_WB_DATA_CNT_WIDTH:0] data_cnt;
131
reg    [`DBG_WB_DATA_CNT_LIM_WIDTH:0] data_cnt_limit;
132
wire          data_cnt_end;
133
reg           data_cnt_end_q;
134
 
135
reg           crc_match_reg;
136
 
137
reg    [`DBG_WB_ACC_TYPE_LEN -1:0] acc_type;
138
reg    [`DBG_WB_ADR_LEN -1:0] adr;
139
reg    [`DBG_WB_LEN_LEN -1:0] len;
140
reg    [`DBG_WB_LEN_LEN:0]    len_var;
141
reg           start_rd_tck;
142
reg           rd_tck_started;
143
reg           start_rd_csff;
144
reg           start_wb_rd;
145
reg           start_wb_rd_q;
146
reg           start_wr_tck;
147
reg           start_wr_csff;
148
reg           start_wb_wr;
149
reg           start_wb_wr_q;
150
 
151
reg           status_cnt_en;
152
wire          status_cnt_end;
153
 
154
wire          byte, half, long;
155
reg           byte_q, half_q, long_q;
156
 
157
reg [`DBG_WB_STATUS_CNT_WIDTH -1:0] status_cnt;
158
 
159
reg [`DBG_WB_STATUS_LEN -1:0] status;
160
 
161
reg           wb_error, wb_error_csff, wb_error_tck;
162
reg           wb_overrun, wb_overrun_csff, wb_overrun_tck;
163
reg           underrun_tck;
164
 
165
reg           busy_wb;
166
reg           busy_tck;
167
reg           wb_end;
168
reg           wb_end_rst;
169
reg           wb_end_rst_csff;
170
reg           wb_end_csff;
171
reg           wb_end_tck, wb_end_tck_q;
172
reg           busy_csff;
173
reg           latch_data;
174
reg           update_dr_csff, update_dr_wb;
175
 
176
reg           set_addr, set_addr_csff, set_addr_wb, set_addr_wb_q;
177
wire   [31:0] input_data;
178
 
179
wire          len_eq_0;
180
wire          crc_cnt_31;
181
 
182
reg     [1:0] ptr;
183
reg     [2:0] fifo_cnt;
184
wire          fifo_full;
185
wire          fifo_empty;
186
reg     [7:0] mem [0:3];
187
reg     [2:0] mem_ptr_dsff;
188
reg           wishbone_ce_csff;
189
reg           mem_ptr_init;
190 363 julius
reg [`DBG_WB_CMD_LEN_INT -1: 0] curr_cmd;
191 6 julius
wire          curr_cmd_go;
192
reg           curr_cmd_go_q;
193
wire          curr_cmd_wr_comm;
194
wire          curr_cmd_rd_comm;
195
wire          acc_type_read;
196
wire          acc_type_write;
197
wire          acc_type_8bit;
198
wire          acc_type_16bit;
199
wire          acc_type_32bit;
200
 
201
 
202
assign enable = wishbone_ce_i & shift_dr_i;
203
assign crc_en_o = enable & crc_cnt_end & (~status_cnt_end);
204
assign shift_crc_o = enable & status_cnt_end;  // Signals dbg module to shift out the CRC
205
 
206
assign curr_cmd_go      = (curr_cmd == `DBG_WB_GO) && cmd_cnt_end;
207
assign curr_cmd_wr_comm = (curr_cmd == `DBG_WB_WR_COMM) && cmd_cnt_end;
208
assign curr_cmd_rd_comm = (curr_cmd == `DBG_WB_RD_COMM) && cmd_cnt_end;
209
 
210
assign acc_type_read    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_READ16  || acc_type == `DBG_WB_READ32);
211
assign acc_type_write   = (acc_type == `DBG_WB_WRITE8 || acc_type == `DBG_WB_WRITE16 || acc_type == `DBG_WB_WRITE32);
212
 
213
assign acc_type_8bit    = (acc_type == `DBG_WB_READ8  || acc_type == `DBG_WB_WRITE8);
214
assign acc_type_16bit   = (acc_type == `DBG_WB_READ16 || acc_type == `DBG_WB_WRITE16);
215
assign acc_type_32bit   = (acc_type == `DBG_WB_READ32 || acc_type == `DBG_WB_WRITE32);
216
 
217
 
218
// Selecting where to take the data from
219
always @ (posedge tck_i or posedge rst_i)
220
begin
221
  if (rst_i)
222 360 julius
    ptr <=  2'h0;
223 6 julius
  else if (update_dr_i)
224 360 julius
    ptr <=  2'h0;
225 6 julius
  else if (curr_cmd_go && acc_type_read && crc_cnt_31) // first latch
226 360 julius
    ptr <=  ptr + 1'b1;
227 6 julius
  else if (curr_cmd_go && acc_type_read && byte && (!byte_q))
228
    ptr <= ptr + 1'd1;
229
end
230
 
231
 
232
// Shift register for shifting in and out the data
233
always @ (posedge tck_i or posedge rst_i)
234
begin
235
  if (rst_i)
236
    begin
237 360 julius
      latch_data <=  1'b0;
238
      dr <=  {`DBG_WB_DR_LEN{1'b0}};
239 6 julius
    end
240
  else if (curr_cmd_rd_comm && crc_cnt_31)  // Latching data (from iternal regs)
241
    begin
242 360 julius
      dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1:0] <=  {acc_type, adr, len};
243 6 julius
    end
244 547 julius
  else if (acc_type_read && curr_cmd_go && crc_cnt_31 && !busy_tck)  // Latchind first data (from WB)
245 6 julius
    begin
246 360 julius
      dr[31:0] <=  input_data[31:0];
247
      latch_data <=  1'b1;
248 6 julius
    end
249 547 julius
  else if (acc_type_read && curr_cmd_go && crc_cnt_end && !busy_tck && wb_end_tck_q)
250 6 julius
    begin
251 547 julius
       // Had to wait for data from WB.
252
       dr[31:0] <=  input_data[31:0];
253
       latch_data <=  1'b1;
254
    end
255
  else if (acc_type_read && curr_cmd_go && crc_cnt_end && !busy_tck) // Latching data (from WB)
256
    begin
257 6 julius
      if (acc_type == `DBG_WB_READ8)
258
        begin
259
          if(byte & (~byte_q))
260
            begin
261
              case (ptr)    // synthesis parallel_case
262 360 julius
                2'b00 : dr[31:24] <=  input_data[31:24];
263
                2'b01 : dr[31:24] <=  input_data[23:16];
264
                2'b10 : dr[31:24] <=  input_data[15:8];
265
                2'b11 : dr[31:24] <=  input_data[7:0];
266 6 julius
              endcase
267 360 julius
              latch_data <=  1'b1;
268 6 julius
            end
269
          else
270
            begin
271 46 julius
               if (enable) // jb
272 360 julius
                 dr[31:24] <=  {dr[30:24], 1'b0};
273
              latch_data <=  1'b0;
274 6 julius
            end
275
        end
276
      else if (acc_type == `DBG_WB_READ16)
277
        begin
278
          if(half & (~half_q))
279
            begin
280
              if (ptr[1])
281 360 julius
                dr[31:16] <=  input_data[15:0];
282 6 julius
              else
283 360 julius
                dr[31:16] <=  input_data[31:16];
284
              latch_data <=  1'b1;
285 6 julius
            end
286
          else
287
            begin
288 46 julius
               if (enable) // jb
289 360 julius
                 dr[31:16] <=  {dr[30:16], 1'b0};
290
              latch_data <=  1'b0;
291 6 julius
            end
292
        end
293
      else if (acc_type == `DBG_WB_READ32)
294
        begin
295
          if(long & (~long_q))
296
            begin
297 360 julius
              dr[31:0] <=  input_data[31:0];
298
              latch_data <=  1'b1;
299 6 julius
            end
300
          else
301
            begin
302 46 julius
               if (enable) // jb
303 360 julius
                 dr[31:0] <=  {dr[30:0], 1'b0};
304
              latch_data <=  1'b0;
305 6 julius
            end
306
        end
307
    end
308
  else if (enable && (!addr_len_cnt_end))
309
    begin
310 360 julius
      dr <=  {dr[`DBG_WB_DR_LEN -2:0], tdi_i};
311 6 julius
    end
312
end
313
 
314
 
315
 
316
assign cmd_cnt_en = enable & (~cmd_cnt_end);
317
 
318
 
319
// Command counter
320
always @ (posedge tck_i or posedge rst_i)
321
begin
322
  if (rst_i)
323 360 julius
    cmd_cnt <=  {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
324 6 julius
  else if (update_dr_i)
325 360 julius
    cmd_cnt <=  {`DBG_WB_CMD_CNT_WIDTH{1'b0}};
326 6 julius
  else if (cmd_cnt_en)
327 363 julius
    cmd_cnt <=  cmd_cnt + `DBG_WB_CMD_CNT_WIDTH'd1;
328 6 julius
end
329
 
330
 
331
// Assigning current command
332
always @ (posedge tck_i or posedge rst_i)
333
begin
334
  if (rst_i)
335 363 julius
    curr_cmd <=  {`DBG_WB_CMD_LEN_INT{1'b0}};
336 6 julius
  else if (update_dr_i)
337 363 julius
    curr_cmd <=  {`DBG_WB_CMD_LEN_INT{1'b0}};
338
  else if (cmd_cnt == (`DBG_WB_CMD_LEN_INT -1))
339
    curr_cmd <=  {dr[`DBG_WB_CMD_LEN_INT-2 :0], tdi_i};
340 6 julius
end
341
 
342
 
343
// Assigning current command
344
always @ (posedge tck_i or posedge rst_i)
345
begin
346
  if (rst_i)
347 360 julius
    curr_cmd_go_q <=  1'b0;
348 6 julius
  else
349 360 julius
    curr_cmd_go_q <=  curr_cmd_go;
350 6 julius
end
351
 
352
 
353
always @ (enable or cmd_cnt_end or addr_len_cnt_end or curr_cmd_wr_comm or curr_cmd_rd_comm or crc_cnt_end)
354
begin
355
  if (enable && (!addr_len_cnt_end))
356
    begin
357
      if (cmd_cnt_end && curr_cmd_wr_comm)
358
        addr_len_cnt_en = 1'b1;
359
      else if (crc_cnt_end && curr_cmd_rd_comm)
360
        addr_len_cnt_en = 1'b1;
361
      else
362
        addr_len_cnt_en = 1'b0;
363
    end
364
  else
365
    addr_len_cnt_en = 1'b0;
366
end
367
 
368
 
369
// Address/length counter
370
always @ (posedge tck_i or posedge rst_i)
371
begin
372
  if (rst_i)
373 363 julius
    addr_len_cnt <=  6'd0;
374 6 julius
  else if (update_dr_i)
375 363 julius
    addr_len_cnt <=  6'd0;
376 6 julius
  else if (addr_len_cnt_en)
377 363 julius
    addr_len_cnt <=  addr_len_cnt + 6'd1;
378 6 julius
end
379
 
380
 
381
always @ (enable or data_cnt_end or cmd_cnt_end or curr_cmd_go or acc_type_write or acc_type_read or crc_cnt_end)
382
begin
383
  if (enable && (!data_cnt_end))
384
    begin
385
      if (cmd_cnt_end && curr_cmd_go && acc_type_write)
386
        data_cnt_en = 1'b1;
387
      else if (crc_cnt_end && curr_cmd_go && acc_type_read)
388
        data_cnt_en = 1'b1;
389
      else
390
        data_cnt_en = 1'b0;
391
    end
392
  else
393
    data_cnt_en = 1'b0;
394
end
395
 
396
 
397
// Data counter
398
always @ (posedge tck_i or posedge rst_i)
399
begin
400
  if (rst_i)
401 363 julius
    data_cnt <=  {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
402 6 julius
  else if (update_dr_i)
403 363 julius
    data_cnt <=  {`DBG_WB_DATA_CNT_WIDTH+1{1'b0}};
404 6 julius
  else if (data_cnt_en)
405 363 julius
    data_cnt <=  data_cnt + 1;
406 6 julius
end
407
 
408
 
409
 
410
// Upper limit. Data counter counts until this value is reached.
411
always @ (posedge tck_i or posedge rst_i)
412
begin
413
  if (rst_i)
414 363 julius
    data_cnt_limit <=  {`DBG_WB_DATA_CNT_LIM_WIDTH+1{1'b0}};
415 6 julius
  else if (update_dr_i)
416 363 julius
    data_cnt_limit <=  len + 1;
417 6 julius
end
418
 
419
 
420
always @ (enable or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or addr_len_cnt_end or data_cnt_end or acc_type_write or acc_type_read or cmd_cnt_end)
421
begin
422
  if (enable && (!crc_cnt_end) && cmd_cnt_end)
423
    begin
424
      if (addr_len_cnt_end && curr_cmd_wr_comm)
425
        crc_cnt_en = 1'b1;
426
      else if (data_cnt_end && curr_cmd_go && acc_type_write)
427
        crc_cnt_en = 1'b1;
428
      else if (cmd_cnt_end && (curr_cmd_go && acc_type_read || curr_cmd_rd_comm))
429
        crc_cnt_en = 1'b1;
430
      else
431
        crc_cnt_en = 1'b0;
432
    end
433
  else
434
    crc_cnt_en = 1'b0;
435
end
436 46 julius
 
437 6 julius
 
438
// crc counter
439
always @ (posedge tck_i or posedge rst_i)
440
begin
441
  if (rst_i)
442 360 julius
    crc_cnt <=  {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
443 6 julius
  else if(crc_cnt_en)
444 363 julius
    crc_cnt <=  crc_cnt + 1;
445 6 julius
  else if (update_dr_i)
446 360 julius
    crc_cnt <=  {`DBG_WB_CRC_CNT_WIDTH{1'b0}};
447 6 julius
end
448
 
449
assign cmd_cnt_end      = cmd_cnt      == `DBG_WB_CMD_LEN;
450
assign addr_len_cnt_end = addr_len_cnt == `DBG_WB_DR_LEN;
451
assign crc_cnt_end      = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd32;
452
assign crc_cnt_31       = crc_cnt      == `DBG_WB_CRC_CNT_WIDTH'd31;
453
assign data_cnt_end     = (data_cnt    == {data_cnt_limit, 3'b000});
454
 
455
always @ (posedge tck_i or posedge rst_i)
456
begin
457
  if (rst_i)
458
    begin
459 360 julius
      crc_cnt_end_q       <=  1'b0;
460
      cmd_cnt_end_q       <=  1'b0;
461
      data_cnt_end_q      <=  1'b0;
462
      addr_len_cnt_end_q  <=  1'b0;
463 6 julius
    end
464
  else
465
    begin
466 360 julius
      crc_cnt_end_q       <=  crc_cnt_end;
467
      cmd_cnt_end_q       <=  cmd_cnt_end;
468
      data_cnt_end_q      <=  data_cnt_end;
469
      addr_len_cnt_end_q  <=  addr_len_cnt_end;
470 6 julius
    end
471
end
472
 
473
 
474
// Status counter is made of 4 serialy connected registers
475
always @ (posedge tck_i or posedge rst_i)
476
begin
477
  if (rst_i)
478 360 julius
    status_cnt <=  {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
479 6 julius
  else if (update_dr_i)
480 360 julius
    status_cnt <=  {`DBG_WB_STATUS_CNT_WIDTH{1'b0}};
481 6 julius
  else if (status_cnt_en)
482 363 julius
    status_cnt <=  status_cnt + `DBG_WB_STATUS_CNT_WIDTH'd1;
483 6 julius
end
484
 
485
 
486
always @ (enable or status_cnt_end or crc_cnt_end or curr_cmd_rd_comm or curr_cmd_wr_comm or curr_cmd_go or acc_type_write or acc_type_read or data_cnt_end or addr_len_cnt_end)
487
begin
488
  if (enable && (!status_cnt_end))
489
    begin
490
      if (crc_cnt_end && curr_cmd_wr_comm)
491
        status_cnt_en = 1'b1;
492
      else if (crc_cnt_end && curr_cmd_go && acc_type_write)
493
        status_cnt_en = 1'b1;
494
      else if (data_cnt_end && curr_cmd_go && acc_type_read)
495
        status_cnt_en = 1'b1;
496
      else if (addr_len_cnt_end && curr_cmd_rd_comm)
497
        status_cnt_en = 1'b1;
498
      else
499
        status_cnt_en = 1'b0;
500
    end
501
  else
502
    status_cnt_en = 1'b0;
503
end
504
 
505
 
506
assign status_cnt_end = status_cnt == `DBG_WB_STATUS_LEN;
507
 
508
 
509
// Latching acc_type, address and length
510
always @ (posedge tck_i or posedge rst_i)
511
begin
512
  if (rst_i)
513
    begin
514 360 julius
      acc_type  <=  {`DBG_WB_ACC_TYPE_LEN{1'b0}};
515
      adr       <=  {`DBG_WB_ADR_LEN{1'b0}};
516
      len       <=  {`DBG_WB_LEN_LEN{1'b0}};
517
      set_addr  <=  1'b0;
518 6 julius
    end
519
  else if(crc_cnt_end && (!crc_cnt_end_q) && crc_match_i && curr_cmd_wr_comm)
520
    begin
521 360 julius
      acc_type  <=  dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN];
522
      adr       <=  dr[`DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1 : `DBG_WB_LEN_LEN];
523
      len       <=  dr[`DBG_WB_LEN_LEN -1:0];
524
      set_addr  <=  1'b1;
525 6 julius
    end
526
  else if(wb_end_tck)               // Writing back the address
527
    begin
528 360 julius
      adr  <=  wb_adr_dsff;
529 6 julius
    end
530
  else
531 360 julius
    set_addr <=  1'b0;
532 6 julius
end
533
 
534
 
535
always @ (posedge tck_i or posedge rst_i)
536
begin
537
  if (rst_i)
538 360 julius
    crc_match_reg <=  1'b0;
539 6 julius
  else if(crc_cnt_end & (~crc_cnt_end_q))
540 360 julius
    crc_match_reg <=  crc_match_i;
541 6 julius
end
542
 
543
// Length counter
544
always @ (posedge tck_i or posedge rst_i)
545
begin
546
  if (rst_i)
547 360 julius
    len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
548 6 julius
  else if(update_dr_i)
549 363 julius
    len_var <=  len + 1;
550 6 julius
  else if (start_rd_tck)
551
    begin
552
      case (acc_type)  // synthesis parallel_case
553
        `DBG_WB_READ8 :
554
                    if (len_var > 'd1)
555 363 julius
                      len_var <=  len_var - 1;
556 6 julius
                    else
557 360 julius
                      len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
558 6 julius
        `DBG_WB_READ16:
559
                    if (len_var > 'd2)
560 363 julius
                      len_var <=  len_var - 2;
561 6 julius
                    else
562 360 julius
                      len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
563 6 julius
        `DBG_WB_READ32:
564
                    if (len_var > 'd4)
565 363 julius
                      len_var <=  len_var - 4;
566 6 julius
                    else
567 360 julius
                      len_var <=  {1'b0, {`DBG_WB_LEN_LEN{1'b0}}};
568
        default:      len_var <=  {1'bx, {`DBG_WB_LEN_LEN{1'bx}}};
569 6 julius
      endcase
570
    end
571
end
572
 
573
 
574 363 julius
assign len_eq_0 = !(|len_var);
575
 
576 6 julius
 
577
 
578
assign byte = data_cnt[2:0] == 3'd7;
579
assign half = data_cnt[3:0] == 4'd15;
580
assign long = data_cnt[4:0] == 5'd31;
581
 
582
 
583
always @ (posedge tck_i or posedge rst_i)
584
begin
585
  if (rst_i)
586
    begin
587 360 julius
      byte_q <=   1'b0;
588
      half_q <=   1'b0;
589
      long_q <=   1'b0;
590 6 julius
    end
591
  else
592
    begin
593 360 julius
      byte_q <=  byte;
594
      half_q <=  half;
595
      long_q <=  long;
596 6 julius
    end
597
end
598
 
599
 
600
// Start wishbone write cycle
601
always @ (posedge tck_i or posedge rst_i)
602
begin
603
  if (rst_i)
604
    begin
605 360 julius
      start_wr_tck <=  1'b0;
606
      wb_dat_tmp <=  32'h0;
607 6 julius
    end
608
  else if (curr_cmd_go && acc_type_write)
609
    begin
610
      case (acc_type)  // synthesis parallel_case full_case
611
        `DBG_WB_WRITE8  : begin
612
                        if (byte_q)
613
                          begin
614 360 julius
                            start_wr_tck <=  1'b1;
615
                            wb_dat_tmp <=  {4{dr[7:0]}};
616 6 julius
                          end
617
                        else
618
                          begin
619 360 julius
                            start_wr_tck <=  1'b0;
620 6 julius
                          end
621
                      end
622
        `DBG_WB_WRITE16 : begin
623
                        if (half_q)
624
                          begin
625 360 julius
                            start_wr_tck <=  1'b1;
626
                            wb_dat_tmp <=  {2{dr[15:0]}};
627 6 julius
                          end
628
                        else
629
                          begin
630 360 julius
                            start_wr_tck <=  1'b0;
631 6 julius
                          end
632
                      end
633
        `DBG_WB_WRITE32 : begin
634
                        if (long_q)
635
                          begin
636 360 julius
                            start_wr_tck <=  1'b1;
637
                            wb_dat_tmp <=  dr[31:0];
638 6 julius
                          end
639
                        else
640
                          begin
641 360 julius
                            start_wr_tck <=  1'b0;
642 6 julius
                          end
643 363 julius
                       end
644
        default: begin
645
 
646
        end
647 6 julius
      endcase
648
    end
649
  else
650 360 julius
    start_wr_tck <=  1'b0;
651 6 julius
end
652
 
653
 
654
// wb_dat_o in WB clk domain
655
always @ (posedge wb_clk_i)
656
begin
657 360 julius
  wb_dat_dsff <=  wb_dat_tmp;
658 6 julius
end
659
 
660
assign wb_dat_o = wb_dat_dsff;
661
 
662
 
663
// Start wishbone read cycle
664
always @ (posedge tck_i or posedge rst_i)
665
begin
666
  if (rst_i)
667 360 julius
    start_rd_tck <=  1'b0;
668 6 julius
  else if (curr_cmd_go && (!curr_cmd_go_q) && acc_type_read)              // First read after cmd is entered
669 360 julius
    start_rd_tck <=  1'b1;
670 6 julius
  else if ((!start_rd_tck) && curr_cmd_go && acc_type_read  && (!len_eq_0) && (!fifo_full) && (!rd_tck_started))
671 360 julius
    start_rd_tck <=  1'b1;
672 6 julius
  else
673 360 julius
    start_rd_tck <=  1'b0;
674 6 julius
end
675
 
676
 
677
always @ (posedge tck_i or posedge rst_i)
678
begin
679
  if (rst_i)
680 360 julius
    rd_tck_started <=  1'b0;
681 6 julius
  else if (update_dr_i || wb_end_tck && (!wb_end_tck_q))
682 360 julius
    rd_tck_started <=  1'b0;
683 6 julius
  else if (start_rd_tck)
684 360 julius
    rd_tck_started <=  1'b1;
685 6 julius
end
686
 
687
 
688
 
689
always @ (posedge wb_clk_i or posedge rst_i)
690
begin
691
  if (rst_i)
692
    begin
693 360 julius
      start_rd_csff   <=  1'b0;
694
      start_wb_rd     <=  1'b0;
695
      start_wb_rd_q   <=  1'b0;
696 6 julius
 
697 360 julius
      start_wr_csff   <=  1'b0;
698
      start_wb_wr     <=  1'b0;
699
      start_wb_wr_q   <=  1'b0;
700 6 julius
 
701 360 julius
      set_addr_csff   <=  1'b0;
702
      set_addr_wb     <=  1'b0;
703
      set_addr_wb_q   <=  1'b0;
704 6 julius
    end
705
  else
706
    begin
707 360 julius
      start_rd_csff   <=  start_rd_tck;
708
      start_wb_rd     <=  start_rd_csff;
709
      start_wb_rd_q   <=  start_wb_rd;
710 6 julius
 
711 360 julius
      start_wr_csff   <=  start_wr_tck;
712
      start_wb_wr     <=  start_wr_csff;
713
      start_wb_wr_q   <=  start_wb_wr;
714 6 julius
 
715 360 julius
      set_addr_csff   <=  set_addr;
716
      set_addr_wb     <=  set_addr_csff;
717
      set_addr_wb_q   <=  set_addr_wb;
718 6 julius
    end
719
end
720
 
721
 
722
// wb_cyc_o
723
always @ (posedge wb_clk_i or posedge rst_i)
724
begin
725
  if (rst_i)
726 360 julius
    wb_cyc_o <=  1'b0;
727 6 julius
  else if ((start_wb_wr && (!start_wb_wr_q)) || (start_wb_rd && (!start_wb_rd_q)))
728 360 julius
    wb_cyc_o <=  1'b1;
729 6 julius
  else if (wb_ack_i || wb_err_i)
730 360 julius
    wb_cyc_o <=  1'b0;
731 6 julius
end
732
 
733
 
734
// wb_adr_o logic
735
always @ (posedge wb_clk_i or posedge rst_i)
736
begin
737
  if (rst_i)
738 363 julius
    wb_adr_dsff <=  32'd0;
739 6 julius
  else if (set_addr_wb && (!set_addr_wb_q)) // Setting starting address
740 360 julius
    wb_adr_dsff <=  adr;
741 6 julius
  else if (wb_ack_i)
742
    begin
743
      if ((acc_type == `DBG_WB_WRITE8) || (acc_type == `DBG_WB_READ8))
744 363 julius
        wb_adr_dsff <=  wb_adr_dsff + 32'd1;
745 6 julius
      else if ((acc_type == `DBG_WB_WRITE16) || (acc_type == `DBG_WB_READ16))
746 363 julius
        wb_adr_dsff <=  wb_adr_dsff + 32'd2;
747 6 julius
      else
748 363 julius
        wb_adr_dsff <=  wb_adr_dsff + 32'd4;
749 6 julius
    end
750
end
751
 
752
 
753
assign wb_adr_o = wb_adr_dsff;
754
 
755
 
756
//    adr   byte  |  short  |  long
757
//     0    1000     1100      1111
758
//     1    0100     err       err
759
//     2    0010     0011      err
760
//     3    0001     err       err
761
// wb_sel_o logic
762
 
763
always @ (posedge wb_clk_i or posedge rst_i)
764
begin
765
  if (rst_i)
766 360 julius
    wb_sel_dsff[3:0] <=  4'h0;
767 547 julius
  else if ((start_wb_wr && (!start_wb_wr_q)))
768 6 julius
    begin
769
      case ({wb_adr_dsff[1:0], acc_type_8bit, acc_type_16bit, acc_type_32bit}) // synthesis parallel_case
770 360 julius
        {2'd0, 3'b100} : wb_sel_dsff[3:0] <=  4'h8;
771
        {2'd0, 3'b010} : wb_sel_dsff[3:0] <=  4'hC;
772
        {2'd0, 3'b001} : wb_sel_dsff[3:0] <=  4'hF;
773
        {2'd1, 3'b100} : wb_sel_dsff[3:0] <=  4'h4;
774
        {2'd2, 3'b100} : wb_sel_dsff[3:0] <=  4'h2;
775
        {2'd2, 3'b010} : wb_sel_dsff[3:0] <=  4'h3;
776
        {2'd3, 3'b100} : wb_sel_dsff[3:0] <=  4'h1;
777
        default:         wb_sel_dsff[3:0] <=  4'hx;
778 6 julius
      endcase
779
    end
780
end
781
 
782
 
783
assign wb_sel_o = wb_sel_dsff;
784
 
785 547 julius
/*
786 6 julius
always @ (posedge wb_clk_i)
787
begin
788 360 julius
  wb_we_dsff <=  curr_cmd_go && acc_type_write;
789 6 julius
end
790 547 julius
*/
791 6 julius
 
792 547 julius
always @ (posedge wb_clk_i or posedge rst_i)
793
begin
794
  if (rst_i)
795
     wb_we_dsff <=  1'b0;
796
  else if ((start_wb_wr && (!start_wb_wr_q)))
797
    wb_we_dsff <=  1'b1;
798
  else if (wb_ack_i || wb_err_i)
799
    wb_we_dsff <=  1'b0;
800
end
801 6 julius
 
802 547 julius
 
803 6 julius
assign wb_we_o = wb_we_dsff;
804
assign wb_cab_o = 1'b0;
805
assign wb_stb_o = wb_cyc_o;
806
assign wb_cti_o = 3'h0;     // always performing single access
807
assign wb_bte_o = 2'h0;     // always performing single access
808
 
809
 
810
 
811
// Logic for detecting end of transaction
812
always @ (posedge wb_clk_i or posedge rst_i)
813
begin
814
  if (rst_i)
815 360 julius
    wb_end <=  1'b0;
816 6 julius
  else if (wb_ack_i || wb_err_i)
817 360 julius
    wb_end <=  1'b1;
818 6 julius
  else if (wb_end_rst)
819 360 julius
    wb_end <=  1'b0;
820 6 julius
end
821
 
822
 
823
always @ (posedge tck_i or posedge rst_i)
824
begin
825
  if (rst_i)
826
    begin
827 360 julius
      wb_end_csff  <=  1'b0;
828
      wb_end_tck   <=  1'b0;
829
      wb_end_tck_q <=  1'b0;
830 6 julius
    end
831
  else
832
    begin
833 360 julius
      wb_end_csff  <=  wb_end;
834
      wb_end_tck   <=  wb_end_csff;
835
      wb_end_tck_q <=  wb_end_tck;
836 6 julius
    end
837
end
838
 
839
 
840
always @ (posedge wb_clk_i or posedge rst_i)
841
begin
842
  if (rst_i)
843
    begin
844 360 julius
      wb_end_rst_csff <=  1'b0;
845
      wb_end_rst      <=  1'b0;
846 6 julius
    end
847
  else
848
    begin
849 360 julius
      wb_end_rst_csff <=  wb_end_tck;
850
      wb_end_rst      <=  wb_end_rst_csff;
851 6 julius
    end
852
end
853
 
854
 
855
always @ (posedge wb_clk_i or posedge rst_i)
856
begin
857
  if (rst_i)
858 360 julius
    busy_wb <=  1'b0;
859 6 julius
  else if (wb_end_rst)
860 360 julius
    busy_wb <=  1'b0;
861 6 julius
  else if (wb_cyc_o)
862 360 julius
    busy_wb <=  1'b1;
863 6 julius
end
864
 
865
 
866
always @ (posedge tck_i or posedge rst_i)
867
begin
868
  if (rst_i)
869
    begin
870 360 julius
      busy_csff       <=  1'b0;
871
      busy_tck        <=  1'b0;
872 6 julius
 
873 360 julius
      update_dr_csff  <=  1'b0;
874
      update_dr_wb    <=  1'b0;
875 6 julius
    end
876
  else
877
    begin
878 360 julius
      busy_csff       <=  busy_wb;
879
      busy_tck        <=  busy_csff;
880 6 julius
 
881 360 julius
      update_dr_csff  <=  update_dr_i;
882
      update_dr_wb    <=  update_dr_csff;
883 6 julius
    end
884
end
885
 
886
 
887
// Detecting WB error
888
always @ (posedge wb_clk_i or posedge rst_i)
889
begin
890
  if (rst_i)
891 360 julius
    wb_error <=  1'b0;
892 6 julius
  else if(wb_err_i)
893 360 julius
    wb_error <=  1'b1;
894 6 julius
  else if(update_dr_wb) // error remains active until update_dr arrives
895 360 julius
    wb_error <=  1'b0;
896 6 julius
end
897
 
898
 
899
// Detecting overrun when write operation.
900
always @ (posedge wb_clk_i or posedge rst_i)
901
begin
902
  if (rst_i)
903 360 julius
    wb_overrun <=  1'b0;
904 6 julius
  else if(start_wb_wr && (!start_wb_wr_q) && wb_cyc_o)
905 360 julius
    wb_overrun <=  1'b1;
906 6 julius
  else if(update_dr_wb) // error remains active until update_dr arrives
907 360 julius
    wb_overrun <=  1'b0;
908 6 julius
end
909
 
910
 
911
// Detecting underrun when read operation
912
always @ (posedge tck_i or posedge rst_i)
913
begin
914
  if (rst_i)
915 360 julius
    underrun_tck <=  1'b0;
916 6 julius
  else if(latch_data && fifo_empty && (!data_cnt_end))
917 360 julius
    underrun_tck <=  1'b1;
918 6 julius
  else if(update_dr_i) // error remains active until update_dr arrives
919 360 julius
    underrun_tck <=  1'b0;
920 6 julius
end
921
 
922
 
923
always @ (posedge tck_i or posedge rst_i)
924
begin
925
  if (rst_i)
926
    begin
927 360 julius
      wb_error_csff   <=  1'b0;
928
      wb_error_tck    <=  1'b0;
929 6 julius
 
930 360 julius
      wb_overrun_csff <=  1'b0;
931
      wb_overrun_tck  <=  1'b0;
932 6 julius
    end
933
  else
934
    begin
935 360 julius
      wb_error_csff   <=  wb_error;
936
      wb_error_tck    <=  wb_error_csff;
937 6 julius
 
938 360 julius
      wb_overrun_csff <=  wb_overrun;
939
      wb_overrun_tck  <=  wb_overrun_csff;
940 6 julius
    end
941
end
942
 
943
 
944
 
945
always @ (posedge wb_clk_i or posedge rst_i)
946
begin
947
  if (rst_i)
948
    begin
949 360 julius
      wishbone_ce_csff  <=  1'b0;
950
      mem_ptr_init      <=  1'b0;
951 6 julius
    end
952
  else
953
    begin
954 360 julius
      wishbone_ce_csff  <=   wishbone_ce_i;
955
      mem_ptr_init      <=  ~wishbone_ce_csff;
956 6 julius
    end
957
end
958
 
959
 
960
// Logic for latching data that is read from wishbone
961
always @ (posedge wb_clk_i or posedge rst_i)
962
begin
963
  if (rst_i)
964 360 julius
    mem_ptr_dsff <=  3'h0;
965 6 julius
  else if(mem_ptr_init)
966 360 julius
    mem_ptr_dsff <=  3'h0;
967 6 julius
  else if (wb_ack_i)
968
    begin
969
      if (acc_type == `DBG_WB_READ8)
970 363 julius
        mem_ptr_dsff <=  mem_ptr_dsff + 3'd1;
971 6 julius
      else if (acc_type == `DBG_WB_READ16)
972 363 julius
        mem_ptr_dsff <=  mem_ptr_dsff + 3'd2;
973 6 julius
    end
974
end
975
 
976
 
977
// Logic for latching data that is read from wishbone
978
always @ (posedge wb_clk_i)
979
begin
980
  if (wb_ack_i)
981
    begin
982
      case (wb_sel_dsff)    // synthesis parallel_case
983 547 julius
        4'b1000  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[31:24];// byte
984
        4'b0100  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[23:16];// byte
985
        4'b0010  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[15:08];// byte
986
        4'b0001  :  mem[mem_ptr_dsff[1:0]] <=  wb_dat_i[07:00];// byte
987
 
988
        4'b1100  :                                                  // half
989 6 julius
                    begin
990 360 julius
                      mem[mem_ptr_dsff[1:0]]      <=  wb_dat_i[31:24];
991
                      mem[mem_ptr_dsff[1:0]+1'b1] <=  wb_dat_i[23:16];
992 6 julius
                    end
993
        4'b0011  :                                                      // half
994
                    begin
995 360 julius
                      mem[mem_ptr_dsff[1:0]]      <=  wb_dat_i[15:08];
996
                      mem[mem_ptr_dsff[1:0]+1'b1] <=  wb_dat_i[07:00];
997 6 julius
                    end
998 547 julius
        /*4'b1111  :                                                      // long*/
999
        default:
1000 6 julius
                    begin
1001 360 julius
                      mem[0] <=  wb_dat_i[31:24];
1002
                      mem[1] <=  wb_dat_i[23:16];
1003
                      mem[2] <=  wb_dat_i[15:08];
1004
                      mem[3] <=  wb_dat_i[07:00];
1005 6 julius
                    end
1006 547 julius
        /*
1007 6 julius
        default  :                                                      // long
1008
                    begin
1009 360 julius
                      mem[0] <=  8'hxx;
1010
                      mem[1] <=  8'hxx;
1011
                      mem[2] <=  8'hxx;
1012
                      mem[3] <=  8'hxx;
1013 6 julius
                    end
1014 547 julius
         */
1015 6 julius
      endcase
1016
    end
1017
end
1018
 
1019
 
1020
 
1021
assign input_data = {mem[0], mem[1], mem[2], mem[3]};
1022
 
1023
 
1024
// Fifo counter and empty/full detection
1025
always @ (posedge tck_i or posedge rst_i)
1026
begin
1027
  if (rst_i)
1028 360 julius
    fifo_cnt <=  3'h0;
1029 6 julius
  else if (update_dr_i)
1030 360 julius
    fifo_cnt <=  3'h0;
1031 6 julius
  else if (wb_end_tck && (!wb_end_tck_q) && (!latch_data) && (!fifo_full))  // incrementing
1032
    begin
1033
      case (acc_type)  // synthesis parallel_case
1034 363 julius
        `DBG_WB_READ8 : fifo_cnt <=  fifo_cnt + 3'd1;
1035
        `DBG_WB_READ16: fifo_cnt <=  fifo_cnt + 3'd2;
1036 360 julius
        `DBG_WB_READ32: fifo_cnt <=  fifo_cnt + 3'd4;
1037
        default:        fifo_cnt <=  3'bxxx;
1038 6 julius
      endcase
1039
    end
1040
  else if (!(wb_end_tck && (!wb_end_tck_q)) && latch_data && (!fifo_empty))  // decrementing
1041
    begin
1042
      case (acc_type)  // synthesis parallel_case
1043 363 julius
        `DBG_WB_READ8 : fifo_cnt <=  fifo_cnt - 3'd1;
1044
        `DBG_WB_READ16: fifo_cnt <=  fifo_cnt - 3'd2;
1045 360 julius
        `DBG_WB_READ32: fifo_cnt <=  fifo_cnt - 3'd4;
1046
        default:        fifo_cnt <=  3'bxxx;
1047 6 julius
      endcase
1048
    end
1049
end
1050
 
1051
 
1052
assign fifo_full  = fifo_cnt == 3'h4;
1053
assign fifo_empty = fifo_cnt == 3'h0;
1054
 
1055
 
1056
// TDO multiplexer
1057
always @ (pause_dr_i or busy_tck or crc_cnt_end or crc_cnt_end_q or curr_cmd_wr_comm or
1058
          curr_cmd_rd_comm or curr_cmd_go or acc_type_write or acc_type_read or crc_match_i
1059
          or data_cnt_end or dr or data_cnt_end_q or crc_match_reg or status_cnt_en or status
1060
          or addr_len_cnt_end or addr_len_cnt_end_q)
1061
begin
1062
  if (pause_dr_i)
1063
    begin
1064
    tdo_o = busy_tck;
1065
    end
1066
  else if (crc_cnt_end && (!crc_cnt_end_q) && (curr_cmd_wr_comm || curr_cmd_go && acc_type_write ))
1067
    begin
1068
      tdo_o = ~crc_match_i;
1069
    end
1070
  else if (curr_cmd_go && acc_type_read && crc_cnt_end && (!data_cnt_end))
1071
    begin
1072
      tdo_o = dr[31];
1073
    end
1074
  else if (curr_cmd_go && acc_type_read && data_cnt_end && (!data_cnt_end_q))
1075
    begin
1076
      tdo_o = ~crc_match_reg;
1077
    end
1078
  else if (curr_cmd_rd_comm && addr_len_cnt_end && (!addr_len_cnt_end_q))
1079
    begin
1080
      tdo_o = ~crc_match_reg;
1081
    end
1082
  else if (curr_cmd_rd_comm && crc_cnt_end && (!addr_len_cnt_end))
1083
    begin
1084
      tdo_o = dr[`DBG_WB_ACC_TYPE_LEN + `DBG_WB_ADR_LEN + `DBG_WB_LEN_LEN -1];
1085
    end
1086
  else if (status_cnt_en)
1087
    begin
1088
      tdo_o = status[3];
1089
    end
1090
  else
1091
    begin
1092
      tdo_o = 1'b0;
1093
    end
1094
end
1095
 
1096
// Status register
1097
always @ (posedge tck_i or posedge rst_i)
1098
begin
1099
  if (rst_i)
1100
    begin
1101 360 julius
    status <=  {`DBG_WB_STATUS_LEN{1'b0}};
1102 6 julius
    end
1103
  else if(crc_cnt_end && (!crc_cnt_end_q) && (!(curr_cmd_go && acc_type_read)))
1104
    begin
1105 360 julius
    status <=  {1'b0, wb_error_tck, wb_overrun_tck, crc_match_i};
1106 6 julius
    end
1107
  else if (data_cnt_end && (!data_cnt_end_q) && curr_cmd_go && acc_type_read)
1108
    begin
1109 360 julius
    status <=  {1'b0, wb_error_tck, underrun_tck, crc_match_reg};
1110 6 julius
    end
1111
  else if (addr_len_cnt_end && (!addr_len_cnt_end) && curr_cmd_rd_comm)
1112
    begin
1113 360 julius
    status <=  {1'b0, 1'b0, 1'b0, crc_match_reg};
1114 6 julius
    end
1115
  else if (shift_dr_i && (!status_cnt_end))
1116
    begin
1117 360 julius
    status <=  {status[`DBG_WB_STATUS_LEN -2:0], status[`DBG_WB_STATUS_LEN -1]};
1118 6 julius
    end
1119
end
1120
// Following status is shifted out (MSB first):
1121
// 3. bit:          1 if crc is OK, else 0
1122
// 2. bit:          1'b0
1123
// 1. bit:          1 if WB error occured, else 0
1124
// 0. bit:          1 if overrun occured during write (data couldn't be written fast enough)
1125
//                    or underrun occured during read (data couldn't be read fast enough)
1126
 
1127
 
1128
endmodule
1129
 

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