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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  eth_crc.v                                                   ////

////                                                              ////

////  This file is part of the Ethernet IP core project           ////

////  http://www.opencores.org/project,ethmac                     ////

////                                                              ////

////  Author(s):                                                  ////

////      - Igor Mohor (igorM@opencores.org)                      ////

////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////

////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////

////                                                              ////

////  All additional information is avaliable in the Readme.txt   ////

////  file.                                                       ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2001 Authors                                   ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: not supported by cvs2svn $

// Revision 1.2  2001/10/19 08:43:51  mohor

// eth_timescale.v changed to timescale.v This is done because of the

// simulation of the few cores in a one joined project.

//

// Revision 1.1  2001/08/06 14:44:29  mohor

// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).

// Include files fixed to contain no path.

// File names and module names changed ta have a eth_ prologue in the name.

// File eth_timescale.v is used to define timescale

// All pin names on the top module are changed to contain _I, _O or _OE at the end.

// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O

// and Mdo_OE. The bidirectional signal must be created on the top level. This

// is done due to the ASIC tools.

//

// Revision 1.1  2001/07/30 21:23:42  mohor

// Directory structure changed. Files checked and joind together.

//

// Revision 1.3  2001/06/19 18:16:40  mohor

// TxClk changed to MTxClk (as discribed in the documentation).

// Crc changed so only one file can be used instead of two.

//

// Revision 1.2  2001/06/19 10:38:07  mohor

// Minor changes in header.

//

// Revision 1.1  2001/06/19 10:27:57  mohor

// TxEthMAC initial release.

//

//

//

`include "timescale.v"

module eth_crc (Clk, Reset, Data, Enable, Initialize, Crc, CrcError);

input Clk;

input Reset;

input [3:0] Data;

input Enable;

input Initialize;

output [31:0] Crc;

output CrcError;

reg  [31:0] Crc;

wire [31:0] CrcNext;

assign CrcNext[0] = Enable & (Data[0] ^ Crc[28]);

assign CrcNext[1] = Enable & (Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29]);

assign CrcNext[2] = Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30]);

assign CrcNext[3] = Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31]);

assign CrcNext[4] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[0];

assign CrcNext[5] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[1];

assign CrcNext[6] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[ 2];

assign CrcNext[7] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[3];

assign CrcNext[8] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[4];

assign CrcNext[9] = (Enable & (Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30])) ^ Crc[5];

assign CrcNext[10] = (Enable & (Data[3] ^ Data[2] ^ Data[0] ^ Crc[28] ^ Crc[30] ^ Crc[31])) ^ Crc[6];

assign CrcNext[11] = (Enable & (Data[3] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[31])) ^ Crc[7];

assign CrcNext[12] = (Enable & (Data[2] ^ Data[1] ^ Data[0] ^ Crc[28] ^ Crc[29] ^ Crc[30])) ^ Crc[8];

assign CrcNext[13] = (Enable & (Data[3] ^ Data[2] ^ Data[1] ^ Crc[29] ^ Crc[30] ^ Crc[31])) ^ Crc[9];

assign CrcNext[14] = (Enable & (Data[3] ^ Data[2] ^ Crc[30] ^ Crc[31])) ^ Crc[10];

assign CrcNext[15] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[11];

assign CrcNext[16] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[12];

assign CrcNext[17] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[13];

assign CrcNext[18] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[14];

assign CrcNext[19] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[15];

assign CrcNext[20] = Crc[16];

assign CrcNext[21] = Crc[17];

assign CrcNext[22] = (Enable & (Data[0] ^ Crc[28])) ^ Crc[18];

assign CrcNext[23] = (Enable & (Data[1] ^ Data[0] ^ Crc[29] ^ Crc[28])) ^ Crc[19];

assign CrcNext[24] = (Enable & (Data[2] ^ Data[1] ^ Crc[30] ^ Crc[29])) ^ Crc[20];

assign CrcNext[25] = (Enable & (Data[3] ^ Data[2] ^ Crc[31] ^ Crc[30])) ^ Crc[21];

assign CrcNext[26] = (Enable & (Data[3] ^ Data[0] ^ Crc[31] ^ Crc[28])) ^ Crc[22];

assign CrcNext[27] = (Enable & (Data[1] ^ Crc[29])) ^ Crc[23];

assign CrcNext[28] = (Enable & (Data[2] ^ Crc[30])) ^ Crc[24];

assign CrcNext[29] = (Enable & (Data[3] ^ Crc[31])) ^ Crc[25];

assign CrcNext[30] = Crc[26];

assign CrcNext[31] = Crc[27];

always @ (posedge Clk or posedge Reset)

begin

  if (Reset)

    Crc <=  32'hffffffff;

  else

  if(Initialize)

    Crc <=  32'hffffffff;

  else

    Crc <=  CrcNext;

end

assign CrcError = Crc[31:0] != 32'hc704dd7b;  // CRC not equal to magic number

endmodule