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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_fifo.v                                                  ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Julius Baxter (julius@opencores.org)                  ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "ethmac_defines.v"
`include "timescale.v"
 
module eth_fifo (data_in, data_out, clk, reset, write, read, clear,
                 almost_full, full, almost_empty, empty, cnt);
 
   parameter DATA_WIDTH    = 32;
   parameter DEPTH         = 8;
   parameter CNT_WIDTH     = 3;
 
   input                     clk;
   input                     reset;
   input                     write;
   input                     read;
   input                     clear;
   input [DATA_WIDTH-1:0]    data_in;
 
   output [DATA_WIDTH-1:0]   data_out;
   output                    almost_full;
   output                    full;
   output                    almost_empty;
   output                    empty;
   output [CNT_WIDTH-1:0]    cnt;
 
 
   reg [CNT_WIDTH-1:0]        read_pointer;
   reg [CNT_WIDTH-1:0]        cnt;
 
   always @ (posedge clk or posedge reset)
     begin
        if(reset)
          cnt <= 0;
        else
          if(clear)
            cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};
          else
            if(read ^ write)
              if(read)
                cnt <= cnt - 1;
              else
                cnt <= cnt + 1;
     end
 
 
   assign empty = ~(|cnt);
   assign almost_empty = cnt==1;
   assign full  = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);
   assign almost_full  = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2);
 
 
`ifdef ETH_FIFO_GENERIC
 
   reg     [DATA_WIDTH-1:0]  fifo  [0:DEPTH-1] /*synthesis syn_ramstyle = "no_rw_check"*/ ;
 
 
   // This should make the synthesis tool infer a RAM
   reg [CNT_WIDTH-1:0]        waddr, raddr, raddr_reg;
   reg                       clear_reg; // Register the clear pulse
 
   reg                       fallthrough_read;
   reg [CNT_WIDTH-1:0]        fallthrough_read_addr;
 
 
   always @(posedge clk)
     if (reset)
       fallthrough_read <= 0;
     else
       fallthrough_read <= empty & write;
 
   always @(posedge clk)
     if (empty & write)
       fallthrough_read_addr <= waddr;
 
   always @(posedge clk)
     if (reset)
       waddr <= 0;
     else if (write)
       waddr <= waddr + 1;
 
   always @(posedge clk)
     if (reset)
       raddr <= 0;
     else if (clear)
       raddr <= waddr;
     else if (read | clear_reg)
       raddr <= raddr + 1;
 
   always @ (posedge clk)
     if (write & ~full)
       fifo[waddr] <=  data_in;
 
 
   always @(posedge clk)
     clear_reg <= clear;
 
   always @ (posedge clk)
     if (read | clear_reg)
       raddr_reg <= raddr;
     else if (fallthrough_read) // To pulse RE for fall-through on Xilinx
       raddr_reg <= fallthrough_read_addr;
 
   assign  data_out = fifo[raddr_reg];
 
   always @ (posedge clk or posedge reset)
     begin
        if(reset)
          read_pointer <= 0;
        else
          if(clear)
            // Begin read pointer at 1
            read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1};
          else
            if(read & ~empty)
              read_pointer <= read_pointer + 1'b1;
     end
 
 
`else // !`ifdef ETH_FIFO_GENERIC
 
   reg     [CNT_WIDTH-1:0]   write_pointer;
 
 
   always @ (posedge clk or posedge reset)
     begin
        if(reset)
          read_pointer <= 0;
        else
          if(clear)
            read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read};
          else
            if(read & ~empty)
              read_pointer <= read_pointer + 1'b1;
     end
 
   always @ (posedge clk or posedge reset)
     begin
        if(reset)
          write_pointer <= 0;
        else
          if(clear)
            write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write};
          else
            if(write & ~full)
              write_pointer <= write_pointer + 1'b1;
     end // always @ (posedge clk or posedge reset)
 
`endif // !`ifdef ETH_FIFO_GENERIC
 
 `ifdef ETH_FIFO_XILINX
 
   generate
      if (CNT_WIDTH==4)
        begin
           xilinx_dist_ram_16x32 fifo
             ( .data_out(data_out),
               .we(write & ~full),
               .data_in(data_in),
               .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
               .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
               .wclk(clk)
               );
        end // if (CNT_WIDTH==4)
      else if (CNT_WIDTH==6)
        begin
 
           wire  [DATA_WIDTH-1:0]  data_out0;
           wire [DATA_WIDTH-1:0]   data_out1;
           wire [DATA_WIDTH-1:0]   data_out2;
           wire [DATA_WIDTH-1:0]   data_out3;
 
           wire                    we_ram0,we_ram1,we_ram2,we_ram3;
 
           assign we_ram0 = (write_pointer[5:4]==2'b00);
           assign we_ram1 = (write_pointer[5:4]==2'b01);
           assign we_ram2 = (write_pointer[5:4]==2'b10);
           assign we_ram3 = (write_pointer[5:4]==2'b11);
 
           assign data_out = (read_pointer[5:4]==2'b11) ? data_out3 :
                             (read_pointer[5:4]==2'b10) ? data_out2 :
                             (read_pointer[5:4]==2'b01) ? data_out1 : data_out0;
 
           xilinx_dist_ram_16x32 fifo0
             ( .data_out(data_out0),
               .we(write & ~full & we_ram0),
               .data_in(data_in),
               .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
               .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
               .wclk(clk)
               );
 
           xilinx_dist_ram_16x32 fifo1
             ( .data_out(data_out1),
               .we(write & ~full & we_ram1),
               .data_in(data_in),
               .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
               .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
               .wclk(clk)
               );
 
           xilinx_dist_ram_16x32 fifo2
             ( .data_out(data_out2),
               .we(write & ~full & we_ram2),
               .data_in(data_in),
               .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
               .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
               .wclk(clk)
               );
 
           xilinx_dist_ram_16x32 fifo3
             ( .data_out(data_out3),
               .we(write & ~full & we_ram3),
               .data_in(data_in),
               .read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),
               .write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),
               .wclk(clk)
               );
        end // if (CNT_WIDTH==6)
 
   endgenerate
 `endif //  `ifdef ETH_FIFO_XILINX
 
   `ifdef ETH_FIFO_RAMB18
 
   wire [8:0]                       read_pointer_to_xilinx_ram;
   wire [8:0]                       read_pointer_preincremented;
   assign read_pointer_preincremented = read_pointer + 1;
 
   assign read_pointer_to_xilinx_ram = (read) ?
                                       read_pointer_preincremented :
                                       read_pointer;
 
   wire [8:0]                       write_pointer_to_xilinx_ram;
   assign write_pointer_to_xilinx_ram = {{(9-CNT_WIDTH){1'b0}},write_pointer};
 
   // synthesis translate_off
   // Port A - Write
   // Port B - Rread
   BLK_MEM_GEN_V3_1 #(
                      .C_ADDRA_WIDTH(9),
                      .C_ADDRB_WIDTH(9),
                      .C_ALGORITHM(1),
                      .C_BYTE_SIZE(9),
                      .C_COMMON_CLK(0),
                      .C_DEFAULT_DATA("0"),
                      .C_DISABLE_WARN_BHV_COLL(0),
                      .C_DISABLE_WARN_BHV_RANGE(0),
                      .C_FAMILY("virtex5"),
                      .C_HAS_ENA(0),
                      .C_HAS_ENB(0),
                      .C_HAS_INJECTERR(0),
                      .C_HAS_MEM_OUTPUT_REGS_A(0),
                      .C_HAS_MEM_OUTPUT_REGS_B(0),
                      .C_HAS_MUX_OUTPUT_REGS_A(0),
                      .C_HAS_MUX_OUTPUT_REGS_B(0),
                      .C_HAS_REGCEA(0),
                      .C_HAS_REGCEB(0),
                      .C_HAS_RSTA(0),
                      .C_HAS_RSTB(0),
                      .C_INITA_VAL("0"),
                      .C_INITB_VAL("0"),
                      .C_INIT_FILE_NAME("no_coe_file_loaded"),
                      .C_LOAD_INIT_FILE(0),
                      .C_MEM_TYPE(1),
                      .C_MUX_PIPELINE_STAGES(0),
                      .C_PRIM_TYPE(1),
                      .C_READ_DEPTH_A(512),
                      .C_READ_DEPTH_B(512),
                      .C_READ_WIDTH_A(32),
                      .C_READ_WIDTH_B(32),
                      .C_RSTRAM_A(0),
                      .C_RSTRAM_B(0),
                      .C_RST_PRIORITY_A("CE"),
                      .C_RST_PRIORITY_B("CE"),
                      .C_RST_TYPE("SYNC"),
                      .C_SIM_COLLISION_CHECK("WARNING_ONLY"),
                      .C_USE_BYTE_WEA(0),
                      .C_USE_BYTE_WEB(0),
                      .C_USE_DEFAULT_DATA(0),
                      .C_USE_ECC(0),
                      .C_WEA_WIDTH(1),
                      .C_WEB_WIDTH(1),
                      .C_WRITE_DEPTH_A(512),
                      .C_WRITE_DEPTH_B(512),
                      .C_WRITE_MODE_A("WRITE_FIRST"),
                      .C_WRITE_MODE_B("READ_FIRST"),
                      .C_WRITE_WIDTH_A(32),
                      .C_WRITE_WIDTH_B(32),
                      .C_XDEVICEFAMILY("virtex5"))
   inst (
         .CLKA(clk),
         .WEA(write),
         .ADDRA(write_pointer_to_xilinx_ram),
         .DINA(data_in),
         .CLKB(clk),
         .ADDRB(read_pointer_to_xilinx_ram),
         .DOUTB(data_out),
         .RSTA(reset),
         .ENA(),
         .REGCEA(),
         .DOUTA(),
         .RSTB(),
         .ENB(),
         .REGCEB(),
         .WEB(),
         .DINB(),
         .INJECTSBITERR(),
         .INJECTDBITERR(),
         .SBITERR(),
         .DBITERR(),
         .RDADDRECC()
         );
   // synthesis translate_on
   `endif //  `ifdef ETH_FIFO_RAMB18
 
 
 
 `ifdef ETH_ALTERA_ALTSYNCRAM
   altera_dpram_16x32   altera_dpram_16x32_inst
   (
    .data             (data_in),
    .wren             (write & ~full),
    .wraddress        (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),
    .rdaddress        (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),
    .clock            (clk),
    .q                (data_out)
    );  //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE
 `endif //  `ifdef ETH_ALTERA_ALTSYNCRAM
 
 
endmodule // eth_fifo
 

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_fifo.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	439	julius	`//// http://www.opencores.org/project,ethmac ////`
7	6	julius	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10	439	julius	`//// - Julius Baxter (julius@opencores.org) ////`
11	6	julius	`//// ////`
12			`//// All additional information is avaliable in the Readme.txt ////`
13			`//// file. ////`
14			`//// ////`
15			`//////////////////////////////////////////////////////////////////////`
16			`//// ////`
17			`//// Copyright (C) 2001 Authors ////`
18			`//// ////`
19			`//// This source file may be used and distributed without ////`
20			`//// restriction provided that this copyright statement is not ////`
21			`//// removed from the file and that any derivative work contains ////`
22			`//// the original copyright notice and the associated disclaimer. ////`
23			`//// ////`
24			`//// This source file is free software; you can redistribute it ////`
25			`//// and/or modify it under the terms of the GNU Lesser General ////`
26			`//// Public License as published by the Free Software Foundation; ////`
27			`//// either version 2.1 of the License, or (at your option) any ////`
28			`//// later version. ////`
29			`//// ////`
30			`//// This source is distributed in the hope that it will be ////`
31			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
32			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
33			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
34			`//// details. ////`
35			`//// ////`
36			`//// You should have received a copy of the GNU Lesser General ////`
37			`//// Public License along with this source; if not, download it ////`
38			`//// from http://www.opencores.org/lgpl.shtml ////`
39			`//// ////`
40			`//////////////////////////////////////////////////////////////////////`
41
42	409	julius	`include "ethmac_defines.v"
43	6	julius	`include "timescale.v"
44
45	439	julius	`module eth_fifo (data_in, data_out, clk, reset, write, read, clear,`
46			`almost_full, full, almost_empty, empty, cnt);`
47	6	julius
48	530	julius	`parameter DATA_WIDTH = 32;`
49			`parameter DEPTH = 8;`
50			`parameter CNT_WIDTH = 3;`
51	6	julius
52	530	julius	`input clk;`
53			`input reset;`
54			`input write;`
55			`input read;`
56			`input clear;`
57			`input [DATA_WIDTH-1:0] data_in;`
58	6	julius
59	530	julius	`output [DATA_WIDTH-1:0] data_out;`
60			`output almost_full;`
61			`output full;`
62			`output almost_empty;`
63			`output empty;`
64			`output [CNT_WIDTH-1:0] cnt;`
65	6	julius
66
67	530	julius	`reg [CNT_WIDTH-1:0] read_pointer;`
68			`reg [CNT_WIDTH-1:0] cnt;`
69	403	julius
70	530	julius	`always @ (posedge clk or posedge reset)`
71			`begin`
72			`if(reset)`
73			`cnt <= 0;`
74			`else`
75			`if(clear)`
76			`cnt <= { {(CNT_WIDTH-1){1'b0}}, read^write};`
77			`else`
78			`if(read ^ write)`
79			`if(read)`
80			`cnt <= cnt - 1;`
81			`else`
82			`cnt <= cnt + 1;`
83			`end`
84	6	julius
85	530	julius
86			`assign empty = ~(\|cnt);`
87			`assign almost_empty = cnt==1;`
88			`assign full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-1);`
89			`assign almost_full = {{32-CNT_WIDTH{1'b0}},cnt} == (DEPTH-2);`
90
91	403	julius
92			`ifdef ETH_FIFO_GENERIC
93
94			`reg [DATA_WIDTH-1:0] fifo [0:DEPTH-1] /synthesis syn_ramstyle = "no_rw_check"/ ;`
95
96
97	439	julius	`// This should make the synthesis tool infer a RAM`
98	530	julius	`reg [CNT_WIDTH-1:0] waddr, raddr, raddr_reg;`
99			`reg clear_reg; // Register the clear pulse`
100	439	julius
101	530	julius	`reg fallthrough_read;`
102			`reg [CNT_WIDTH-1:0] fallthrough_read_addr;`
103	439	julius
104	403	julius
105			`always @(posedge clk)`
106			`if (reset)`
107	439	julius	`fallthrough_read <= 0;`
108			`else`
109			`fallthrough_read <= empty & write;`
110
111			`always @(posedge clk)`
112			`if (empty & write)`
113			`fallthrough_read_addr <= waddr;`
114	530	julius
115	439	julius	`always @(posedge clk)`
116			`if (reset)`
117	403	julius	`waddr <= 0;`
118			`else if (write)`
119			`waddr <= waddr + 1;`
120
121			`always @(posedge clk)`
122			`if (reset)`
123			`raddr <= 0;`
124			`else if (clear)`
125			`raddr <= waddr;`
126	439	julius	`else if (read \| clear_reg)`
127	403	julius	`raddr <= raddr + 1;`
128
129			`always @ (posedge clk)`
130			`if (write & ~full)`
131			`fifo[waddr] <= data_in;`
132
133
134			`always @(posedge clk)`
135			`clear_reg <= clear;`
136
137			`always @ (posedge clk)`
138			`if (read \| clear_reg)`
139			`raddr_reg <= raddr;`
140	439	julius	`else if (fallthrough_read) // To pulse RE for fall-through on Xilinx`
141			`raddr_reg <= fallthrough_read_addr;`
142	403	julius
143			`assign data_out = fifo[raddr_reg];`
144
145	530	julius	`always @ (posedge clk or posedge reset)`
146			`begin`
147			`if(reset)`
148			`read_pointer <= 0;`
149			`else`
150			`if(clear)`
151			`// Begin read pointer at 1`
152			`read_pointer <= { {(CNT_WIDTH-1){1'b0}}, 1'b1};`
153			`else`
154			`if(read & ~empty)`
155			`read_pointer <= read_pointer + 1'b1;`
156			`end`
157	403	julius
158
159	530	julius	`else // !`ifdef ETH_FIFO_GENERIC
160	485	julius
161	530	julius	`reg [CNT_WIDTH-1:0] write_pointer;`
162	485	julius
163
164	530	julius	`always @ (posedge clk or posedge reset)`
165			`begin`
166			`if(reset)`
167			`read_pointer <= 0;`
168			`else`
169			`if(clear)`
170			`read_pointer <= { {(CNT_WIDTH-1){1'b0}}, read};`
171			`else`
172			`if(read & ~empty)`
173			`read_pointer <= read_pointer + 1'b1;`
174			`end`
175	485	julius
176	530	julius	`always @ (posedge clk or posedge reset)`
177			`begin`
178			`if(reset)`
179			`write_pointer <= 0;`
180			`else`
181			`if(clear)`
182			`write_pointer <= { {(CNT_WIDTH-1){1'b0}}, write};`
183			`else`
184			`if(write & ~full)`
185			`write_pointer <= write_pointer + 1'b1;`
186			`end // always @ (posedge clk or posedge reset)`
187	485	julius
188	530	julius	`endif // !`ifdef ETH_FIFO_GENERIC
189
190			`ifdef ETH_FIFO_XILINX
191	403	julius
192	530	julius	`generate`
193			`if (CNT_WIDTH==4)`
194			`begin`
195			`xilinx_dist_ram_16x32 fifo`
196			`( .data_out(data_out),`
197			`.we(write & ~full),`
198			`.data_in(data_in),`
199			`.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),`
200			`.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),`
201			`.wclk(clk)`
202			`);`
203			`end // if (CNT_WIDTH==4)`
204			`else if (CNT_WIDTH==6)`
205			`begin`
206	403	julius
207	530	julius	`wire [DATA_WIDTH-1:0] data_out0;`
208			`wire [DATA_WIDTH-1:0] data_out1;`
209			`wire [DATA_WIDTH-1:0] data_out2;`
210			`wire [DATA_WIDTH-1:0] data_out3;`
211
212			`wire we_ram0,we_ram1,we_ram2,we_ram3;`
213	6	julius
214	530	julius	`assign we_ram0 = (write_pointer[5:4]==2'b00);`
215			`assign we_ram1 = (write_pointer[5:4]==2'b01);`
216			`assign we_ram2 = (write_pointer[5:4]==2'b10);`
217			`assign we_ram3 = (write_pointer[5:4]==2'b11);`
218
219			`assign data_out = (read_pointer[5:4]==2'b11) ? data_out3 :`
220			`(read_pointer[5:4]==2'b10) ? data_out2 :`
221			`(read_pointer[5:4]==2'b01) ? data_out1 : data_out0;`
222
223			`xilinx_dist_ram_16x32 fifo0`
224			`( .data_out(data_out0),`
225			`.we(write & ~full & we_ram0),`
226			`.data_in(data_in),`
227			`.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),`
228			`.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),`
229			`.wclk(clk)`
230			`);`
231
232			`xilinx_dist_ram_16x32 fifo1`
233			`( .data_out(data_out1),`
234			`.we(write & ~full & we_ram1),`
235			`.data_in(data_in),`
236			`.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),`
237			`.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),`
238			`.wclk(clk)`
239			`);`
240	6	julius
241	530	julius	`xilinx_dist_ram_16x32 fifo2`
242			`( .data_out(data_out2),`
243			`.we(write & ~full & we_ram2),`
244			`.data_in(data_in),`
245			`.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),`
246			`.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),`
247			`.wclk(clk)`
248			`);`
249
250			`xilinx_dist_ram_16x32 fifo3`
251			`( .data_out(data_out3),`
252			`.we(write & ~full & we_ram3),`
253			`.data_in(data_in),`
254			`.read_address( clear ? {CNT_WIDTH-1{1'b0}} : read_pointer[3:0]),`
255			`.write_address(clear ? {CNT_WIDTH-1{1'b0}} : write_pointer[3:0]),`
256			`.wclk(clk)`
257			`);`
258			`end // if (CNT_WIDTH==6)`
259
260			`endgenerate`
261			`endif // `ifdef ETH_FIFO_XILINX
262	485	julius
263	530	julius	`ifdef ETH_FIFO_RAMB18
264	485	julius
265	530	julius	`wire [8:0] read_pointer_to_xilinx_ram;`
266			`wire [8:0] read_pointer_preincremented;`
267			`assign read_pointer_preincremented = read_pointer + 1;`
268	485	julius
269	530	julius	`assign read_pointer_to_xilinx_ram = (read) ?`
270			`read_pointer_preincremented :`
271			`read_pointer;`
272	485	julius
273	530	julius	`wire [8:0] write_pointer_to_xilinx_ram;`
274			`assign write_pointer_to_xilinx_ram = {{(9-CNT_WIDTH){1'b0}},write_pointer};`
275	485	julius
276	530	julius	`// synthesis translate_off`
277			`// Port A - Write`
278			`// Port B - Rread`
279			`BLK_MEM_GEN_V3_1 #(`
280			`.C_ADDRA_WIDTH(9),`
281			`.C_ADDRB_WIDTH(9),`
282			`.C_ALGORITHM(1),`
283			`.C_BYTE_SIZE(9),`
284			`.C_COMMON_CLK(0),`
285			`.C_DEFAULT_DATA("0"),`
286			`.C_DISABLE_WARN_BHV_COLL(0),`
287			`.C_DISABLE_WARN_BHV_RANGE(0),`
288			`.C_FAMILY("virtex5"),`
289			`.C_HAS_ENA(0),`
290			`.C_HAS_ENB(0),`
291			`.C_HAS_INJECTERR(0),`
292			`.C_HAS_MEM_OUTPUT_REGS_A(0),`
293			`.C_HAS_MEM_OUTPUT_REGS_B(0),`
294			`.C_HAS_MUX_OUTPUT_REGS_A(0),`
295			`.C_HAS_MUX_OUTPUT_REGS_B(0),`
296			`.C_HAS_REGCEA(0),`
297			`.C_HAS_REGCEB(0),`
298			`.C_HAS_RSTA(0),`
299			`.C_HAS_RSTB(0),`
300			`.C_INITA_VAL("0"),`
301			`.C_INITB_VAL("0"),`
302			`.C_INIT_FILE_NAME("no_coe_file_loaded"),`
303			`.C_LOAD_INIT_FILE(0),`
304			`.C_MEM_TYPE(1),`
305			`.C_MUX_PIPELINE_STAGES(0),`
306			`.C_PRIM_TYPE(1),`
307			`.C_READ_DEPTH_A(512),`
308			`.C_READ_DEPTH_B(512),`
309			`.C_READ_WIDTH_A(32),`
310			`.C_READ_WIDTH_B(32),`
311			`.C_RSTRAM_A(0),`
312			`.C_RSTRAM_B(0),`
313			`.C_RST_PRIORITY_A("CE"),`
314			`.C_RST_PRIORITY_B("CE"),`
315			`.C_RST_TYPE("SYNC"),`
316			`.C_SIM_COLLISION_CHECK("WARNING_ONLY"),`
317			`.C_USE_BYTE_WEA(0),`
318			`.C_USE_BYTE_WEB(0),`
319			`.C_USE_DEFAULT_DATA(0),`
320			`.C_USE_ECC(0),`
321			`.C_WEA_WIDTH(1),`
322			`.C_WEB_WIDTH(1),`
323			`.C_WRITE_DEPTH_A(512),`
324			`.C_WRITE_DEPTH_B(512),`
325			`.C_WRITE_MODE_A("WRITE_FIRST"),`
326			`.C_WRITE_MODE_B("READ_FIRST"),`
327			`.C_WRITE_WIDTH_A(32),`
328			`.C_WRITE_WIDTH_B(32),`
329			`.C_XDEVICEFAMILY("virtex5"))`
330			`inst (`
331			`.CLKA(clk),`
332			`.WEA(write),`
333			`.ADDRA(write_pointer_to_xilinx_ram),`
334			`.DINA(data_in),`
335			`.CLKB(clk),`
336			`.ADDRB(read_pointer_to_xilinx_ram),`
337			`.DOUTB(data_out),`
338			`.RSTA(reset),`
339			`.ENA(),`
340			`.REGCEA(),`
341			`.DOUTA(),`
342			`.RSTB(),`
343			`.ENB(),`
344			`.REGCEB(),`
345			`.WEB(),`
346			`.DINB(),`
347			`.INJECTSBITERR(),`
348			`.INJECTDBITERR(),`
349			`.SBITERR(),`
350			`.DBITERR(),`
351			`.RDADDRECC()`
352			`);`
353			`// synthesis translate_on`
354			`endif // `ifdef ETH_FIFO_RAMB18
355	6	julius
356
357	403	julius
358	530	julius	`ifdef ETH_ALTERA_ALTSYNCRAM
359			`altera_dpram_16x32 altera_dpram_16x32_inst`
360			`(`
361			`.data (data_in),`
362			`.wren (write & ~full),`
363			`.wraddress (clear ? {CNT_WIDTH-1{1'b0}} : write_pointer),`
364			`.rdaddress (clear ? {CNT_WIDTH-1{1'b0}} : read_pointer ),`
365			`.clock (clk),`
366			`.q (data_out)`
367			`); //exemplar attribute altera_dpram_16x32_inst NOOPT TRUE`
368			`endif // `ifdef ETH_ALTERA_ALTSYNCRAM
369
370	6	julius
371	530	julius	`endmodule // eth_fifo`
372	6	julius

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_fifo.v] - Blame information for rev 633