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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_macstatus.v                                             ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.16  2005/02/21 10:42:11  igorm
// Defer indication fixed.
//
// Revision 1.15  2003/01/30 13:28:19  tadejm
// Defer indication changed.
//
// Revision 1.14  2002/11/22 01:57:06  mohor
// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort
// synchronized.
//
// Revision 1.13  2002/11/13 22:30:58  tadejm
// Late collision is reported only when not in the full duplex.
// Sample is taken (for status) as soon as MRxDV is not valid (regardless
// of the received byte cnt).
//
// Revision 1.12  2002/09/12 14:50:16  mohor
// CarrierSenseLost bug fixed when operating in full duplex mode.
//
// Revision 1.11  2002/09/04 18:38:03  mohor
// CarrierSenseLost status is not set when working in loopback mode.
//
// Revision 1.10  2002/07/25 18:17:46  mohor
// InvalidSymbol generation changed.
//
// Revision 1.9  2002/04/22 13:51:44  mohor
// Short frame and ReceivedLengthOK were not detected correctly.
//
// Revision 1.8  2002/02/18 10:40:17  mohor
// Small fixes.
//
// Revision 1.7  2002/02/15 17:07:39  mohor
// Status was not written correctly when frames were discarted because of
// address mismatch.
//
// Revision 1.6  2002/02/11 09:18:21  mohor
// Tx status is written back to the BD.
//
// Revision 1.5  2002/02/08 16:21:54  mohor
// Rx status is written back to the BD.
//
// Revision 1.4  2002/01/23 10:28:16  mohor
// Link in the header changed.
//
// Revision 1.3  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2  2001/09/11 14:17:00  mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//
 
`include "timescale.v"
 
 
module eth_macstatus(
                      MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,
                      MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,
                      RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,
                      InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,
                      r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,
                      LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,
                      RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,
                      StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,
                      r_FullD
                    );
 
 
 
 
input         MRxClk;
input         Reset;
input         RxCrcError;
input         MRxErr;
input         MRxDV;
 
input         RxStateSFD;
input   [1:0] RxStateData;
input         RxStatePreamble;
input         RxStateIdle;
input         Transmitting;
input  [15:0] RxByteCnt;
input         RxByteCntEq0;
input         RxByteCntGreat2;
input         RxByteCntMaxFrame;
input   [3:0] MRxD;
input         Collision;
input   [5:0] CollValid;
input         r_RecSmall;
input  [15:0] r_MinFL;
input  [15:0] r_MaxFL;
input         r_HugEn;
input         StartTxDone;
input         StartTxAbort;
input   [3:0] RetryCnt;
input         MTxClk;
input         MaxCollisionOccured;
input         LateCollision;
input         DeferIndication;
input         TxStartFrm;
input         StatePreamble;
input   [1:0] StateData;
input         CarrierSense;
input         TxUsedData;
input         Loopback;
input         r_FullD;
 
 
output        ReceivedLengthOK;
output        ReceiveEnd;
output        ReceivedPacketGood;
output        InvalidSymbol;
output        LatchedCrcError;
output        RxLateCollision;
output        ShortFrame;
output        DribbleNibble;
output        ReceivedPacketTooBig;
output        LoadRxStatus;
output  [3:0] RetryCntLatched;
output        RetryLimit;
output        LateCollLatched;
output        DeferLatched;
input         RstDeferLatched;
output        CarrierSenseLost;
output        LatchedMRxErr;
 
 
reg           ReceiveEnd;
 
reg           LatchedCrcError;
reg           LatchedMRxErr;
reg           LoadRxStatus;
reg           InvalidSymbol;
reg     [3:0] RetryCntLatched;
reg           RetryLimit;
reg           LateCollLatched;
reg           DeferLatched;
reg           CarrierSenseLost;
 
wire          TakeSample;
wire          SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps 
 
// Crc error
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedCrcError <= 1'b0;
  else
  if(RxStateSFD)
    LatchedCrcError <= 1'b0;
  else
  if(RxStateData[0])
    LatchedCrcError <= RxCrcError & ~RxByteCntEq0;
end
 
 
// LatchedMRxErr
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LatchedMRxErr <= 1'b0;
  else
  if(MRxErr & MRxDV & (RxStatePreamble | RxStateSFD | (|RxStateData) | RxStateIdle & ~Transmitting))
    LatchedMRxErr <= 1'b1;
  else
    LatchedMRxErr <= 1'b0;
end
 
 
// ReceivedPacketGood
assign ReceivedPacketGood = ~LatchedCrcError;
 
 
// ReceivedLengthOK
assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];
 
 
 
 
 
// Time to take a sample
//assign TakeSample = |RxStateData     & ~MRxDV & RxByteCntGreat2  |
assign TakeSample = (|RxStateData)   & (~MRxDV)                    |
                      RxStateData[0] &   MRxDV & RxByteCntMaxFrame;
 
 
// LoadRxStatus
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    LoadRxStatus <= 1'b0;
  else
    LoadRxStatus <= TakeSample;
end
 
 
 
// ReceiveEnd
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceiveEnd  <= 1'b0;
  else
    ReceiveEnd  <= LoadRxStatus;
end
 
 
// Invalid Symbol received during 100Mbps mode
assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;
 
 
// InvalidSymbol
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    InvalidSymbol <= 1'b0;
  else
  if(LoadRxStatus & ~SetInvalidSymbol)
    InvalidSymbol <= 1'b0;
  else
  if(SetInvalidSymbol)
    InvalidSymbol <= 1'b1;
end
 
 
// Late Collision
 
reg RxLateCollision;
reg RxColWindow;
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxLateCollision <= 1'b0;
  else
  if(LoadRxStatus)
    RxLateCollision <= 1'b0;
  else
  if(Collision & (~r_FullD) & (~RxColWindow | r_RecSmall))
    RxLateCollision <= 1'b1;
end
 
// Collision Window
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    RxColWindow <= 1'b1;
  else
  if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])
    RxColWindow <= 1'b0;
  else
  if(RxStateIdle)
    RxColWindow <= 1'b1;
end
 
 
// ShortFrame
reg ShortFrame;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ShortFrame <= 1'b0;
  else
  if(LoadRxStatus)
    ShortFrame <= 1'b0;
  else
  if(TakeSample)
    ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0];
end
 
 
// DribbleNibble
reg DribbleNibble;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    DribbleNibble <= 1'b0;
  else
  if(RxStateSFD)
    DribbleNibble <= 1'b0;
  else
  if(~MRxDV & RxStateData[1])
    DribbleNibble <= 1'b1;
end
 
 
reg ReceivedPacketTooBig;
always @ (posedge MRxClk or posedge Reset)
begin
  if(Reset)
    ReceivedPacketTooBig <= 1'b0;
  else
  if(LoadRxStatus)
    ReceivedPacketTooBig <= 1'b0;
  else
  if(TakeSample)
    ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];
end
 
 
 
// Latched Retry counter for tx status
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryCntLatched <= 4'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryCntLatched <= RetryCnt;
end
 
 
// Latched Retransmission limit
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    RetryLimit <= 1'h0;
  else
  if(StartTxDone | StartTxAbort)
    RetryLimit <= MaxCollisionOccured;
end
 
 
// Latched Late Collision
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    LateCollLatched <= 1'b0;
  else
  if(StartTxDone | StartTxAbort)
    LateCollLatched <= LateCollision;
end
 
 
 
// Latched Defer state
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    DeferLatched <= 1'b0;
  else
  if(DeferIndication)
    DeferLatched <= 1'b1;
  else
  if(RstDeferLatched)
    DeferLatched <= 1'b0;
end
 
 
// CarrierSenseLost
always @ (posedge MTxClk or posedge Reset)
begin
  if(Reset)
    CarrierSenseLost <= 1'b0;
  else
  if((StatePreamble | (|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)
    CarrierSenseLost <= 1'b1;
  else
  if(TxStartFrm)
    CarrierSenseLost <= 1'b0;
end
 
 
endmodule

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_macstatus.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	570	olof	`//// http://www.opencores.org/project,ethmac ////`
7	6	julius	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is available in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43	403	julius	`// $Log: not supported by cvs2svn $`
44	6	julius	`// Revision 1.16 2005/02/21 10:42:11 igorm`
45			`// Defer indication fixed.`
46			`//`
47			`// Revision 1.15 2003/01/30 13:28:19 tadejm`
48			`// Defer indication changed.`
49			`//`
50			`// Revision 1.14 2002/11/22 01:57:06 mohor`
51			`// Rx Flow control fixed. CF flag added to the RX buffer descriptor. RxAbort`
52			`// synchronized.`
53			`//`
54			`// Revision 1.13 2002/11/13 22:30:58 tadejm`
55			`// Late collision is reported only when not in the full duplex.`
56			`// Sample is taken (for status) as soon as MRxDV is not valid (regardless`
57			`// of the received byte cnt).`
58			`//`
59			`// Revision 1.12 2002/09/12 14:50:16 mohor`
60			`// CarrierSenseLost bug fixed when operating in full duplex mode.`
61			`//`
62			`// Revision 1.11 2002/09/04 18:38:03 mohor`
63			`// CarrierSenseLost status is not set when working in loopback mode.`
64			`//`
65			`// Revision 1.10 2002/07/25 18:17:46 mohor`
66			`// InvalidSymbol generation changed.`
67			`//`
68			`// Revision 1.9 2002/04/22 13:51:44 mohor`
69			`// Short frame and ReceivedLengthOK were not detected correctly.`
70			`//`
71			`// Revision 1.8 2002/02/18 10:40:17 mohor`
72			`// Small fixes.`
73			`//`
74			`// Revision 1.7 2002/02/15 17:07:39 mohor`
75			`// Status was not written correctly when frames were discarted because of`
76			`// address mismatch.`
77			`//`
78			`// Revision 1.6 2002/02/11 09:18:21 mohor`
79			`// Tx status is written back to the BD.`
80			`//`
81			`// Revision 1.5 2002/02/08 16:21:54 mohor`
82			`// Rx status is written back to the BD.`
83			`//`
84			`// Revision 1.4 2002/01/23 10:28:16 mohor`
85			`// Link in the header changed.`
86			`//`
87			`// Revision 1.3 2001/10/19 08:43:51 mohor`
88			`// eth_timescale.v changed to timescale.v This is done because of the`
89			`// simulation of the few cores in a one joined project.`
90			`//`
91			`// Revision 1.2 2001/09/11 14:17:00 mohor`
92			`// Few little NCSIM warnings fixed.`
93			`//`
94			`// Revision 1.1 2001/08/06 14:44:29 mohor`
95			`// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).`
96			`// Include files fixed to contain no path.`
97			`// File names and module names changed ta have a eth_ prologue in the name.`
98			`// File eth_timescale.v is used to define timescale`
99			`// All pin names on the top module are changed to contain _I, _O or _OE at the end.`
100			`// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O`
101			`// and Mdo_OE. The bidirectional signal must be created on the top level. This`
102			`// is done due to the ASIC tools.`
103			`//`
104			`// Revision 1.1 2001/07/30 21:23:42 mohor`
105			`// Directory structure changed. Files checked and joind together.`
106			`//`
107			`//`
108			`//`
109			`//`
110			`//`
111
112			`include "timescale.v"
113
114
115			`module eth_macstatus(`
116			`MRxClk, Reset, ReceivedLengthOK, ReceiveEnd, ReceivedPacketGood, RxCrcError,`
117			`MRxErr, MRxDV, RxStateSFD, RxStateData, RxStatePreamble, RxStateIdle, Transmitting,`
118			`RxByteCnt, RxByteCntEq0, RxByteCntGreat2, RxByteCntMaxFrame,`
119			`InvalidSymbol, MRxD, LatchedCrcError, Collision, CollValid, RxLateCollision,`
120			`r_RecSmall, r_MinFL, r_MaxFL, ShortFrame, DribbleNibble, ReceivedPacketTooBig, r_HugEn,`
121			`LoadRxStatus, StartTxDone, StartTxAbort, RetryCnt, RetryCntLatched, MTxClk, MaxCollisionOccured,`
122			`RetryLimit, LateCollision, LateCollLatched, DeferIndication, DeferLatched, RstDeferLatched, TxStartFrm,`
123			`StatePreamble, StateData, CarrierSense, CarrierSenseLost, TxUsedData, LatchedMRxErr, Loopback,`
124			`r_FullD`
125			`);`
126
127
128
129
130			`input MRxClk;`
131			`input Reset;`
132			`input RxCrcError;`
133			`input MRxErr;`
134			`input MRxDV;`
135
136			`input RxStateSFD;`
137			`input [1:0] RxStateData;`
138			`input RxStatePreamble;`
139			`input RxStateIdle;`
140			`input Transmitting;`
141			`input [15:0] RxByteCnt;`
142			`input RxByteCntEq0;`
143			`input RxByteCntGreat2;`
144			`input RxByteCntMaxFrame;`
145			`input [3:0] MRxD;`
146			`input Collision;`
147			`input [5:0] CollValid;`
148			`input r_RecSmall;`
149			`input [15:0] r_MinFL;`
150			`input [15:0] r_MaxFL;`
151			`input r_HugEn;`
152			`input StartTxDone;`
153			`input StartTxAbort;`
154			`input [3:0] RetryCnt;`
155			`input MTxClk;`
156			`input MaxCollisionOccured;`
157			`input LateCollision;`
158			`input DeferIndication;`
159			`input TxStartFrm;`
160			`input StatePreamble;`
161			`input [1:0] StateData;`
162			`input CarrierSense;`
163			`input TxUsedData;`
164			`input Loopback;`
165			`input r_FullD;`
166
167
168			`output ReceivedLengthOK;`
169			`output ReceiveEnd;`
170			`output ReceivedPacketGood;`
171			`output InvalidSymbol;`
172			`output LatchedCrcError;`
173			`output RxLateCollision;`
174			`output ShortFrame;`
175			`output DribbleNibble;`
176			`output ReceivedPacketTooBig;`
177			`output LoadRxStatus;`
178			`output [3:0] RetryCntLatched;`
179			`output RetryLimit;`
180			`output LateCollLatched;`
181			`output DeferLatched;`
182			`input RstDeferLatched;`
183			`output CarrierSenseLost;`
184			`output LatchedMRxErr;`
185
186
187			`reg ReceiveEnd;`
188
189			`reg LatchedCrcError;`
190			`reg LatchedMRxErr;`
191			`reg LoadRxStatus;`
192			`reg InvalidSymbol;`
193			`reg [3:0] RetryCntLatched;`
194			`reg RetryLimit;`
195			`reg LateCollLatched;`
196			`reg DeferLatched;`
197			`reg CarrierSenseLost;`
198
199			`wire TakeSample;`
200			`wire SetInvalidSymbol; // Invalid symbol was received during reception in 100Mbps`
201
202			`// Crc error`
203			`always @ (posedge MRxClk or posedge Reset)`
204			`begin`
205			`if(Reset)`
206	403	julius	`LatchedCrcError <= 1'b0;`
207	6	julius	`else`
208			`if(RxStateSFD)`
209	403	julius	`LatchedCrcError <= 1'b0;`
210	6	julius	`else`
211			`if(RxStateData[0])`
212	403	julius	`LatchedCrcError <= RxCrcError & ~RxByteCntEq0;`
213	6	julius	`end`
214
215
216			`// LatchedMRxErr`
217			`always @ (posedge MRxClk or posedge Reset)`
218			`begin`
219			`if(Reset)`
220	403	julius	`LatchedMRxErr <= 1'b0;`
221	6	julius	`else`
222			`if(MRxErr & MRxDV & (RxStatePreamble \| RxStateSFD \| (\|RxStateData) \| RxStateIdle & ~Transmitting))`
223	403	julius	`LatchedMRxErr <= 1'b1;`
224	6	julius	`else`
225	403	julius	`LatchedMRxErr <= 1'b0;`
226	6	julius	`end`
227
228
229			`// ReceivedPacketGood`
230			`assign ReceivedPacketGood = ~LatchedCrcError;`
231
232
233			`// ReceivedLengthOK`
234			`assign ReceivedLengthOK = RxByteCnt[15:0] >= r_MinFL[15:0] & RxByteCnt[15:0] <= r_MaxFL[15:0];`
235
236
237
238
239
240			`// Time to take a sample`
241			`//assign TakeSample = \|RxStateData & ~MRxDV & RxByteCntGreat2 \|`
242			`assign TakeSample = (\|RxStateData) & (~MRxDV) \|`
243			`RxStateData[0] & MRxDV & RxByteCntMaxFrame;`
244
245
246			`// LoadRxStatus`
247			`always @ (posedge MRxClk or posedge Reset)`
248			`begin`
249			`if(Reset)`
250	403	julius	`LoadRxStatus <= 1'b0;`
251	6	julius	`else`
252	403	julius	`LoadRxStatus <= TakeSample;`
253	6	julius	`end`
254
255
256
257			`// ReceiveEnd`
258			`always @ (posedge MRxClk or posedge Reset)`
259			`begin`
260			`if(Reset)`
261	403	julius	`ReceiveEnd <= 1'b0;`
262	6	julius	`else`
263	403	julius	`ReceiveEnd <= LoadRxStatus;`
264	6	julius	`end`
265
266
267			`// Invalid Symbol received during 100Mbps mode`
268			`assign SetInvalidSymbol = MRxDV & MRxErr & MRxD[3:0] == 4'he;`
269
270
271			`// InvalidSymbol`
272			`always @ (posedge MRxClk or posedge Reset)`
273			`begin`
274			`if(Reset)`
275	403	julius	`InvalidSymbol <= 1'b0;`
276	6	julius	`else`
277			`if(LoadRxStatus & ~SetInvalidSymbol)`
278	403	julius	`InvalidSymbol <= 1'b0;`
279	6	julius	`else`
280			`if(SetInvalidSymbol)`
281	403	julius	`InvalidSymbol <= 1'b1;`
282	6	julius	`end`
283
284
285			`// Late Collision`
286
287			`reg RxLateCollision;`
288			`reg RxColWindow;`
289			`// Collision Window`
290			`always @ (posedge MRxClk or posedge Reset)`
291			`begin`
292			`if(Reset)`
293	403	julius	`RxLateCollision <= 1'b0;`
294	6	julius	`else`
295			`if(LoadRxStatus)`
296	403	julius	`RxLateCollision <= 1'b0;`
297	6	julius	`else`
298			`if(Collision & (~r_FullD) & (~RxColWindow \| r_RecSmall))`
299	403	julius	`RxLateCollision <= 1'b1;`
300	6	julius	`end`
301
302			`// Collision Window`
303			`always @ (posedge MRxClk or posedge Reset)`
304			`begin`
305			`if(Reset)`
306	403	julius	`RxColWindow <= 1'b1;`
307	6	julius	`else`
308			`if(~Collision & RxByteCnt[5:0] == CollValid[5:0] & RxStateData[1])`
309	403	julius	`RxColWindow <= 1'b0;`
310	6	julius	`else`
311			`if(RxStateIdle)`
312	403	julius	`RxColWindow <= 1'b1;`
313	6	julius	`end`
314
315
316			`// ShortFrame`
317			`reg ShortFrame;`
318			`always @ (posedge MRxClk or posedge Reset)`
319			`begin`
320			`if(Reset)`
321	403	julius	`ShortFrame <= 1'b0;`
322	6	julius	`else`
323			`if(LoadRxStatus)`
324	403	julius	`ShortFrame <= 1'b0;`
325	6	julius	`else`
326			`if(TakeSample)`
327	403	julius	`ShortFrame <= RxByteCnt[15:0] < r_MinFL[15:0];`
328	6	julius	`end`
329
330
331			`// DribbleNibble`
332			`reg DribbleNibble;`
333			`always @ (posedge MRxClk or posedge Reset)`
334			`begin`
335			`if(Reset)`
336	403	julius	`DribbleNibble <= 1'b0;`
337	6	julius	`else`
338			`if(RxStateSFD)`
339	403	julius	`DribbleNibble <= 1'b0;`
340	6	julius	`else`
341			`if(~MRxDV & RxStateData[1])`
342	403	julius	`DribbleNibble <= 1'b1;`
343	6	julius	`end`
344
345
346			`reg ReceivedPacketTooBig;`
347			`always @ (posedge MRxClk or posedge Reset)`
348			`begin`
349			`if(Reset)`
350	403	julius	`ReceivedPacketTooBig <= 1'b0;`
351	6	julius	`else`
352			`if(LoadRxStatus)`
353	403	julius	`ReceivedPacketTooBig <= 1'b0;`
354	6	julius	`else`
355			`if(TakeSample)`
356	403	julius	`ReceivedPacketTooBig <= ~r_HugEn & RxByteCnt[15:0] > r_MaxFL[15:0];`
357	6	julius	`end`
358
359
360
361			`// Latched Retry counter for tx status`
362			`always @ (posedge MTxClk or posedge Reset)`
363			`begin`
364			`if(Reset)`
365	403	julius	`RetryCntLatched <= 4'h0;`
366	6	julius	`else`
367			`if(StartTxDone \| StartTxAbort)`
368	403	julius	`RetryCntLatched <= RetryCnt;`
369	6	julius	`end`
370
371
372			`// Latched Retransmission limit`
373			`always @ (posedge MTxClk or posedge Reset)`
374			`begin`
375			`if(Reset)`
376	403	julius	`RetryLimit <= 1'h0;`
377	6	julius	`else`
378			`if(StartTxDone \| StartTxAbort)`
379	403	julius	`RetryLimit <= MaxCollisionOccured;`
380	6	julius	`end`
381
382
383			`// Latched Late Collision`
384			`always @ (posedge MTxClk or posedge Reset)`
385			`begin`
386			`if(Reset)`
387	403	julius	`LateCollLatched <= 1'b0;`
388	6	julius	`else`
389			`if(StartTxDone \| StartTxAbort)`
390	403	julius	`LateCollLatched <= LateCollision;`
391	6	julius	`end`
392
393
394
395			`// Latched Defer state`
396			`always @ (posedge MTxClk or posedge Reset)`
397			`begin`
398			`if(Reset)`
399	403	julius	`DeferLatched <= 1'b0;`
400	6	julius	`else`
401			`if(DeferIndication)`
402	403	julius	`DeferLatched <= 1'b1;`
403	6	julius	`else`
404			`if(RstDeferLatched)`
405	403	julius	`DeferLatched <= 1'b0;`
406	6	julius	`end`
407
408
409			`// CarrierSenseLost`
410			`always @ (posedge MTxClk or posedge Reset)`
411			`begin`
412			`if(Reset)`
413	403	julius	`CarrierSenseLost <= 1'b0;`
414	6	julius	`else`
415			`if((StatePreamble \| (\|StateData)) & ~CarrierSense & ~Loopback & ~Collision & ~r_FullD)`
416	403	julius	`CarrierSenseLost <= 1'b1;`
417	6	julius	`else`
418			`if(TxStartFrm)`
419	403	julius	`CarrierSenseLost <= 1'b0;`
420	6	julius	`end`
421
422
423			`endmodule`

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