URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_rxethmac.v] - Blame information for rev 445

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_rxethmac.v                                              ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`include "timescale.v"
 
 
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
                     HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
                     ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
                     CrcError, StateIdle, StatePreamble, StateSFD, StateData,
                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
                     PassAll, ControlFrmAddressOK
                     );
 
   input         MRxClk;
   input         MRxDV;
   input [3:0]    MRxD;
   input         Transmitting;
   input         HugEn;
   input         DlyCrcEn;
   input [15:0]  MaxFL;
   input         r_IFG;
   input         Reset;
   input [47:0]  MAC;     //  Station Address  
   input         r_Bro;   //  broadcast disable
   input         r_Pro;   //  promiscuous enable 
   input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
   input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
   input         PassAll;
   input         ControlFrmAddressOK;
 
   output [7:0]  RxData;
   output        RxValid;
   output        RxStartFrm;
   output        RxEndFrm;
   output [15:0] ByteCnt;
   output        ByteCntEq0;
   output        ByteCntGreat2;
   output        ByteCntMaxFrame;
   output        CrcError;
   output        StateIdle;
   output        StatePreamble;
   output        StateSFD;
   output [1:0]  StateData;
   output        RxAbort;
   output        AddressMiss;
 
   reg [7:0]      RxData;
   reg           RxValid;
   reg           RxStartFrm;
   reg           RxEndFrm;
   reg           Broadcast;
   reg           Multicast;
   reg [5:0]      CrcHash;
   reg           CrcHashGood;
   reg           DelayData;
   reg [7:0]      LatchedByte;
   reg [7:0]      RxData_d;
   reg           RxValid_d;
   reg           RxStartFrm_d;
   reg           RxEndFrm_d;
 
   wire          MRxDEqD;
   wire          MRxDEq5;
   wire          StateDrop;
   wire          ByteCntEq1;
   wire          ByteCntEq2;
   wire          ByteCntEq3;
   wire          ByteCntEq4;
   wire          ByteCntEq5;
   wire          ByteCntEq6;
   wire          ByteCntEq7;
   wire          ByteCntSmall7;
   wire [31:0]    Crc;
   wire          Enable_Crc;
   wire          Initialize_Crc;
   wire [3:0]     Data_Crc;
   wire          GenerateRxValid;
   wire          GenerateRxStartFrm;
   wire          GenerateRxEndFrm;
   wire          DribbleRxEndFrm;
   wire [3:0]     DlyCrcCnt;
   wire          IFGCounterEq24;
 
   assign MRxDEqD = MRxD == 4'hd;
   assign MRxDEq5 = MRxD == 4'h5;
 
 
   // Rx State Machine module
   eth_rxstatem rxstatem1
     (
      .MRxClk(MRxClk),
      .Reset(Reset),
      .MRxDV(MRxDV),
      .ByteCntEq0(ByteCntEq0),
      .ByteCntGreat2(ByteCntGreat2),
      .Transmitting(Transmitting),
      .MRxDEq5(MRxDEq5),
      .MRxDEqD(MRxDEqD),
      .IFGCounterEq24(IFGCounterEq24),
      .ByteCntMaxFrame(ByteCntMaxFrame),
      .StateData(StateData),
      .StateIdle(StateIdle),
      .StatePreamble(StatePreamble),
      .StateSFD(StateSFD),
      .StateDrop(StateDrop)
      );
 
 
   // Rx Counters module
   eth_rxcounters rxcounters1
     (.MRxClk(MRxClk),
      .Reset(Reset),
      .MRxDV(MRxDV),
      .StateIdle(StateIdle),
      .StateSFD(StateSFD),
      .StateData(StateData),
      .StateDrop(StateDrop),
      .StatePreamble(StatePreamble),
      .MRxDEqD(MRxDEqD),
      .DlyCrcEn(DlyCrcEn),
      .DlyCrcCnt(DlyCrcCnt),
      .Transmitting(Transmitting),
      .MaxFL(MaxFL),
      .r_IFG(r_IFG),
      .HugEn(HugEn),
      .IFGCounterEq24(IFGCounterEq24),
      .ByteCntEq0(ByteCntEq0),
      .ByteCntEq1(ByteCntEq1),
      .ByteCntEq2(ByteCntEq2),
      .ByteCntEq3(ByteCntEq3),
      .ByteCntEq4(ByteCntEq4),
      .ByteCntEq5(ByteCntEq5),
      .ByteCntEq6(ByteCntEq6),
      .ByteCntEq7(ByteCntEq7),
      .ByteCntGreat2(ByteCntGreat2),
      .ByteCntSmall7(ByteCntSmall7),
      .ByteCntMaxFrame(ByteCntMaxFrame),
      .ByteCntOut(ByteCnt)
      );
 
   // Rx Address Check
 
   eth_rxaddrcheck rxaddrcheck1
     (.MRxClk(MRxClk),
      .Reset( Reset),
      .RxData(RxData),
      .Broadcast (Broadcast),
      .r_Bro (r_Bro),
      .r_Pro(r_Pro),
      .ByteCntEq6(ByteCntEq6),
      .ByteCntEq7(ByteCntEq7),
      .ByteCntEq2(ByteCntEq2),
      .ByteCntEq3(ByteCntEq3),
      .ByteCntEq4(ByteCntEq4),
      .ByteCntEq5(ByteCntEq5),
      .HASH0(r_HASH0),
      .HASH1(r_HASH1),
      .CrcHash(CrcHash),
      .CrcHashGood(CrcHashGood),
      .StateData(StateData),
      .Multicast(Multicast),
      .MAC(MAC),
      .RxAbort(RxAbort),
      .RxEndFrm(RxEndFrm),
      .AddressMiss(AddressMiss),
      .PassAll(PassAll),
      .ControlFrmAddressOK(ControlFrmAddressOK)
      );
 
 
   assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
   assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
                           DlyCrcCnt[3:0] < 4'h9;
 
   assign Data_Crc[0] = MRxD[3];
   assign Data_Crc[1] = MRxD[2];
   assign Data_Crc[2] = MRxD[1];
   assign Data_Crc[3] = MRxD[0];
 
 
   // Connecting module Crc
   eth_crc crcrx
     (.Clk(MRxClk),
      .Reset(Reset),
      .Data(Data_Crc),
      .Enable(Enable_Crc),
      .Initialize(Initialize_Crc),
      .Crc(Crc), .CrcError(CrcError)
      );
 
 
 
   // Latching CRC for use in the hash table
 
   always @ (posedge MRxClk)
     begin
        CrcHashGood <=  StateData[0] & ByteCntEq6;
     end
 
   always @ (posedge MRxClk)
     begin
        if(Reset | StateIdle)
          CrcHash[5:0] <=  6'h0;
        else
          if(StateData[0] & ByteCntEq6)
            CrcHash[5:0] <=  Crc[31:26];
     end
 
 
   // Output byte stream
   always @ (posedge MRxClk or posedge Reset)
     begin
        if(Reset)
          begin
             RxData_d[7:0]      <=  8'h0;
             DelayData          <=  1'b0;
             LatchedByte[7:0]   <=  8'h0;
             RxData[7:0]        <=  8'h0;
          end
        else
          begin
             // Latched byte
             LatchedByte[7:0]   <=  {MRxD[3:0], LatchedByte[7:4]};
 
             DelayData          <=  StateData[0];
 
             if(GenerateRxValid)
               // Data goes through only in data state 
               RxData_d[7:0] <=  LatchedByte[7:0] & {8{|StateData}};
             else
               if(~DelayData)
                 // Delaying data to be valid for two cycles. 
                 // Zero when not active.
                 RxData_d[7:0] <=  8'h0;
 
             RxData[7:0] <=  RxData_d[7:0];          // Output data byte
          end
     end
 
 
 
   always @ (posedge MRxClk or posedge Reset)
     begin
        if(Reset)
          Broadcast <=  1'b0;
        else
          begin
             if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
               Broadcast <=  1'b0;
             else
               if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
                 Broadcast <=  1'b1;
               else
                 if(RxAbort | RxEndFrm)
                   Broadcast <=  1'b0;
          end
     end
 
 
   always @ (posedge MRxClk or posedge Reset)
     begin
        if(Reset)
          Multicast <=  1'b0;
        else
          begin
             if(StateData[0] & ByteCntEq1 & LatchedByte[0])
               Multicast <=  1'b1;
             else if(RxAbort | RxEndFrm)
               Multicast <=  1'b0;
          end
     end
 
 
   assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
 
   always @ (posedge MRxClk or posedge Reset)
     begin
        if(Reset)
          begin
             RxValid_d <=  1'b0;
             RxValid   <=  1'b0;
          end
        else
          begin
             RxValid_d <=  GenerateRxValid;
             RxValid   <=  RxValid_d;
          end
     end
 
 
   assign GenerateRxStartFrm = StateData[0] &
                               ((ByteCntEq1 & ~DlyCrcEn) |
                                ((DlyCrcCnt == 4'h3) & DlyCrcEn));
 
   always @ (posedge MRxClk or posedge Reset)
     begin
        if(Reset)
          begin
             RxStartFrm_d <=  1'b0;
             RxStartFrm   <=  1'b0;
          end
        else
          begin
             RxStartFrm_d <=  GenerateRxStartFrm;
             RxStartFrm   <=  RxStartFrm_d;
          end
     end
 
 
   assign GenerateRxEndFrm = StateData[0] &
                             (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
   assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
 
 
   always @ (posedge MRxClk or posedge Reset)
     begin
        if(Reset)
          begin
             RxEndFrm_d <=  1'b0;
             RxEndFrm   <=  1'b0;
          end
        else
          begin
             RxEndFrm_d <=  GenerateRxEndFrm;
             RxEndFrm   <=  RxEndFrm_d | DribbleRxEndFrm;
          end
     end
 
 
endmodule

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_rxethmac.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	409	julius	`//// http://www.opencores.org/project,ethmac ////`
7	6	julius	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// - Novan Hartadi (novan@vlsi.itb.ac.id) ////`
11			`//// - Mahmud Galela (mgalela@vlsi.itb.ac.id) ////`
12			`//// ////`
13			`//// All additional information is avaliable in the Readme.txt ////`
14			`//// file. ////`
15			`//// ////`
16			`//////////////////////////////////////////////////////////////////////`
17			`//// ////`
18			`//// Copyright (C) 2001 Authors ////`
19			`//// ////`
20			`//// This source file may be used and distributed without ////`
21			`//// restriction provided that this copyright statement is not ////`
22			`//// removed from the file and that any derivative work contains ////`
23			`//// the original copyright notice and the associated disclaimer. ////`
24			`//// ////`
25			`//// This source file is free software; you can redistribute it ////`
26			`//// and/or modify it under the terms of the GNU Lesser General ////`
27			`//// Public License as published by the Free Software Foundation; ////`
28			`//// either version 2.1 of the License, or (at your option) any ////`
29			`//// later version. ////`
30			`//// ////`
31			`//// This source is distributed in the hope that it will be ////`
32			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
33			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
34			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
35			`//// details. ////`
36			`//// ////`
37			`//// You should have received a copy of the GNU Lesser General ////`
38			`//// Public License along with this source; if not, download it ////`
39			`//// from http://www.opencores.org/lgpl.shtml ////`
40			`//// ////`
41			`//////////////////////////////////////////////////////////////////////`
42
43			`include "timescale.v"
44
45
46	439	julius	`module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,`
47			`HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,`
48			`ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,`
49			`CrcError, StateIdle, StatePreamble, StateSFD, StateData,`
50			`MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,`
51			`PassAll, ControlFrmAddressOK`
52			`);`
53	6	julius
54	439	julius	`input MRxClk;`
55			`input MRxDV;`
56			`input [3:0] MRxD;`
57			`input Transmitting;`
58			`input HugEn;`
59			`input DlyCrcEn;`
60			`input [15:0] MaxFL;`
61			`input r_IFG;`
62			`input Reset;`
63			`input [47:0] MAC; // Station Address`
64			`input r_Bro; // broadcast disable`
65			`input r_Pro; // promiscuous enable`
66			`input [31:0] r_HASH0; // lower 4 bytes Hash Table`
67			`input [31:0] r_HASH1; // upper 4 bytes Hash Table`
68			`input PassAll;`
69			`input ControlFrmAddressOK;`
70	6	julius
71	439	julius	`output [7:0] RxData;`
72			`output RxValid;`
73			`output RxStartFrm;`
74			`output RxEndFrm;`
75			`output [15:0] ByteCnt;`
76			`output ByteCntEq0;`
77			`output ByteCntGreat2;`
78			`output ByteCntMaxFrame;`
79			`output CrcError;`
80			`output StateIdle;`
81			`output StatePreamble;`
82			`output StateSFD;`
83			`output [1:0] StateData;`
84			`output RxAbort;`
85			`output AddressMiss;`
86	6	julius
87	439	julius	`reg [7:0] RxData;`
88			`reg RxValid;`
89			`reg RxStartFrm;`
90			`reg RxEndFrm;`
91			`reg Broadcast;`
92			`reg Multicast;`
93			`reg [5:0] CrcHash;`
94			`reg CrcHashGood;`
95			`reg DelayData;`
96			`reg [7:0] LatchedByte;`
97			`reg [7:0] RxData_d;`
98			`reg RxValid_d;`
99			`reg RxStartFrm_d;`
100			`reg RxEndFrm_d;`
101	6	julius
102	439	julius	`wire MRxDEqD;`
103			`wire MRxDEq5;`
104			`wire StateDrop;`
105			`wire ByteCntEq1;`
106			`wire ByteCntEq2;`
107			`wire ByteCntEq3;`
108			`wire ByteCntEq4;`
109			`wire ByteCntEq5;`
110			`wire ByteCntEq6;`
111			`wire ByteCntEq7;`
112			`wire ByteCntSmall7;`
113			`wire [31:0] Crc;`
114			`wire Enable_Crc;`
115			`wire Initialize_Crc;`
116			`wire [3:0] Data_Crc;`
117			`wire GenerateRxValid;`
118			`wire GenerateRxStartFrm;`
119			`wire GenerateRxEndFrm;`
120			`wire DribbleRxEndFrm;`
121			`wire [3:0] DlyCrcCnt;`
122			`wire IFGCounterEq24;`
123	6	julius
124	439	julius	`assign MRxDEqD = MRxD == 4'hd;`
125			`assign MRxDEq5 = MRxD == 4'h5;`
126	6	julius
127
128	439	julius	`// Rx State Machine module`
129			`eth_rxstatem rxstatem1`
130			`(`
131			`.MRxClk(MRxClk),`
132			`.Reset(Reset),`
133			`.MRxDV(MRxDV),`
134			`.ByteCntEq0(ByteCntEq0),`
135			`.ByteCntGreat2(ByteCntGreat2),`
136			`.Transmitting(Transmitting),`
137			`.MRxDEq5(MRxDEq5),`
138			`.MRxDEqD(MRxDEqD),`
139			`.IFGCounterEq24(IFGCounterEq24),`
140			`.ByteCntMaxFrame(ByteCntMaxFrame),`
141			`.StateData(StateData),`
142			`.StateIdle(StateIdle),`
143			`.StatePreamble(StatePreamble),`
144			`.StateSFD(StateSFD),`
145			`.StateDrop(StateDrop)`
146			`);`
147	6	julius
148
149	439	julius	`// Rx Counters module`
150			`eth_rxcounters rxcounters1`
151			`(.MRxClk(MRxClk),`
152			`.Reset(Reset),`
153			`.MRxDV(MRxDV),`
154			`.StateIdle(StateIdle),`
155			`.StateSFD(StateSFD),`
156			`.StateData(StateData),`
157			`.StateDrop(StateDrop),`
158			`.StatePreamble(StatePreamble),`
159			`.MRxDEqD(MRxDEqD),`
160			`.DlyCrcEn(DlyCrcEn),`
161			`.DlyCrcCnt(DlyCrcCnt),`
162			`.Transmitting(Transmitting),`
163			`.MaxFL(MaxFL),`
164			`.r_IFG(r_IFG),`
165			`.HugEn(HugEn),`
166			`.IFGCounterEq24(IFGCounterEq24),`
167			`.ByteCntEq0(ByteCntEq0),`
168			`.ByteCntEq1(ByteCntEq1),`
169			`.ByteCntEq2(ByteCntEq2),`
170			`.ByteCntEq3(ByteCntEq3),`
171			`.ByteCntEq4(ByteCntEq4),`
172			`.ByteCntEq5(ByteCntEq5),`
173			`.ByteCntEq6(ByteCntEq6),`
174			`.ByteCntEq7(ByteCntEq7),`
175			`.ByteCntGreat2(ByteCntGreat2),`
176			`.ByteCntSmall7(ByteCntSmall7),`
177			`.ByteCntMaxFrame(ByteCntMaxFrame),`
178			`.ByteCntOut(ByteCnt)`
179			`);`
180	6	julius
181	439	julius	`// Rx Address Check`
182	6	julius
183	439	julius	`eth_rxaddrcheck rxaddrcheck1`
184			`(.MRxClk(MRxClk),`
185			`.Reset( Reset),`
186			`.RxData(RxData),`
187			`.Broadcast (Broadcast),`
188			`.r_Bro (r_Bro),`
189			`.r_Pro(r_Pro),`
190			`.ByteCntEq6(ByteCntEq6),`
191			`.ByteCntEq7(ByteCntEq7),`
192			`.ByteCntEq2(ByteCntEq2),`
193			`.ByteCntEq3(ByteCntEq3),`
194			`.ByteCntEq4(ByteCntEq4),`
195			`.ByteCntEq5(ByteCntEq5),`
196			`.HASH0(r_HASH0),`
197			`.HASH1(r_HASH1),`
198			`.CrcHash(CrcHash),`
199			`.CrcHashGood(CrcHashGood),`
200			`.StateData(StateData),`
201			`.Multicast(Multicast),`
202			`.MAC(MAC),`
203			`.RxAbort(RxAbort),`
204			`.RxEndFrm(RxEndFrm),`
205			`.AddressMiss(AddressMiss),`
206			`.PassAll(PassAll),`
207			`.ControlFrmAddressOK(ControlFrmAddressOK)`
208			`);`
209	6	julius
210
211	439	julius	`assign Enable_Crc = MRxDV & (\|StateData & ~ByteCntMaxFrame);`
212			`assign Initialize_Crc = StateSFD \| DlyCrcEn & (\|DlyCrcCnt[3:0]) &`
213			`DlyCrcCnt[3:0] < 4'h9;`
214	6	julius
215	439	julius	`assign Data_Crc[0] = MRxD[3];`
216			`assign Data_Crc[1] = MRxD[2];`
217			`assign Data_Crc[2] = MRxD[1];`
218			`assign Data_Crc[3] = MRxD[0];`
219	6	julius
220
221	439	julius	`// Connecting module Crc`
222			`eth_crc crcrx`
223			`(.Clk(MRxClk),`
224			`.Reset(Reset),`
225			`.Data(Data_Crc),`
226			`.Enable(Enable_Crc),`
227			`.Initialize(Initialize_Crc),`
228			`.Crc(Crc), .CrcError(CrcError)`
229			`);`
230	6	julius
231
232
233	439	julius	`// Latching CRC for use in the hash table`
234	6	julius
235	439	julius	`always @ (posedge MRxClk)`
236			`begin`
237			`CrcHashGood <= StateData[0] & ByteCntEq6;`
238			`end`
239	6	julius
240	439	julius	`always @ (posedge MRxClk)`
241			`begin`
242			`if(Reset \| StateIdle)`
243			`CrcHash[5:0] <= 6'h0;`
244			`else`
245			`if(StateData[0] & ByteCntEq6)`
246			`CrcHash[5:0] <= Crc[31:26];`
247			`end`
248	6	julius
249
250	439	julius	`// Output byte stream`
251			`always @ (posedge MRxClk or posedge Reset)`
252			`begin`
253			`if(Reset)`
254			`begin`
255			`RxData_d[7:0] <= 8'h0;`
256			`DelayData <= 1'b0;`
257			`LatchedByte[7:0] <= 8'h0;`
258			`RxData[7:0] <= 8'h0;`
259			`end`
260			`else`
261			`begin`
262			`// Latched byte`
263			`LatchedByte[7:0] <= {MRxD[3:0], LatchedByte[7:4]};`
264
265			`DelayData <= StateData[0];`
266	6	julius
267	439	julius	`if(GenerateRxValid)`
268			`// Data goes through only in data state`
269			`RxData_d[7:0] <= LatchedByte[7:0] & {8{\|StateData}};`
270			`else`
271			`if(~DelayData)`
272			`// Delaying data to be valid for two cycles.`
273			`// Zero when not active.`
274			`RxData_d[7:0] <= 8'h0;`
275	6	julius
276	439	julius	`RxData[7:0] <= RxData_d[7:0]; // Output data byte`
277			`end`
278			`end`
279	6	julius
280	439	julius
281	6	julius
282	439	julius	`always @ (posedge MRxClk or posedge Reset)`
283			`begin`
284			`if(Reset)`
285			`Broadcast <= 1'b0;`
286			`else`
287			`begin`
288			`if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)`
289			`Broadcast <= 1'b0;`
290			`else`
291			`if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)`
292			`Broadcast <= 1'b1;`
293			`else`
294			`if(RxAbort \| RxEndFrm)`
295			`Broadcast <= 1'b0;`
296			`end`
297			`end`
298	6	julius
299
300	439	julius	`always @ (posedge MRxClk or posedge Reset)`
301			`begin`
302			`if(Reset)`
303			`Multicast <= 1'b0;`
304			`else`
305			`begin`
306			`if(StateData[0] & ByteCntEq1 & LatchedByte[0])`
307			`Multicast <= 1'b1;`
308			`else if(RxAbort \| RxEndFrm)`
309			`Multicast <= 1'b0;`
310			`end`
311			`end`
312	6	julius
313
314	439	julius	`assign GenerateRxValid = StateData[0] & (~ByteCntEq0 \| DlyCrcCnt >= 4'h3);`
315	6	julius
316	439	julius	`always @ (posedge MRxClk or posedge Reset)`
317			`begin`
318			`if(Reset)`
319			`begin`
320			`RxValid_d <= 1'b0;`
321			`RxValid <= 1'b0;`
322			`end`
323			`else`
324			`begin`
325			`RxValid_d <= GenerateRxValid;`
326			`RxValid <= RxValid_d;`
327			`end`
328			`end`
329	6	julius
330
331	439	julius	`assign GenerateRxStartFrm = StateData[0] &`
332			`((ByteCntEq1 & ~DlyCrcEn) \|`
333			`((DlyCrcCnt == 4'h3) & DlyCrcEn));`
334	6	julius
335	439	julius	`always @ (posedge MRxClk or posedge Reset)`
336			`begin`
337			`if(Reset)`
338			`begin`
339			`RxStartFrm_d <= 1'b0;`
340			`RxStartFrm <= 1'b0;`
341			`end`
342			`else`
343			`begin`
344			`RxStartFrm_d <= GenerateRxStartFrm;`
345			`RxStartFrm <= RxStartFrm_d;`
346			`end`
347			`end`
348	6	julius
349
350	439	julius	`assign GenerateRxEndFrm = StateData[0] &`
351			`(~MRxDV & ByteCntGreat2 \| ByteCntMaxFrame);`
352			`assign DribbleRxEndFrm = StateData[1] & ~MRxDV & ByteCntGreat2;`
353	6	julius
354
355	439	julius	`always @ (posedge MRxClk or posedge Reset)`
356			`begin`
357			`if(Reset)`
358			`begin`
359			`RxEndFrm_d <= 1'b0;`
360			`RxEndFrm <= 1'b0;`
361			`end`
362			`else`
363			`begin`
364			`RxEndFrm_d <= GenerateRxEndFrm;`
365			`RxEndFrm <= RxEndFrm_d \| DribbleRxEndFrm;`
366			`end`
367			`end`
368	6	julius
369
370			`endmodule`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_rxethmac.v] - Blame information for rev 445