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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_rxethmac.v] - Blame information for rev 570

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1 6 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  eth_rxethmac.v                                              ////
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////                                                              ////
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////  This file is part of the Ethernet IP core project           ////
6 570 olof
////  http://www.opencores.org/project,ethmac                     ////
7 6 julius
////                                                              ////
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////  Author(s):                                                  ////
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////      - Igor Mohor (igorM@opencores.org)                      ////
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////      - Novan Hartadi (novan@vlsi.itb.ac.id)                  ////
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////      - Mahmud Galela (mgalela@vlsi.itb.ac.id)                ////
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////                                                              ////
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////  All additional information is avaliable in the Readme.txt   ////
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////  file.                                                       ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2001 Authors                                   ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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`include "timescale.v"
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46 439 julius
module eth_rxethmac (MRxClk, MRxDV, MRxD, Reset, Transmitting, MaxFL, r_IFG,
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                     HugEn, DlyCrcEn, RxData, RxValid, RxStartFrm, RxEndFrm,
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                     ByteCnt, ByteCntEq0, ByteCntGreat2, ByteCntMaxFrame,
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                     CrcError, StateIdle, StatePreamble, StateSFD, StateData,
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                     MAC, r_Pro, r_Bro,r_HASH0, r_HASH1, RxAbort, AddressMiss,
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                     PassAll, ControlFrmAddressOK
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                     );
53 6 julius
 
54 439 julius
   input         MRxClk;
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   input         MRxDV;
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   input [3:0]    MRxD;
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   input         Transmitting;
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   input         HugEn;
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   input         DlyCrcEn;
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   input [15:0]  MaxFL;
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   input         r_IFG;
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   input         Reset;
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   input [47:0]  MAC;     //  Station Address  
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   input         r_Bro;   //  broadcast disable
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   input         r_Pro;   //  promiscuous enable 
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   input [31:0]  r_HASH0; //  lower 4 bytes Hash Table
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   input [31:0]  r_HASH1; //  upper 4 bytes Hash Table
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   input         PassAll;
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   input         ControlFrmAddressOK;
70 6 julius
 
71 439 julius
   output [7:0]  RxData;
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   output        RxValid;
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   output        RxStartFrm;
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   output        RxEndFrm;
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   output [15:0] ByteCnt;
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   output        ByteCntEq0;
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   output        ByteCntGreat2;
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   output        ByteCntMaxFrame;
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   output        CrcError;
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   output        StateIdle;
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   output        StatePreamble;
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   output        StateSFD;
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   output [1:0]  StateData;
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   output        RxAbort;
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   output        AddressMiss;
86 6 julius
 
87 439 julius
   reg [7:0]      RxData;
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   reg           RxValid;
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   reg           RxStartFrm;
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   reg           RxEndFrm;
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   reg           Broadcast;
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   reg           Multicast;
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   reg [5:0]      CrcHash;
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   reg           CrcHashGood;
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   reg           DelayData;
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   reg [7:0]      LatchedByte;
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   reg [7:0]      RxData_d;
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   reg           RxValid_d;
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   reg           RxStartFrm_d;
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   reg           RxEndFrm_d;
101 6 julius
 
102 439 julius
   wire          MRxDEqD;
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   wire          MRxDEq5;
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   wire          StateDrop;
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   wire          ByteCntEq1;
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   wire          ByteCntEq2;
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   wire          ByteCntEq3;
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   wire          ByteCntEq4;
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   wire          ByteCntEq5;
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   wire          ByteCntEq6;
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   wire          ByteCntEq7;
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   wire          ByteCntSmall7;
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   wire [31:0]    Crc;
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   wire          Enable_Crc;
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   wire          Initialize_Crc;
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   wire [3:0]     Data_Crc;
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   wire          GenerateRxValid;
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   wire          GenerateRxStartFrm;
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   wire          GenerateRxEndFrm;
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   wire          DribbleRxEndFrm;
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   wire [3:0]     DlyCrcCnt;
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   wire          IFGCounterEq24;
123 6 julius
 
124 439 julius
   assign MRxDEqD = MRxD == 4'hd;
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   assign MRxDEq5 = MRxD == 4'h5;
126 6 julius
 
127
 
128 439 julius
   // Rx State Machine module
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   eth_rxstatem rxstatem1
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     (
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      .MRxClk(MRxClk),
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      .Reset(Reset),
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      .MRxDV(MRxDV),
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      .ByteCntEq0(ByteCntEq0),
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      .ByteCntGreat2(ByteCntGreat2),
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      .Transmitting(Transmitting),
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      .MRxDEq5(MRxDEq5),
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      .MRxDEqD(MRxDEqD),
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      .IFGCounterEq24(IFGCounterEq24),
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      .ByteCntMaxFrame(ByteCntMaxFrame),
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      .StateData(StateData),
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      .StateIdle(StateIdle),
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      .StatePreamble(StatePreamble),
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      .StateSFD(StateSFD),
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      .StateDrop(StateDrop)
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      );
147 6 julius
 
148
 
149 439 julius
   // Rx Counters module
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   eth_rxcounters rxcounters1
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     (.MRxClk(MRxClk),
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      .Reset(Reset),
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      .MRxDV(MRxDV),
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      .StateIdle(StateIdle),
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      .StateSFD(StateSFD),
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      .StateData(StateData),
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      .StateDrop(StateDrop),
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      .StatePreamble(StatePreamble),
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      .MRxDEqD(MRxDEqD),
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      .DlyCrcEn(DlyCrcEn),
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      .DlyCrcCnt(DlyCrcCnt),
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      .Transmitting(Transmitting),
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      .MaxFL(MaxFL),
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      .r_IFG(r_IFG),
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      .HugEn(HugEn),
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      .IFGCounterEq24(IFGCounterEq24),
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      .ByteCntEq0(ByteCntEq0),
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      .ByteCntEq1(ByteCntEq1),
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      .ByteCntEq2(ByteCntEq2),
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      .ByteCntEq3(ByteCntEq3),
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      .ByteCntEq4(ByteCntEq4),
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      .ByteCntEq5(ByteCntEq5),
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      .ByteCntEq6(ByteCntEq6),
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      .ByteCntEq7(ByteCntEq7),
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      .ByteCntGreat2(ByteCntGreat2),
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      .ByteCntSmall7(ByteCntSmall7),
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      .ByteCntMaxFrame(ByteCntMaxFrame),
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      .ByteCntOut(ByteCnt)
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      );
180 6 julius
 
181 439 julius
   // Rx Address Check
182 6 julius
 
183 439 julius
   eth_rxaddrcheck rxaddrcheck1
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     (.MRxClk(MRxClk),
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      .Reset( Reset),
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      .RxData(RxData),
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      .Broadcast (Broadcast),
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      .r_Bro (r_Bro),
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      .r_Pro(r_Pro),
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      .ByteCntEq6(ByteCntEq6),
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      .ByteCntEq7(ByteCntEq7),
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      .ByteCntEq2(ByteCntEq2),
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      .ByteCntEq3(ByteCntEq3),
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      .ByteCntEq4(ByteCntEq4),
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      .ByteCntEq5(ByteCntEq5),
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      .HASH0(r_HASH0),
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      .HASH1(r_HASH1),
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      .CrcHash(CrcHash),
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      .CrcHashGood(CrcHashGood),
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      .StateData(StateData),
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      .Multicast(Multicast),
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      .MAC(MAC),
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      .RxAbort(RxAbort),
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      .RxEndFrm(RxEndFrm),
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      .AddressMiss(AddressMiss),
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      .PassAll(PassAll),
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      .ControlFrmAddressOK(ControlFrmAddressOK)
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      );
209 6 julius
 
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211 439 julius
   assign Enable_Crc = MRxDV & (|StateData & ~ByteCntMaxFrame);
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   assign Initialize_Crc = StateSFD | DlyCrcEn & (|DlyCrcCnt[3:0]) &
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                           DlyCrcCnt[3:0] < 4'h9;
214 6 julius
 
215 439 julius
   assign Data_Crc[0] = MRxD[3];
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   assign Data_Crc[1] = MRxD[2];
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   assign Data_Crc[2] = MRxD[1];
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   assign Data_Crc[3] = MRxD[0];
219 6 julius
 
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221 439 julius
   // Connecting module Crc
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   eth_crc crcrx
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     (.Clk(MRxClk),
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      .Reset(Reset),
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      .Data(Data_Crc),
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      .Enable(Enable_Crc),
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      .Initialize(Initialize_Crc),
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      .Crc(Crc), .CrcError(CrcError)
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      );
230 6 julius
 
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233 439 julius
   // Latching CRC for use in the hash table
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235 439 julius
   always @ (posedge MRxClk)
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     begin
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        CrcHashGood <=  StateData[0] & ByteCntEq6;
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     end
239 6 julius
 
240 439 julius
   always @ (posedge MRxClk)
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     begin
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        if(Reset | StateIdle)
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          CrcHash[5:0] <=  6'h0;
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        else
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          if(StateData[0] & ByteCntEq6)
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            CrcHash[5:0] <=  Crc[31:26];
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     end
248 6 julius
 
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250 439 julius
   // Output byte stream
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   always @ (posedge MRxClk or posedge Reset)
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     begin
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        if(Reset)
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          begin
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             RxData_d[7:0]      <=  8'h0;
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             DelayData          <=  1'b0;
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             LatchedByte[7:0]   <=  8'h0;
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             RxData[7:0]        <=  8'h0;
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          end
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        else
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          begin
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             // Latched byte
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             LatchedByte[7:0]   <=  {MRxD[3:0], LatchedByte[7:4]};
264
 
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             DelayData          <=  StateData[0];
266 6 julius
 
267 439 julius
             if(GenerateRxValid)
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               // Data goes through only in data state 
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               RxData_d[7:0] <=  LatchedByte[7:0] & {8{|StateData}};
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             else
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               if(~DelayData)
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                 // Delaying data to be valid for two cycles. 
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                 // Zero when not active.
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                 RxData_d[7:0] <=  8'h0;
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276 439 julius
             RxData[7:0] <=  RxData_d[7:0];          // Output data byte
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          end
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     end
279 6 julius
 
280 439 julius
 
281 6 julius
 
282 439 julius
   always @ (posedge MRxClk or posedge Reset)
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     begin
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        if(Reset)
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          Broadcast <=  1'b0;
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        else
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          begin
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             if(StateData[0] & ~(&LatchedByte[7:0]) & ByteCntSmall7)
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               Broadcast <=  1'b0;
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             else
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               if(StateData[0] & (&LatchedByte[7:0]) & ByteCntEq1)
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                 Broadcast <=  1'b1;
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               else
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                 if(RxAbort | RxEndFrm)
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                   Broadcast <=  1'b0;
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          end
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     end
298 6 julius
 
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300 439 julius
   always @ (posedge MRxClk or posedge Reset)
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     begin
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        if(Reset)
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          Multicast <=  1'b0;
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        else
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          begin
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             if(StateData[0] & ByteCntEq1 & LatchedByte[0])
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               Multicast <=  1'b1;
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             else if(RxAbort | RxEndFrm)
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               Multicast <=  1'b0;
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          end
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     end
312 6 julius
 
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314 439 julius
   assign GenerateRxValid = StateData[0] & (~ByteCntEq0 | DlyCrcCnt >= 4'h3);
315 6 julius
 
316 439 julius
   always @ (posedge MRxClk or posedge Reset)
317
     begin
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        if(Reset)
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          begin
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             RxValid_d <=  1'b0;
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             RxValid   <=  1'b0;
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          end
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        else
324
          begin
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             RxValid_d <=  GenerateRxValid;
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             RxValid   <=  RxValid_d;
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          end
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     end
329 6 julius
 
330
 
331 439 julius
   assign GenerateRxStartFrm = StateData[0] &
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                               ((ByteCntEq1 & ~DlyCrcEn) |
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                                ((DlyCrcCnt == 4'h3) & DlyCrcEn));
334 6 julius
 
335 439 julius
   always @ (posedge MRxClk or posedge Reset)
336
     begin
337
        if(Reset)
338
          begin
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             RxStartFrm_d <=  1'b0;
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             RxStartFrm   <=  1'b0;
341
          end
342
        else
343
          begin
344
             RxStartFrm_d <=  GenerateRxStartFrm;
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             RxStartFrm   <=  RxStartFrm_d;
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          end
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     end
348 6 julius
 
349
 
350 439 julius
   assign GenerateRxEndFrm = StateData[0] &
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                             (~MRxDV & ByteCntGreat2 | ByteCntMaxFrame);
352
   assign DribbleRxEndFrm  = StateData[1] &  ~MRxDV & ByteCntGreat2;
353 6 julius
 
354
 
355 439 julius
   always @ (posedge MRxClk or posedge Reset)
356
     begin
357
        if(Reset)
358
          begin
359
             RxEndFrm_d <=  1'b0;
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             RxEndFrm   <=  1'b0;
361
          end
362
        else
363
          begin
364
             RxEndFrm_d <=  GenerateRxEndFrm;
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             RxEndFrm   <=  RxEndFrm_d | DribbleRxEndFrm;
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          end
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     end
368 6 julius
 
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endmodule

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