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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_spram_256x32.v                                          ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2003/12/05 12:43:06  tadejm
// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.
//
// Revision 1.8  2003/12/04 14:59:13  simons
// Lapsus fixed (!we -> ~we).
//
// Revision 1.7  2003/11/12 18:24:59  tadejm
// WISHBONE slave changed and tested from only 32-bit accesss to byte access.
//
// Revision 1.6  2003/10/17 07:46:15  markom
// mbist signals updated according to newest convention
//
// Revision 1.5  2003/08/14 16:42:58  simons
// Artisan ram instance added.
//
// Revision 1.4  2002/10/18 17:04:20  tadejm
// Changed BIST scan signals.
//
// Revision 1.3  2002/10/10 16:29:30  mohor
// BIST added.
//
// Revision 1.2  2002/09/23 18:24:31  mohor
// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).
//
// Revision 1.1  2002/07/23 16:36:09  mohor
// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.
//
//
//
 
`include "ethmac_defines.v"
`include "timescale.v"
 
module eth_spram_256x32(
                        // Generic synchronous single-port RAM interface
                        clk, rst, ce, we, oe, addr, di, dato
 
`ifdef ETH_BIST
                        ,
                        // debug chain signals
                        mbist_si_i,       // bist scan serial in
                        mbist_so_o,       // bist scan serial out
                        mbist_ctrl_i        // bist chain shift control
`endif
 
 
 
                        );
   parameter we_width = 4;
 
   //
   // Generic synchronous single-port RAM interface
   //
   input           clk;  // Clock, rising edge
   input           rst;  // Reset, active high
   input           ce;   // Chip enable input, active high
   input [we_width-1:0] we;   // Write enable input, active high
   input                oe;   // Output enable input, active high
   input [7:0]           addr; // address bus inputs
   input [31:0]  di;   // input data bus
   output [31:0]         dato;   // output data bus
 
 
`ifdef ETH_BIST
   input           mbist_si_i;       // bist scan serial in
   output          mbist_so_o;       // bist scan serial out
   input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
`endif
 
`ifdef ETH_XILINX_RAMB4
 
   /*RAMB4_S16 ram0
    (
    .DO      (do[15:0]),
    .ADDR    (addr),
    .DI      (di[15:0]),
    .EN      (ce),
    .CLK     (clk),
    .WE      (we),
    .RST     (rst)
    );
 
    RAMB4_S16 ram1
    (
    .DO      (do[31:16]),
    .ADDR    (addr),
    .DI      (di[31:16]),
    .EN      (ce),
    .CLK     (clk),
    .WE      (we),
    .RST     (rst)
    );*/
 
   RAMB4_S8 ram0
     (
      .DO      (dato[7:0]),
      .ADDR    ({1'b0, addr}),
      .DI      (di[7:0]),
      .EN      (ce),
      .CLK     (clk),
      .WE      (we[0]),
      .RST     (rst)
      );
 
   RAMB4_S8 ram1
     (
      .DO      (dato[15:8]),
      .ADDR    ({1'b0, addr}),
      .DI      (di[15:8]),
      .EN      (ce),
      .CLK     (clk),
      .WE      (we[1]),
      .RST     (rst)
      );
 
   RAMB4_S8 ram2
     (
      .DO      (dato[23:16]),
      .ADDR    ({1'b0, addr}),
      .DI      (di[23:16]),
      .EN      (ce),
      .CLK     (clk),
      .WE      (we[2]),
      .RST     (rst)
      );
 
   RAMB4_S8 ram3
     (
      .DO      (dato[31:24]),
      .ADDR    ({1'b0, addr}),
      .DI      (di[31:24]),
      .EN      (ce),
      .CLK     (clk),
      .WE      (we[3]),
      .RST     (rst)
      );
 
`else   // !ETH_XILINX_RAMB4
 `ifdef  ETH_VIRTUAL_SILICON_RAM
  `ifdef ETH_BIST
   //vs_hdsp_256x32_bist ram0_bist
   vs_hdsp_256x32_bw_bist ram0_bist
  `else
     //vs_hdsp_256x32 ram0
     vs_hdsp_256x32_bw ram0
  `endif
       (
        .CK         (clk),
        .CEN        (!ce),
        .WEN        (~we),
        .OEN        (!oe),
        .ADR        (addr),
        .DI         (di),
        .DOUT       (dato)
 
  `ifdef ETH_BIST
        ,
        // debug chain signals
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i       (mbist_ctrl_i)
  `endif
        );
 
 `else   // !ETH_VIRTUAL_SILICON_RAM
 
  `ifdef  ETH_ARTISAN_RAM
   `ifdef ETH_BIST
   //art_hssp_256x32_bist ram0_bist
   art_hssp_256x32_bw_bist ram0_bist
   `else
     //art_hssp_256x32 ram0
     art_hssp_256x32_bw ram0
   `endif
       (
        .CLK        (clk),
        .CEN        (!ce),
        .WEN        (~we),
        .OEN        (!oe),
        .A          (addr),
        .D          (di),
        .Q          (dato)
 
   `ifdef ETH_BIST
        ,
        // debug chain signals
        .mbist_si_i       (mbist_si_i),
        .mbist_so_o       (mbist_so_o),
        .mbist_ctrl_i     (mbist_ctrl_i)
   `endif
        );
 
  `else   // !ETH_ARTISAN_RAM
   `ifdef ETH_ALTERA_ALTSYNCRAM
 
   altera_spram_256x32  altera_spram_256x32_inst
     (
      .address        (addr),
      .wren           (ce & we),
      .clock          (clk),
      .data           (di),
      .q              (dato)
      );  //exemplar attribute altera_spram_256x32_inst NOOPT TRUE
 
   `else   // !ETH_ALTERA_ALTSYNCRAM
 
 
   //
   // Generic single-port synchronous RAM model
   //
 
   //
   // Generic RAM's registers and wires
   //
   reg [ 7: 0]                          mem0 [255:0]; // RAM content
   reg [15: 8]                         mem1 [255:0]; // RAM content
   reg [23:16]                         mem2 [255:0]; // RAM content
   reg [31:24]                         mem3 [255:0]; // RAM content
   wire [31:0]                          q;            // RAM output
   reg [7:0]                            raddr;        // RAM read address
 
   reg [31:0]                           mem[255:0];
 
   //
   // Data output drivers
   //
   //assign do = (oe & ce) ? q : {32{1'bz}};
   assign dato = (oe & ce) ? q : {32{1'bx}};
 
   //
   // RAM read and write
   //
 
   // read operation
   always@(posedge clk)
     if (ce)
       raddr <=  addr; // read address needs to be registered to read clock
 
   generate
      if (we_width > 1)
        begin
 
           assign  q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr],
                                             mem0[raddr]};
 
           // write operation
           always@(posedge clk)
             begin
                if (ce && we[3])
                  mem3[addr] <=  di[31:24];
                if (ce && we[2])
                  mem2[addr] <=  di[23:16];
                if (ce && we[1])
                  mem1[addr] <=  di[15: 8];
                if (ce && we[0])
                  mem0[addr] <=  di[ 7: 0];
             end
 
        end // if (we_width > 1)
      else
        begin
           assign  q = rst ? {32{1'b0}} : {mem[raddr]};
 
           // write operation
           always@(posedge clk)
             begin
                if (ce && we[0])
                  mem[addr] <=  di[ 31: 0];
             end
 
        end // else: !if(we_width > 1)
      endgenerate
 
   // Task prints range of memory
   // *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations. 
   task print_ram;
      input [7:0] start;
      input [7:0] finish;
      integer     rnum;
      begin
         for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1)
           $display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);
      end
   endtask
 
   `endif  // !ETH_ALTERA_ALTSYNCRAM
  `endif  // !ETH_ARTISAN_RAM
 `endif  // !ETH_VIRTUAL_SILICON_RAM
`endif  // !ETH_XILINX_RAMB4
 
endmodule

Line No.	Rev	Author	Line
1	6	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth_spram_256x32.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	570	olof	`//// http://www.opencores.org/project,ethmac ////`
7	6	julius	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is available in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41			`// CVS Revision History`
42			`//`
43	403	julius	`// $Log: not supported by cvs2svn $`
44	6	julius	`// Revision 1.9 2003/12/05 12:43:06 tadejm`
45			`// Corrected address mismatch for xilinx RAMB4_S8 model which has wider address than RAMB4_S16.`
46			`//`
47			`// Revision 1.8 2003/12/04 14:59:13 simons`
48			`// Lapsus fixed (!we -> ~we).`
49			`//`
50			`// Revision 1.7 2003/11/12 18:24:59 tadejm`
51			`// WISHBONE slave changed and tested from only 32-bit accesss to byte access.`
52			`//`
53			`// Revision 1.6 2003/10/17 07:46:15 markom`
54			`// mbist signals updated according to newest convention`
55			`//`
56			`// Revision 1.5 2003/08/14 16:42:58 simons`
57			`// Artisan ram instance added.`
58			`//`
59			`// Revision 1.4 2002/10/18 17:04:20 tadejm`
60			`// Changed BIST scan signals.`
61			`//`
62			`// Revision 1.3 2002/10/10 16:29:30 mohor`
63			`// BIST added.`
64			`//`
65			`// Revision 1.2 2002/09/23 18:24:31 mohor`
66			`// ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).`
67			`//`
68			`// Revision 1.1 2002/07/23 16:36:09 mohor`
69			`// ethernet spram added. So far a generic ram and xilinx RAMB4 are used.`
70			`//`
71			`//`
72			`//`
73
74	409	julius	`include "ethmac_defines.v"
75	6	julius	`include "timescale.v"
76
77			`module eth_spram_256x32(`
78	403	julius	`// Generic synchronous single-port RAM interface`
79	439	julius	`clk, rst, ce, we, oe, addr, di, dato`
80	6	julius
81			`ifdef ETH_BIST
82	403	julius	`,`
83			`// debug chain signals`
84			`mbist_si_i, // bist scan serial in`
85			`mbist_so_o, // bist scan serial out`
86			`mbist_ctrl_i // bist chain shift control`
87	6	julius	`endif
88
89
90
91	403	julius	`);`
92			`parameter we_width = 4;`
93
94			`//`
95			`// Generic synchronous single-port RAM interface`
96			`//`
97			`input clk; // Clock, rising edge`
98			`input rst; // Reset, active high`
99			`input ce; // Chip enable input, active high`
100			`input [we_width-1:0] we; // Write enable input, active high`
101			`input oe; // Output enable input, active high`
102			`input [7:0] addr; // address bus inputs`
103			`input [31:0] di; // input data bus`
104	439	julius	`output [31:0] dato; // output data bus`
105	403	julius
106	6	julius
107			`ifdef ETH_BIST
108	403	julius	`input mbist_si_i; // bist scan serial in`
109			`output mbist_so_o; // bist scan serial out`
110			input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
111	6	julius	`endif
112
113			`ifdef ETH_XILINX_RAMB4
114
115	403	julius	`/*RAMB4_S16 ram0`
116	6	julius	`(`
117	403	julius	`.DO (do[15:0]),`
118			`.ADDR (addr),`
119			`.DI (di[15:0]),`
120			`.EN (ce),`
121			`.CLK (clk),`
122			`.WE (we),`
123			`.RST (rst)`
124	6	julius	`);`
125
126			`RAMB4_S16 ram1`
127			`(`
128	403	julius	`.DO (do[31:16]),`
129			`.ADDR (addr),`
130			`.DI (di[31:16]),`
131			`.EN (ce),`
132			`.CLK (clk),`
133			`.WE (we),`
134			`.RST (rst)`
135	6	julius	`);*/`
136
137	403	julius	`RAMB4_S8 ram0`
138			`(`
139	439	julius	`.DO (dato[7:0]),`
140	403	julius	`.ADDR ({1'b0, addr}),`
141			`.DI (di[7:0]),`
142			`.EN (ce),`
143			`.CLK (clk),`
144			`.WE (we[0]),`
145			`.RST (rst)`
146			`);`
147	6	julius
148	403	julius	`RAMB4_S8 ram1`
149			`(`
150	439	julius	`.DO (dato[15:8]),`
151	403	julius	`.ADDR ({1'b0, addr}),`
152			`.DI (di[15:8]),`
153			`.EN (ce),`
154			`.CLK (clk),`
155			`.WE (we[1]),`
156			`.RST (rst)`
157			`);`
158	6	julius
159	403	julius	`RAMB4_S8 ram2`
160			`(`
161	439	julius	`.DO (dato[23:16]),`
162	403	julius	`.ADDR ({1'b0, addr}),`
163			`.DI (di[23:16]),`
164			`.EN (ce),`
165			`.CLK (clk),`
166			`.WE (we[2]),`
167			`.RST (rst)`
168			`);`
169	6	julius
170	403	julius	`RAMB4_S8 ram3`
171			`(`
172	439	julius	`.DO (dato[31:24]),`
173	403	julius	`.ADDR ({1'b0, addr}),`
174			`.DI (di[31:24]),`
175			`.EN (ce),`
176			`.CLK (clk),`
177			`.WE (we[3]),`
178			`.RST (rst)`
179			`);`
180	6	julius
181			`else // !ETH_XILINX_RAMB4
182	403	julius	`ifdef ETH_VIRTUAL_SILICON_RAM
183	6	julius	`ifdef ETH_BIST
184	403	julius	`//vs_hdsp_256x32_bist ram0_bist`
185			`vs_hdsp_256x32_bw_bist ram0_bist`
186	6	julius	`else
187	403	julius	`//vs_hdsp_256x32 ram0`
188			`vs_hdsp_256x32_bw ram0`
189	6	julius	`endif
190	403	julius	`(`
191	6	julius	`.CK (clk),`
192			`.CEN (!ce),`
193			`.WEN (~we),`
194			`.OEN (!oe),`
195			`.ADR (addr),`
196			`.DI (di),`
197	439	julius	`.DOUT (dato)`
198	6	julius
199	403	julius	`ifdef ETH_BIST
200	6	julius	`,`
201			`// debug chain signals`
202			`.mbist_si_i (mbist_si_i),`
203			`.mbist_so_o (mbist_so_o),`
204			`.mbist_ctrl_i (mbist_ctrl_i)`
205	403	julius	`endif
206			`);`
207	6	julius
208	403	julius	`else // !ETH_VIRTUAL_SILICON_RAM
209	6	julius
210	403	julius	`ifdef ETH_ARTISAN_RAM
211			`ifdef ETH_BIST
212			`//art_hssp_256x32_bist ram0_bist`
213			`art_hssp_256x32_bw_bist ram0_bist`
214			`else
215			`//art_hssp_256x32 ram0`
216			`art_hssp_256x32_bw ram0`
217			`endif
218			`(`
219	6	julius	`.CLK (clk),`
220			`.CEN (!ce),`
221			`.WEN (~we),`
222			`.OEN (!oe),`
223			`.A (addr),`
224			`.D (di),`
225	439	julius	`.Q (dato)`
226	6	julius
227	403	julius	`ifdef ETH_BIST
228	6	julius	`,`
229			`// debug chain signals`
230			`.mbist_si_i (mbist_si_i),`
231			`.mbist_so_o (mbist_so_o),`
232			`.mbist_ctrl_i (mbist_ctrl_i)`
233	403	julius	`endif
234			`);`
235	6	julius
236	403	julius	`else // !ETH_ARTISAN_RAM
237			`ifdef ETH_ALTERA_ALTSYNCRAM
238	6	julius
239	403	julius	`altera_spram_256x32 altera_spram_256x32_inst`
240			`(`
241			`.address (addr),`
242			`.wren (ce & we),`
243			`.clock (clk),`
244			`.data (di),`
245	439	julius	`.q (dato)`
246	403	julius	`); //exemplar attribute altera_spram_256x32_inst NOOPT TRUE`
247	6	julius
248	403	julius	`else // !ETH_ALTERA_ALTSYNCRAM
249	6	julius
250	403	julius
251			`//`
252			`// Generic single-port synchronous RAM model`
253			`//`
254	6	julius
255	403	julius	`//`
256			`// Generic RAM's registers and wires`
257			`//`
258			`reg [ 7: 0] mem0 [255:0]; // RAM content`
259			`reg [15: 8] mem1 [255:0]; // RAM content`
260			`reg [23:16] mem2 [255:0]; // RAM content`
261			`reg [31:24] mem3 [255:0]; // RAM content`
262			`wire [31:0] q; // RAM output`
263			`reg [7:0] raddr; // RAM read address`
264	6	julius
265	403	julius	`reg [31:0] mem[255:0];`
266	6	julius
267	403	julius	`//`
268			`// Data output drivers`
269			`//`
270			`//assign do = (oe & ce) ? q : {32{1'bz}};`
271	439	julius	`assign dato = (oe & ce) ? q : {32{1'bx}};`
272	6	julius
273	403	julius	`//`
274			`// RAM read and write`
275			`//`
276	6	julius
277	403	julius	`// read operation`
278			`always@(posedge clk)`
279			`if (ce)`
280			`raddr <= addr; // read address needs to be registered to read clock`
281	6	julius
282	403	julius	`generate`
283			`if (we_width > 1)`
284			`begin`
285
286			`assign q = rst ? {32{1'b0}} : {mem3[raddr], mem2[raddr], mem1[raddr],`
287			`mem0[raddr]};`
288
289			`// write operation`
290			`always@(posedge clk)`
291			`begin`
292	6	julius	`if (ce && we[3])`
293	403	julius	`mem3[addr] <= di[31:24];`
294	6	julius	`if (ce && we[2])`
295	403	julius	`mem2[addr] <= di[23:16];`
296	6	julius	`if (ce && we[1])`
297	403	julius	`mem1[addr] <= di[15: 8];`
298	6	julius	`if (ce && we[0])`
299	403	julius	`mem0[addr] <= di[ 7: 0];`
300			`end`
301	6	julius
302	403	julius	`end // if (we_width > 1)`
303			`else`
304			`begin`
305			`assign q = rst ? {32{1'b0}} : {mem[raddr]};`
306	6	julius
307	403	julius	`// write operation`
308			`always@(posedge clk)`
309			`begin`
310			`if (ce && we[0])`
311			`mem[addr] <= di[ 31: 0];`
312			`end`
313
314			`end // else: !if(we_width > 1)`
315			`endgenerate`
316	6	julius
317			`// Task prints range of memory`
318			`// *** Remember that tasks are non reentrant, don't call this task in parallel for multiple instantiations.`
319			`task print_ram;`
320			`input [7:0] start;`
321			`input [7:0] finish;`
322			`integer rnum;`
323			`begin`
324	439	julius	`for (rnum={24'd0,start};rnum<={24'd0,finish};rnum=rnum+1)`
325	403	julius	`$display("Addr %h = %0h %0h %0h %0h",rnum,mem3[rnum],mem2[rnum],mem1[rnum],mem0[rnum]);`
326	6	julius	`end`
327			`endtask`
328	403	julius
329			`endif // !ETH_ALTERA_ALTSYNCRAM
330			`endif // !ETH_ARTISAN_RAM
331			`endif // !ETH_VIRTUAL_SILICON_RAM
332	6	julius	`endif // !ETH_XILINX_RAMB4
333
334			`endmodule`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [eth_spram_256x32.v] - Blame information for rev 805