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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [ethmac/] [ethmac.v] - Blame information for rev 439

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth.v                                                       ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/project,ethmac                     ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor (igorM@opencores.org)                      ////
////                                                              ////
////  All additional information is available in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001, 2002 Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
 
 
`include "ethmac_defines.v"
`include "timescale.v"
 
 
module ethmac // renamed jb
  (
   // WISHBONE common
   wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,
 
   // WISHBONE slave
   wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,
 
   // WISHBONE master
   m_wb_adr_o, m_wb_sel_o, m_wb_we_o,
   m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,
   m_wb_stb_o, m_wb_ack_i, m_wb_err_i,
 
`ifdef ETH_WISHBONE_B3
   m_wb_cti_o, m_wb_bte_o,
`endif
 
   //TX
   mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,
 
   //RX
   mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i,
   mcrs_pad_i,
 
   // MIIM
   mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,
 
   int_o
 
   // Bist
`ifdef ETH_BIST
   ,
   // debug chain signals
   mbist_si_i,       // bist scan serial in
   mbist_so_o,       // bist scan serial out
   mbist_ctrl_i        // bist chain shift control
`endif
 
   );
 
 
 
   // WISHBONE common
   input           wb_clk_i;     // WISHBONE clock
   input           wb_rst_i;     // WISHBONE reset
   input [31:0]    wb_dat_i;     // WISHBONE data input
   output [31:0]   wb_dat_o;     // WISHBONE data output
   output          wb_err_o;     // WISHBONE error output
 
   // WISHBONE slave
   input [11:2]    wb_adr_i;     // WISHBONE address input
   input [3:0]      wb_sel_i;     // WISHBONE byte select input
   input           wb_we_i;      // WISHBONE write enable input
   input           wb_cyc_i;     // WISHBONE cycle input
   input           wb_stb_i;     // WISHBONE strobe input
   output          wb_ack_o;     // WISHBONE acknowledge output
 
   // WISHBONE master
   output [31:0]   m_wb_adr_o;
   output [3:0]    m_wb_sel_o;
   output          m_wb_we_o;
   input [31:0]    m_wb_dat_i;
   output [31:0]   m_wb_dat_o;
   output          m_wb_cyc_o;
   output          m_wb_stb_o;
   input           m_wb_ack_i;
   input           m_wb_err_i;
 
   wire [29:0]      m_wb_adr_tmp;
 
`ifdef ETH_WISHBONE_B3
   output [2:0]    m_wb_cti_o;   // Cycle Type Identifier
   output [1:0]    m_wb_bte_o;   // Burst Type Extension
`endif
 
   // Tx
   input           mtx_clk_pad_i; // Transmit clock (from PHY)
   output [3:0]    mtxd_pad_o;    // Transmit nibble (to PHY)
   output          mtxen_pad_o;   // Transmit enable (to PHY)
   output          mtxerr_pad_o;  // Transmit error (to PHY)
 
   // Rx
   input           mrx_clk_pad_i; // Receive clock (from PHY)
   input [3:0]      mrxd_pad_i;    // Receive nibble (from PHY)
   input           mrxdv_pad_i;   // Receive data valid (from PHY)
   input           mrxerr_pad_i;  // Receive data error (from PHY)
 
   // Common Tx and Rx
   input           mcoll_pad_i;   // Collision (from PHY)
   input           mcrs_pad_i;    // Carrier sense (from PHY)
 
   // MII Management interface
   input           md_pad_i;      // MII data input (from I/O cell)
   output          mdc_pad_o;     // MII Management data clock (to PHY)
   output          md_pad_o;      // MII data output (to I/O cell)
   output          md_padoe_o;    // MII data output enable (to I/O cell)
 
   output          int_o;         // Interrupt output
 
   // Bist
`ifdef ETH_BIST
   input           mbist_si_i;       // bist scan serial in
   output          mbist_so_o;       // bist scan serial out
   input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
`endif
 
`ifdef WISHBONE_DEBUG
   wire [31:0]                          wb_dbg_dat0;
`endif
 
 
   wire [7:0]                           r_ClkDiv;
   wire                                r_MiiNoPre;
   wire [15:0]                          r_CtrlData;
   wire [4:0]                           r_FIAD;
   wire [4:0]                           r_RGAD;
   wire                                r_WCtrlData;
   wire                                r_RStat;
   wire                                r_ScanStat;
   wire                                NValid_stat;
   wire                                Busy_stat;
   wire                                LinkFail;
   wire [15:0]                          Prsd; // Read Status Data (data read 
                                             // from the PHY)
   wire                                WCtrlDataStart;
   wire                                RStatStart;
   wire                                UpdateMIIRX_DATAReg;
 
   wire                                TxStartFrm;
   wire                                TxEndFrm;
   wire                                TxUsedData;
   wire [7:0]                           TxData;
   wire                                TxRetry;
   wire                                TxAbort;
   wire                                TxUnderRun;
   wire                                TxDone;
 
 
   reg                                 WillSendControlFrame_sync1;
   reg                                 WillSendControlFrame_sync2;
   reg                                 WillSendControlFrame_sync3;
   reg                                 RstTxPauseRq;
 
   reg                                 TxPauseRq_sync1;
   reg                                 TxPauseRq_sync2;
   reg                                 TxPauseRq_sync3;
   reg                                 TPauseRq;
 
 
   // Connecting Miim module
   eth_miim miim1
     (
      .Clk(wb_clk_i),
      .Reset(wb_rst_i),
      .Divider(r_ClkDiv),
      .NoPre(r_MiiNoPre),
      .CtrlData(r_CtrlData),
      .Rgad(r_RGAD),
      .Fiad(r_FIAD),
      .WCtrlData(r_WCtrlData),
      .RStat(r_RStat),
      .ScanStat(r_ScanStat),
      .Mdi(md_pad_i),
      .Mdo(md_pad_o),
      .MdoEn(md_padoe_o),
      .Mdc(mdc_pad_o),
      .Busy(Busy_stat),
      .Prsd(Prsd),
      .LinkFail(LinkFail),
      .Nvalid(NValid_stat),
      .WCtrlDataStart(WCtrlDataStart),
      .RStatStart(RStatStart),
      .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)
      );
 
 
 
 
   wire [3:0]                           RegCs;          // Connected to registers
   wire [31:0]                          RegDataOut;     // Multiplexed to wb_dat_o
   wire                                r_RecSmall;     // Receive small frames
   wire                                r_LoopBck;      // Loopback
   wire                                r_TxEn;         // Tx Enable
   wire                                r_RxEn;         // Rx Enable
 
   wire                                MRxDV_Lb;       // Muxed MII receive data valid
   wire                                MRxErr_Lb;      // Muxed MII Receive Error
   wire [3:0]                           MRxD_Lb;        // Muxed MII Receive Data
   wire                                Transmitting;   // Indication that TxEthMAC is transmitting
   wire                                r_HugEn;        // Huge packet enable
   wire                                r_DlyCrcEn;     // Delayed CRC enabled
   wire [15:0]                          r_MaxFL;        // Maximum frame length
 
   wire [15:0]                          r_MinFL;        // Minimum frame length
   wire                                ShortFrame;
   wire                                DribbleNibble;  // Extra nibble received
   wire                                ReceivedPacketTooBig; // Received packet is too big
   wire [47:0]                          r_MAC;          // MAC address
   wire                                LoadRxStatus;   // Rx status was loaded
   wire [31:0]                          r_HASH0;        // HASH table, lower 4 bytes
   wire [31:0]                          r_HASH1;        // HASH table, upper 4 bytes
   wire [7:0]                           r_TxBDNum;      // Receive buffer descriptor number
   wire [6:0]                           r_IPGT;         // 
   wire [6:0]                           r_IPGR1;        // 
   wire [6:0]                           r_IPGR2;        // 
   wire [5:0]                           r_CollValid;    // 
   wire [15:0]                          r_TxPauseTV;    // Transmit PAUSE value
   wire                                r_TxPauseRq;    // Transmit PAUSE request
 
   wire [3:0]                           r_MaxRet;       //
   wire                                r_NoBckof;      // 
   wire                                r_ExDfrEn;      // 
   wire                                r_TxFlow;       // Tx flow control enable
   wire                                r_IFG;          // Minimum interframe gap for incoming packets
 
   wire                                TxB_IRQ;        // Interrupt Tx Buffer
   wire                                TxE_IRQ;        // Interrupt Tx Error
   wire                                RxB_IRQ;        // Interrupt Rx Buffer
   wire                                RxE_IRQ;        // Interrupt Rx Error
   wire                                Busy_IRQ;       // Interrupt Busy (lack of buffers)
 
   //wire        DWord;
   wire                                ByteSelected;
   wire                                BDAck;
   wire [31:0]                          BD_WB_DAT_O;    // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)
   wire [3:0]                           BDCs;           // Buffer descriptor CS
   wire                                CsMiss;         // When access to the address between 0x800 and 0xfff occurs, acknowledge is set
   // but data is not valid.
   wire                                r_Pad;
   wire                                r_CrcEn;
   wire                                r_FullD;
   wire                                r_Pro;
   wire                                r_Bro;
   wire                                r_NoPre;
   wire                                r_RxFlow;
   wire                                r_PassAll;
   wire                                TxCtrlEndFrm;
   wire                                StartTxDone;
   wire                                SetPauseTimer;
   wire                                TxUsedDataIn;
   wire                                TxDoneIn;
   wire                                TxAbortIn;
   wire                                PerPacketPad;
   wire                                PadOut;
   wire                                PerPacketCrcEn;
   wire                                CrcEnOut;
   wire                                TxStartFrmOut;
   wire                                TxEndFrmOut;
   wire                                ReceivedPauseFrm;
   wire                                ControlFrmAddressOK;
   wire                                RxStatusWriteLatched_sync2;
   wire                                LateCollision;
   wire                                DeferIndication;
   wire                                LateCollLatched;
   wire                                DeferLatched;
   wire                                RstDeferLatched;
   wire                                CarrierSenseLost;
 
   wire                                temp_wb_ack_o;
   wire [31:0]                          temp_wb_dat_o;
   wire                                temp_wb_err_o;
 
`ifdef ETH_REGISTERED_OUTPUTS
   reg                                 temp_wb_ack_o_reg;
   reg [31:0]                           temp_wb_dat_o_reg;
   reg                                 temp_wb_err_o_reg;
`endif
 
   //assign DWord = &wb_sel_i;
   assign ByteSelected = |wb_sel_i;
   assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3];   // 0x0   - 0x3FF
   assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2];   // 0x0   - 0x3FF
   assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1];   // 0x0   - 0x3FF
   assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0];   // 0x0   - 0x3FF
   assign BDCs[3]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[3];   // 0x400 - 0x7FF
   assign BDCs[2]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[2];   // 0x400 - 0x7FF
   assign BDCs[1]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[1];   // 0x400 - 0x7FF
   assign BDCs[0]  = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] &  wb_adr_i[10] & wb_sel_i[0];   // 0x400 - 0x7FF
   assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11];                   // 0x800 - 0xfFF
   assign temp_wb_dat_o = ((|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;
   assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected | CsMiss);
 
`ifdef ETH_REGISTERED_OUTPUTS
   assign wb_ack_o = temp_wb_ack_o_reg;
   assign wb_dat_o[31:0] = temp_wb_dat_o_reg;
   assign wb_err_o = temp_wb_err_o_reg;
`else
   assign wb_ack_o = temp_wb_ack_o;
   assign wb_dat_o[31:0] = temp_wb_dat_o;
   assign wb_err_o = temp_wb_err_o;
`endif
 
`ifdef ETH_AVALON_BUS
   // As Avalon has no corresponding "error" signal, I (erroneously) will
   // send an ack to Avalon, even when accessing undefined memory. This
   // is a grey area in Avalon vs. Wishbone specs: My understanding
   // is that Avalon expects all memory addressable by the addr bus feeding
   // a slave to be, at the very minimum, readable.
   assign temp_wb_ack_o = (|RegCs) | BDAck | CsMiss;
`else // WISHBONE
   assign temp_wb_ack_o = (|RegCs) | BDAck;
`endif
 
`ifdef ETH_REGISTERED_OUTPUTS
   always @ (posedge wb_clk_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          begin
             temp_wb_ack_o_reg <= 1'b0;
             temp_wb_dat_o_reg <= 32'h0;
             temp_wb_err_o_reg <= 1'b0;
          end
        else
          begin
             temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;
             temp_wb_dat_o_reg <= temp_wb_dat_o;
             temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;
          end
     end
`endif
 
 
   // Connecting Ethernet registers
   eth_registers ethreg1
     (
      .DataIn(wb_dat_i),
      .Address(wb_adr_i[9:2]),
      .Rw(wb_we_i),
 
      .Cs(RegCs),
      .Clk(wb_clk_i),
      .Reset(wb_rst_i),
 
      .DataOut(RegDataOut),
      .r_RecSmall(r_RecSmall),
 
      .r_Pad(r_Pad),
      .r_HugEn(r_HugEn),
      .r_CrcEn(r_CrcEn),
 
      .r_DlyCrcEn(r_DlyCrcEn),
      .r_FullD(r_FullD),
 
      .r_ExDfrEn(r_ExDfrEn),
      .r_NoBckof(r_NoBckof),
      .r_LoopBck(r_LoopBck),
 
      .r_IFG(r_IFG),
      .r_Pro(r_Pro),
      .r_Iam(),
 
      .r_Bro(r_Bro),
      .r_NoPre(r_NoPre),
      .r_TxEn(r_TxEn),
 
      .r_RxEn(r_RxEn),
      .Busy_IRQ(Busy_IRQ),
      .RxE_IRQ(RxE_IRQ),
 
      .RxB_IRQ(RxB_IRQ),
      .TxE_IRQ(TxE_IRQ),
      .TxB_IRQ(TxB_IRQ),
 
      .r_IPGT(r_IPGT),
 
      .r_IPGR1(r_IPGR1),
      .r_IPGR2(r_IPGR2),
      .r_MinFL(r_MinFL),
 
      .r_MaxFL(r_MaxFL),
      .r_MaxRet(r_MaxRet),
      .r_CollValid(r_CollValid),
 
      .r_TxFlow(r_TxFlow),
      .r_RxFlow(r_RxFlow),
      .r_PassAll(r_PassAll),
 
      .r_MiiNoPre(r_MiiNoPre),
      .r_ClkDiv(r_ClkDiv),
 
      .r_WCtrlData(r_WCtrlData),
      .r_RStat(r_RStat),
      .r_ScanStat(r_ScanStat),
 
      .r_RGAD(r_RGAD),
      .r_FIAD(r_FIAD),
      .r_CtrlData(r_CtrlData),
 
      .NValid_stat(NValid_stat),
      .Busy_stat(Busy_stat),
 
      .LinkFail(LinkFail),
      .r_MAC(r_MAC),
      .WCtrlDataStart(WCtrlDataStart),
 
      .RStatStart(RStatStart),
      .UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),
      .Prsd(Prsd),
 
      .r_TxBDNum(r_TxBDNum),
      .int_o(int_o),
 
      .r_HASH0(r_HASH0),
      .r_HASH1(r_HASH1),
      .r_TxPauseRq(r_TxPauseRq),
 
      .r_TxPauseTV(r_TxPauseTV),
      .RstTxPauseRq(RstTxPauseRq),
      .TxCtrlEndFrm(TxCtrlEndFrm),
 
      .StartTxDone(StartTxDone),
      .TxClk(mtx_clk_pad_i),
      .RxClk(mrx_clk_pad_i),
 
      .dbg_dat(wb_dbg_dat0),
 
      .SetPauseTimer(SetPauseTimer)
 
      );
 
 
 
   wire  [7:0] RxData;
   wire        RxValid;
   wire        RxStartFrm;
   wire        RxEndFrm;
   wire        RxAbort;
 
   wire        WillTransmit;            // Will transmit (to RxEthMAC)
   wire        ResetCollision;          // Reset Collision (for synchronizing 
                                        // collision)
   wire [7:0]  TxDataOut;               // Transmit Packet Data (to TxEthMAC)
   wire        WillSendControlFrame;
   wire        ReceiveEnd;
   wire        ReceivedPacketGood;
   wire        ReceivedLengthOK;
   wire        InvalidSymbol;
   wire        LatchedCrcError;
   wire        RxLateCollision;
   wire [3:0]  RetryCntLatched;
   wire [3:0]  RetryCnt;
   wire        StartTxAbort;
   wire        MaxCollisionOccured;
   wire        RetryLimit;
   wire        StatePreamble;
   wire [1:0]  StateData;
 
   // Connecting MACControl
   eth_maccontrol maccontrol1
     (
      .MTxClk(mtx_clk_pad_i),
      .TPauseRq(TPauseRq),
 
      .TxPauseTV(r_TxPauseTV),
      .TxDataIn(TxData),
 
      .TxStartFrmIn(TxStartFrm),
      .TxEndFrmIn(TxEndFrm),
 
      .TxUsedDataIn(TxUsedDataIn),
      .TxDoneIn(TxDoneIn),
 
      .TxAbortIn(TxAbortIn),
      .MRxClk(mrx_clk_pad_i),
 
      .RxData(RxData),
      .RxValid(RxValid),
 
      .RxStartFrm(RxStartFrm),
      .RxEndFrm(RxEndFrm),
 
      .ReceiveEnd(ReceiveEnd),
      .ReceivedPacketGood(ReceivedPacketGood),
 
      .TxFlow(r_TxFlow),
 
      .RxFlow(r_RxFlow),
      .DlyCrcEn(r_DlyCrcEn),
 
      .MAC(r_MAC),
      .PadIn(r_Pad | PerPacketPad),
 
      .PadOut(PadOut),
      .CrcEnIn(r_CrcEn | PerPacketCrcEn),
 
      .CrcEnOut(CrcEnOut),
      .TxReset(wb_rst_i),
 
      .RxReset(wb_rst_i),
      .ReceivedLengthOK(ReceivedLengthOK),
 
      .TxDataOut(TxDataOut),
      .TxStartFrmOut(TxStartFrmOut),
 
      .TxEndFrmOut(TxEndFrmOut),
      .TxUsedDataOut(TxUsedData),
 
      .TxDoneOut(TxDone),
      .TxAbortOut(TxAbort),
 
      .WillSendControlFrame(WillSendControlFrame),
      .TxCtrlEndFrm(TxCtrlEndFrm),
 
      .ReceivedPauseFrm(ReceivedPauseFrm),
      .ControlFrmAddressOK(ControlFrmAddressOK),
 
      .SetPauseTimer(SetPauseTimer),
 
      .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
      .r_PassAll(r_PassAll)
      );
 
 
 
   wire        TxCarrierSense;          // Synchronized CarrierSense (to Tx 
                                        // clock)
   wire        Collision;               // Synchronized Collision
 
   reg         CarrierSense_Tx1;
   reg         CarrierSense_Tx2;
   reg         Collision_Tx1;
   reg         Collision_Tx2;
 
   reg         RxEnSync;                 // Synchronized Receive Enable
   reg         WillTransmit_q;
   reg         WillTransmit_q2;
 
 
 
   // Muxed MII receive data valid
   assign MRxDV_Lb = r_LoopBck? mtxen_pad_o : mrxdv_pad_i & RxEnSync;
 
   // Muxed MII Receive Error
   assign MRxErr_Lb = r_LoopBck? mtxerr_pad_o : mrxerr_pad_i & RxEnSync;
 
   // Muxed MII Receive Data
   assign MRxD_Lb[3:0] = r_LoopBck? mtxd_pad_o[3:0] : mrxd_pad_i[3:0];
 
 
 
   // Connecting TxEthMAC
   eth_txethmac txethmac1
     (
 
      .MTxClk(mtx_clk_pad_i),
      .Reset(wb_rst_i),
      .CarrierSense(TxCarrierSense),
 
      .Collision(Collision),
      .TxData(TxDataOut),
      .TxStartFrm(TxStartFrmOut),
 
      .TxUnderRun(TxUnderRun),
      .TxEndFrm(TxEndFrmOut),
      .Pad(PadOut),
 
      .MinFL(r_MinFL),
      .CrcEn(CrcEnOut),
      .FullD(r_FullD),
 
      .HugEn(r_HugEn),
      .DlyCrcEn(r_DlyCrcEn),
      .IPGT(r_IPGT),
 
      .IPGR1(r_IPGR1),
      .IPGR2(r_IPGR2),
      .CollValid(r_CollValid),
 
      .MaxRet(r_MaxRet),
      .NoBckof(r_NoBckof),
      .ExDfrEn(r_ExDfrEn),
 
      .MaxFL(r_MaxFL),
      .MTxEn(mtxen_pad_o),
      .MTxD(mtxd_pad_o),
 
      .MTxErr(mtxerr_pad_o),
      .TxUsedData(TxUsedDataIn),
      .TxDone(TxDoneIn),
 
      .TxRetry(TxRetry),
      .TxAbort(TxAbortIn),
      .WillTransmit(WillTransmit),
 
      .ResetCollision(ResetCollision),
      .RetryCnt(RetryCnt),
      .StartTxDone(StartTxDone),
 
      .StartTxAbort(StartTxAbort),
      .MaxCollisionOccured(MaxCollisionOccured),
      .LateCollision(LateCollision),
 
      .DeferIndication(DeferIndication),
      .StatePreamble(StatePreamble),
      .StateData(StateData)
      );
 
 
 
 
   wire [15:0] RxByteCnt;
   wire        RxByteCntEq0;
   wire        RxByteCntGreat2;
   wire        RxByteCntMaxFrame;
   wire        RxCrcError;
   wire        RxStateIdle;
   wire        RxStatePreamble;
   wire        RxStateSFD;
   wire [1:0]  RxStateData;
   wire        AddressMiss;
 
 
 
   // Connecting RxEthMAC
   eth_rxethmac rxethmac1
     (
 
      .MRxClk(mrx_clk_pad_i),
      .MRxDV(MRxDV_Lb),
      .MRxD(MRxD_Lb),
 
      .Transmitting(Transmitting),
      .HugEn(r_HugEn),
      .DlyCrcEn(r_DlyCrcEn),
 
      .MaxFL(r_MaxFL),
      .r_IFG(r_IFG),
      .Reset(wb_rst_i),
 
      .RxData(RxData),
      .RxValid(RxValid),
      .RxStartFrm(RxStartFrm),
 
      .RxEndFrm(RxEndFrm),
      .ByteCnt(RxByteCnt),
 
      .ByteCntEq0(RxByteCntEq0),
      .ByteCntGreat2(RxByteCntGreat2),
      .ByteCntMaxFrame(RxByteCntMaxFrame),
 
      .CrcError(RxCrcError),
      .StateIdle(RxStateIdle),
      .StatePreamble(RxStatePreamble),
 
      .StateSFD(RxStateSFD),
      .StateData(RxStateData),
 
      .MAC(r_MAC),
      .r_Pro(r_Pro),
      .r_Bro(r_Bro),
 
      .r_HASH0(r_HASH0),
      .r_HASH1(r_HASH1),
      .RxAbort(RxAbort),
 
      .AddressMiss(AddressMiss),
      .PassAll(r_PassAll),
      .ControlFrmAddressOK(ControlFrmAddressOK)
      );
 
 
   // MII Carrier Sense Synchronization
   always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          begin
             CarrierSense_Tx1 <=  1'b0;
             CarrierSense_Tx2 <=  1'b0;
          end
        else
          begin
             CarrierSense_Tx1 <=  mcrs_pad_i;
             CarrierSense_Tx2 <=  CarrierSense_Tx1;
          end
     end
 
   assign TxCarrierSense = ~r_FullD & CarrierSense_Tx2;
 
 
   // MII Collision Synchronization
   always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          begin
             Collision_Tx1 <=  1'b0;
             Collision_Tx2 <=  1'b0;
          end
        else
          begin
             Collision_Tx1 <=  mcoll_pad_i;
             if(ResetCollision)
               Collision_Tx2 <=  1'b0;
             else
               if(Collision_Tx1)
                 Collision_Tx2 <=  1'b1;
          end
     end
 
 
   // Synchronized Collision
   assign Collision = ~r_FullD & Collision_Tx2;
 
 
 
   // Delayed WillTransmit
   always @ (posedge mrx_clk_pad_i)
     begin
        WillTransmit_q <=  WillTransmit;
        WillTransmit_q2 <=  WillTransmit_q;
     end
 
 
   assign Transmitting = ~r_FullD & WillTransmit_q2;
 
 
 
   // Synchronized Receive Enable
   always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          RxEnSync <=  1'b0;
        else
          if(~mrxdv_pad_i)
            RxEnSync <=  r_RxEn;
     end
 
 
 
   // Synchronizing WillSendControlFrame to WB_CLK;
   always @ (posedge wb_clk_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          WillSendControlFrame_sync1 <= 1'b0;
        else
          WillSendControlFrame_sync1 <= WillSendControlFrame;
     end
 
   always @ (posedge wb_clk_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          WillSendControlFrame_sync2 <= 1'b0;
        else
          WillSendControlFrame_sync2 <= WillSendControlFrame_sync1;
     end
 
   always @ (posedge wb_clk_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          WillSendControlFrame_sync3 <= 1'b0;
        else
          WillSendControlFrame_sync3 <= WillSendControlFrame_sync2;
     end
 
   always @ (posedge wb_clk_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          RstTxPauseRq <= 1'b0;
        else
          RstTxPauseRq <= WillSendControlFrame_sync2 &
                          ~WillSendControlFrame_sync3;
     end
 
 
 
 
   // TX Pause request Synchronization
   always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          begin
             TxPauseRq_sync1 <=  1'b0;
             TxPauseRq_sync2 <=  1'b0;
             TxPauseRq_sync3 <=  1'b0;
          end
        else
          begin
             TxPauseRq_sync1 <=  (r_TxPauseRq & r_TxFlow);
             TxPauseRq_sync2 <=  TxPauseRq_sync1;
             TxPauseRq_sync3 <=  TxPauseRq_sync2;
          end
     end
 
 
   always @ (posedge mtx_clk_pad_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          TPauseRq <=  1'b0;
        else
          TPauseRq <=  TxPauseRq_sync2 & (~TxPauseRq_sync3);
     end
 
 
   wire LatchedMRxErr;
   reg  RxAbort_latch;
   reg  RxAbort_sync1;
   reg  RxAbort_wb;
   reg  RxAbortRst_sync1;
   reg  RxAbortRst;
 
   // Synchronizing RxAbort to the WISHBONE clock
   always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          RxAbort_latch <=  1'b0;
        else if(RxAbort | (ShortFrame & ~r_RecSmall) | LatchedMRxErr &
                ~InvalidSymbol | (ReceivedPauseFrm & (~r_PassAll)))
          RxAbort_latch <=  1'b1;
        else if(RxAbortRst)
          RxAbort_latch <=  1'b0;
     end
 
   always @ (posedge wb_clk_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          begin
             RxAbort_sync1 <=  1'b0;
             RxAbort_wb    <=  1'b0;
             RxAbort_wb    <=  1'b0;
          end
        else
          begin
             RxAbort_sync1 <=  RxAbort_latch;
             RxAbort_wb    <=  RxAbort_sync1;
          end
     end
 
   always @ (posedge mrx_clk_pad_i or posedge wb_rst_i)
     begin
        if(wb_rst_i)
          begin
             RxAbortRst_sync1 <=  1'b0;
             RxAbortRst       <=  1'b0;
          end
        else
          begin
             RxAbortRst_sync1 <=  RxAbort_wb;
             RxAbortRst       <=  RxAbortRst_sync1;
          end
     end
 
 
 
   // Connecting Wishbone module
   eth_wishbone wishbone
     (
 
      .WB_CLK_I(wb_clk_i),
      .WB_DAT_I(wb_dat_i),
 
      .WB_DAT_O(BD_WB_DAT_O),
 
      // WISHBONE slave
 
      .WB_ADR_I(wb_adr_i[9:2]),
      .WB_WE_I(wb_we_i),
 
      .BDCs(BDCs),
      .WB_ACK_O(BDAck),
 
 
      .Reset(wb_rst_i),
 
      // WISHBONE master
 
      .m_wb_adr_o(m_wb_adr_tmp),
      .m_wb_sel_o(m_wb_sel_o),
      .m_wb_we_o(m_wb_we_o),
 
      .m_wb_dat_i(m_wb_dat_i),
      .m_wb_dat_o(m_wb_dat_o),
      .m_wb_cyc_o(m_wb_cyc_o),
 
      .m_wb_stb_o(m_wb_stb_o),
      .m_wb_ack_i(m_wb_ack_i),
      .m_wb_err_i(m_wb_err_i),
 
`ifdef ETH_WISHBONE_B3
 
      .m_wb_cti_o(m_wb_cti_o),
      .m_wb_bte_o(m_wb_bte_o),
`endif
 
 
      //TX
 
      .MTxClk(mtx_clk_pad_i),
      .TxStartFrm(TxStartFrm),
      .TxEndFrm(TxEndFrm),
 
      .TxUsedData(TxUsedData),
      .TxData(TxData),
 
      .TxRetry(TxRetry),
      .TxAbort(TxAbort),
      .TxUnderRun(TxUnderRun),
 
      .TxDone(TxDone),
 
      .PerPacketCrcEn(PerPacketCrcEn),
      .PerPacketPad(PerPacketPad),
 
      // Register
 
      .r_TxEn(r_TxEn),
      .r_RxEn(r_RxEn),
      .r_TxBDNum(r_TxBDNum),
 
      .r_RxFlow(r_RxFlow),
      .r_PassAll(r_PassAll),
 
      //RX
 
      .MRxClk(mrx_clk_pad_i),
      .RxData(RxData),
      .RxValid(RxValid),
 
      .RxStartFrm(RxStartFrm),
      .RxEndFrm(RxEndFrm),
 
      .Busy_IRQ(Busy_IRQ),
      .RxE_IRQ(RxE_IRQ),
      .RxB_IRQ(RxB_IRQ),
 
      .TxE_IRQ(TxE_IRQ),
      .TxB_IRQ(TxB_IRQ),
 
 
      .RxAbort(RxAbort_wb),
      .RxStatusWriteLatched_sync2(RxStatusWriteLatched_sync2),
 
 
      .InvalidSymbol(InvalidSymbol),
      .LatchedCrcError(LatchedCrcError),
      .RxLength(RxByteCnt),
 
      .RxLateCollision(RxLateCollision),
      .ShortFrame(ShortFrame),
      .DribbleNibble(DribbleNibble),
 
      .ReceivedPacketTooBig(ReceivedPacketTooBig),
      .LoadRxStatus(LoadRxStatus),
      .RetryCntLatched(RetryCntLatched),
 
      .RetryLimit(RetryLimit),
      .LateCollLatched(LateCollLatched),
      .DeferLatched(DeferLatched),
 
      .RstDeferLatched(RstDeferLatched),
 
      .CarrierSenseLost(CarrierSenseLost),
      .ReceivedPacketGood(ReceivedPacketGood),
      .AddressMiss(AddressMiss),
 
      .ReceivedPauseFrm(ReceivedPauseFrm)
 
`ifdef ETH_BIST
      ,
 
      .mbist_si_i       (mbist_si_i),
 
      .mbist_so_o       (mbist_so_o),
 
      .mbist_ctrl_i       (mbist_ctrl_i)
`endif
`ifdef WISHBONE_DEBUG
      ,
 
      .dbg_dat0(wb_dbg_dat0)
`endif
 
      );
 
   assign m_wb_adr_o = {m_wb_adr_tmp, 2'h0};
 
   // Connecting MacStatus module
   eth_macstatus macstatus1
     (
 
      .MRxClk(mrx_clk_pad_i),
      .Reset(wb_rst_i),
 
      .ReceiveEnd(ReceiveEnd),
      .ReceivedPacketGood(ReceivedPacketGood),
      .ReceivedLengthOK(ReceivedLengthOK),
 
      .RxCrcError(RxCrcError),
      .MRxErr(MRxErr_Lb),
      .MRxDV(MRxDV_Lb),
 
      .RxStateSFD(RxStateSFD),
      .RxStateData(RxStateData),
      .RxStatePreamble(RxStatePreamble),
 
      .RxStateIdle(RxStateIdle),
      .Transmitting(Transmitting),
      .RxByteCnt(RxByteCnt),
 
      .RxByteCntEq0(RxByteCntEq0),
      .RxByteCntGreat2(RxByteCntGreat2),
      .RxByteCntMaxFrame(RxByteCntMaxFrame),
 
      .InvalidSymbol(InvalidSymbol),
 
      .MRxD(MRxD_Lb),
      .LatchedCrcError(LatchedCrcError),
      .Collision(mcoll_pad_i),
 
      .CollValid(r_CollValid),
      .RxLateCollision(RxLateCollision),
      .r_RecSmall(r_RecSmall),
 
      .r_MinFL(r_MinFL),
      .r_MaxFL(r_MaxFL),
      .ShortFrame(ShortFrame),
 
      .DribbleNibble(DribbleNibble),
      .ReceivedPacketTooBig(ReceivedPacketTooBig),
      .r_HugEn(r_HugEn),
 
      .LoadRxStatus(LoadRxStatus),
      .RetryCnt(RetryCnt),
      .StartTxDone(StartTxDone),
 
      .StartTxAbort(StartTxAbort),
      .RetryCntLatched(RetryCntLatched),
      .MTxClk(mtx_clk_pad_i),
 
      .MaxCollisionOccured(MaxCollisionOccured),
      .RetryLimit(RetryLimit),
      .LateCollision(LateCollision),
 
      .LateCollLatched(LateCollLatched),
      .DeferIndication(DeferIndication),
      .DeferLatched(DeferLatched),
 
      .RstDeferLatched(RstDeferLatched),
 
      .TxStartFrm(TxStartFrmOut),
      .StatePreamble(StatePreamble),
      .StateData(StateData),
 
      .CarrierSense(CarrierSense_Tx2),
      .CarrierSenseLost(CarrierSenseLost),
      .TxUsedData(TxUsedDataIn),
 
      .LatchedMRxErr(LatchedMRxErr),
      .Loopback(r_LoopBck),
      .r_FullD(r_FullD)
      );
 
 
endmodule

Line No.	Rev	Author	Line
1	408	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// eth.v ////`
4			`//// ////`
5			`//// This file is part of the Ethernet IP core project ////`
6	439	julius	`//// http://www.opencores.org/project,ethmac ////`
7	408	julius	`//// ////`
8			`//// Author(s): ////`
9			`//// - Igor Mohor (igorM@opencores.org) ////`
10			`//// ////`
11			`//// All additional information is available in the Readme.txt ////`
12			`//// file. ////`
13			`//// ////`
14			`//////////////////////////////////////////////////////////////////////`
15			`//// ////`
16			`//// Copyright (C) 2001, 2002 Authors ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer. ////`
22			`//// ////`
23			`//// This source file is free software; you can redistribute it ////`
24			`//// and/or modify it under the terms of the GNU Lesser General ////`
25			`//// Public License as published by the Free Software Foundation; ////`
26			`//// either version 2.1 of the License, or (at your option) any ////`
27			`//// later version. ////`
28			`//// ////`
29			`//// This source is distributed in the hope that it will be ////`
30			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
31			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
32			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
33			`//// details. ////`
34			`//// ////`
35			`//// You should have received a copy of the GNU Lesser General ////`
36			`//// Public License along with this source; if not, download it ////`
37			`//// from http://www.opencores.org/lgpl.shtml ////`
38			`//// ////`
39			`//////////////////////////////////////////////////////////////////////`
40			`//`
41
42
43	409	julius	`include "ethmac_defines.v"
44	408	julius	`include "timescale.v"
45
46
47	409	julius	`module ethmac // renamed jb`
48	439	julius	`(`
49			`// WISHBONE common`
50			`wb_clk_i, wb_rst_i, wb_dat_i, wb_dat_o,`
51	408	julius
52	439	julius	`// WISHBONE slave`
53			`wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i, wb_ack_o, wb_err_o,`
54	408	julius
55	439	julius	`// WISHBONE master`
56			`m_wb_adr_o, m_wb_sel_o, m_wb_we_o,`
57			`m_wb_dat_o, m_wb_dat_i, m_wb_cyc_o,`
58			`m_wb_stb_o, m_wb_ack_i, m_wb_err_i,`
59	408	julius
60			`ifdef ETH_WISHBONE_B3
61	439	julius	`m_wb_cti_o, m_wb_bte_o,`
62	408	julius	`endif
63
64	439	julius	`//TX`
65			`mtx_clk_pad_i, mtxd_pad_o, mtxen_pad_o, mtxerr_pad_o,`
66	408	julius
67	439	julius	`//RX`
68			`mrx_clk_pad_i, mrxd_pad_i, mrxdv_pad_i, mrxerr_pad_i, mcoll_pad_i,`
69			`mcrs_pad_i,`
70	408	julius
71	439	julius	`// MIIM`
72			`mdc_pad_o, md_pad_i, md_pad_o, md_padoe_o,`
73	408	julius
74	439	julius	`int_o`
75	408	julius
76	439	julius	`// Bist`
77	408	julius	`ifdef ETH_BIST
78	439	julius	`,`
79			`// debug chain signals`
80			`mbist_si_i, // bist scan serial in`
81			`mbist_so_o, // bist scan serial out`
82			`mbist_ctrl_i // bist chain shift control`
83	408	julius	`endif
84
85	439	julius	`);`
86	408	julius
87
88
89	439	julius	`// WISHBONE common`
90			`input wb_clk_i; // WISHBONE clock`
91			`input wb_rst_i; // WISHBONE reset`
92			`input [31:0] wb_dat_i; // WISHBONE data input`
93			`output [31:0] wb_dat_o; // WISHBONE data output`
94			`output wb_err_o; // WISHBONE error output`
95	408	julius
96	439	julius	`// WISHBONE slave`
97			`input [11:2] wb_adr_i; // WISHBONE address input`
98			`input [3:0] wb_sel_i; // WISHBONE byte select input`
99			`input wb_we_i; // WISHBONE write enable input`
100			`input wb_cyc_i; // WISHBONE cycle input`
101			`input wb_stb_i; // WISHBONE strobe input`
102			`output wb_ack_o; // WISHBONE acknowledge output`
103	408	julius
104	439	julius	`// WISHBONE master`
105			`output [31:0] m_wb_adr_o;`
106			`output [3:0] m_wb_sel_o;`
107			`output m_wb_we_o;`
108			`input [31:0] m_wb_dat_i;`
109			`output [31:0] m_wb_dat_o;`
110			`output m_wb_cyc_o;`
111			`output m_wb_stb_o;`
112			`input m_wb_ack_i;`
113			`input m_wb_err_i;`
114	408	julius
115	439	julius	`wire [29:0] m_wb_adr_tmp;`
116	408	julius
117			`ifdef ETH_WISHBONE_B3
118	439	julius	`output [2:0] m_wb_cti_o; // Cycle Type Identifier`
119			`output [1:0] m_wb_bte_o; // Burst Type Extension`
120	408	julius	`endif
121
122	439	julius	`// Tx`
123			`input mtx_clk_pad_i; // Transmit clock (from PHY)`
124			`output [3:0] mtxd_pad_o; // Transmit nibble (to PHY)`
125			`output mtxen_pad_o; // Transmit enable (to PHY)`
126			`output mtxerr_pad_o; // Transmit error (to PHY)`
127	408	julius
128	439	julius	`// Rx`
129			`input mrx_clk_pad_i; // Receive clock (from PHY)`
130			`input [3:0] mrxd_pad_i; // Receive nibble (from PHY)`
131			`input mrxdv_pad_i; // Receive data valid (from PHY)`
132			`input mrxerr_pad_i; // Receive data error (from PHY)`
133	408	julius
134	439	julius	`// Common Tx and Rx`
135			`input mcoll_pad_i; // Collision (from PHY)`
136			`input mcrs_pad_i; // Carrier sense (from PHY)`
137	408	julius
138	439	julius	`// MII Management interface`
139			`input md_pad_i; // MII data input (from I/O cell)`
140			`output mdc_pad_o; // MII Management data clock (to PHY)`
141			`output md_pad_o; // MII data output (to I/O cell)`
142			`output md_padoe_o; // MII data output enable (to I/O cell)`
143	408	julius
144	439	julius	`output int_o; // Interrupt output`
145	408	julius
146	439	julius	`// Bist`
147	408	julius	`ifdef ETH_BIST
148	439	julius	`input mbist_si_i; // bist scan serial in`
149			`output mbist_so_o; // bist scan serial out`
150			input [`ETH_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
151	408	julius	`endif
152
153			`ifdef WISHBONE_DEBUG
154	439	julius	`wire [31:0] wb_dbg_dat0;`
155	408	julius	`endif
156
157
158	439	julius	`wire [7:0] r_ClkDiv;`
159			`wire r_MiiNoPre;`
160			`wire [15:0] r_CtrlData;`
161			`wire [4:0] r_FIAD;`
162			`wire [4:0] r_RGAD;`
163			`wire r_WCtrlData;`
164			`wire r_RStat;`
165			`wire r_ScanStat;`
166			`wire NValid_stat;`
167			`wire Busy_stat;`
168			`wire LinkFail;`
169			`wire [15:0] Prsd; // Read Status Data (data read`
170			`// from the PHY)`
171			`wire WCtrlDataStart;`
172			`wire RStatStart;`
173			`wire UpdateMIIRX_DATAReg;`
174	408	julius
175	439	julius	`wire TxStartFrm;`
176			`wire TxEndFrm;`
177			`wire TxUsedData;`
178			`wire [7:0] TxData;`
179			`wire TxRetry;`
180			`wire TxAbort;`
181			`wire TxUnderRun;`
182			`wire TxDone;`
183	408	julius
184
185	439	julius	`reg WillSendControlFrame_sync1;`
186			`reg WillSendControlFrame_sync2;`
187			`reg WillSendControlFrame_sync3;`
188			`reg RstTxPauseRq;`
189	408	julius
190	439	julius	`reg TxPauseRq_sync1;`
191			`reg TxPauseRq_sync2;`
192			`reg TxPauseRq_sync3;`
193			`reg TPauseRq;`
194	408	julius
195
196	439	julius	`// Connecting Miim module`
197			`eth_miim miim1`
198			`(`
199			`.Clk(wb_clk_i),`
200			`.Reset(wb_rst_i),`
201			`.Divider(r_ClkDiv),`
202			`.NoPre(r_MiiNoPre),`
203			`.CtrlData(r_CtrlData),`
204			`.Rgad(r_RGAD),`
205			`.Fiad(r_FIAD),`
206			`.WCtrlData(r_WCtrlData),`
207			`.RStat(r_RStat),`
208			`.ScanStat(r_ScanStat),`
209			`.Mdi(md_pad_i),`
210			`.Mdo(md_pad_o),`
211			`.MdoEn(md_padoe_o),`
212			`.Mdc(mdc_pad_o),`
213			`.Busy(Busy_stat),`
214			`.Prsd(Prsd),`
215			`.LinkFail(LinkFail),`
216			`.Nvalid(NValid_stat),`
217			`.WCtrlDataStart(WCtrlDataStart),`
218			`.RStatStart(RStatStart),`
219			`.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg)`
220			`);`
221	408	julius
222
223
224
225	439	julius	`wire [3:0] RegCs; // Connected to registers`
226			`wire [31:0] RegDataOut; // Multiplexed to wb_dat_o`
227			`wire r_RecSmall; // Receive small frames`
228			`wire r_LoopBck; // Loopback`
229			`wire r_TxEn; // Tx Enable`
230			`wire r_RxEn; // Rx Enable`
231	408	julius
232	439	julius	`wire MRxDV_Lb; // Muxed MII receive data valid`
233			`wire MRxErr_Lb; // Muxed MII Receive Error`
234			`wire [3:0] MRxD_Lb; // Muxed MII Receive Data`
235			`wire Transmitting; // Indication that TxEthMAC is transmitting`
236			`wire r_HugEn; // Huge packet enable`
237			`wire r_DlyCrcEn; // Delayed CRC enabled`
238			`wire [15:0] r_MaxFL; // Maximum frame length`
239	408	julius
240	439	julius	`wire [15:0] r_MinFL; // Minimum frame length`
241			`wire ShortFrame;`
242			`wire DribbleNibble; // Extra nibble received`
243			`wire ReceivedPacketTooBig; // Received packet is too big`
244			`wire [47:0] r_MAC; // MAC address`
245			`wire LoadRxStatus; // Rx status was loaded`
246			`wire [31:0] r_HASH0; // HASH table, lower 4 bytes`
247			`wire [31:0] r_HASH1; // HASH table, upper 4 bytes`
248			`wire [7:0] r_TxBDNum; // Receive buffer descriptor number`
249			`wire [6:0] r_IPGT; //`
250			`wire [6:0] r_IPGR1; //`
251			`wire [6:0] r_IPGR2; //`
252			`wire [5:0] r_CollValid; //`
253			`wire [15:0] r_TxPauseTV; // Transmit PAUSE value`
254			`wire r_TxPauseRq; // Transmit PAUSE request`
255	408	julius
256	439	julius	`wire [3:0] r_MaxRet; //`
257			`wire r_NoBckof; //`
258			`wire r_ExDfrEn; //`
259			`wire r_TxFlow; // Tx flow control enable`
260			`wire r_IFG; // Minimum interframe gap for incoming packets`
261	408	julius
262	439	julius	`wire TxB_IRQ; // Interrupt Tx Buffer`
263			`wire TxE_IRQ; // Interrupt Tx Error`
264			`wire RxB_IRQ; // Interrupt Rx Buffer`
265			`wire RxE_IRQ; // Interrupt Rx Error`
266			`wire Busy_IRQ; // Interrupt Busy (lack of buffers)`
267	408	julius
268	439	julius	`//wire DWord;`
269			`wire ByteSelected;`
270			`wire BDAck;`
271			`wire [31:0] BD_WB_DAT_O; // wb_dat_o that comes from the Wishbone module (for buffer descriptors read/write)`
272			`wire [3:0] BDCs; // Buffer descriptor CS`
273			`wire CsMiss; // When access to the address between 0x800 and 0xfff occurs, acknowledge is set`
274			`// but data is not valid.`
275			`wire r_Pad;`
276			`wire r_CrcEn;`
277			`wire r_FullD;`
278			`wire r_Pro;`
279			`wire r_Bro;`
280			`wire r_NoPre;`
281			`wire r_RxFlow;`
282			`wire r_PassAll;`
283			`wire TxCtrlEndFrm;`
284			`wire StartTxDone;`
285			`wire SetPauseTimer;`
286			`wire TxUsedDataIn;`
287			`wire TxDoneIn;`
288			`wire TxAbortIn;`
289			`wire PerPacketPad;`
290			`wire PadOut;`
291			`wire PerPacketCrcEn;`
292			`wire CrcEnOut;`
293			`wire TxStartFrmOut;`
294			`wire TxEndFrmOut;`
295			`wire ReceivedPauseFrm;`
296			`wire ControlFrmAddressOK;`
297			`wire RxStatusWriteLatched_sync2;`
298			`wire LateCollision;`
299			`wire DeferIndication;`
300			`wire LateCollLatched;`
301			`wire DeferLatched;`
302			`wire RstDeferLatched;`
303			`wire CarrierSenseLost;`
304	408	julius
305	439	julius	`wire temp_wb_ack_o;`
306			`wire [31:0] temp_wb_dat_o;`
307			`wire temp_wb_err_o;`
308	408	julius
309			`ifdef ETH_REGISTERED_OUTPUTS
310	439	julius	`reg temp_wb_ack_o_reg;`
311			`reg [31:0] temp_wb_dat_o_reg;`
312			`reg temp_wb_err_o_reg;`
313	408	julius	`endif
314
315	439	julius	`//assign DWord = &wb_sel_i;`
316			`assign ByteSelected = \|wb_sel_i;`
317			`assign RegCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[3]; // 0x0 - 0x3FF`
318			`assign RegCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[2]; // 0x0 - 0x3FF`
319			`assign RegCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[1]; // 0x0 - 0x3FF`
320			`assign RegCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & ~wb_adr_i[10] & wb_sel_i[0]; // 0x0 - 0x3FF`
321			`assign BDCs[3] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[3]; // 0x400 - 0x7FF`
322			`assign BDCs[2] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[2]; // 0x400 - 0x7FF`
323			`assign BDCs[1] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[1]; // 0x400 - 0x7FF`
324			`assign BDCs[0] = wb_stb_i & wb_cyc_i & ByteSelected & ~wb_adr_i[11] & wb_adr_i[10] & wb_sel_i[0]; // 0x400 - 0x7FF`
325			`assign CsMiss = wb_stb_i & wb_cyc_i & ByteSelected & wb_adr_i[11]; // 0x800 - 0xfFF`
326			`assign temp_wb_dat_o = ((\|RegCs) & ~wb_we_i)? RegDataOut : BD_WB_DAT_O;`
327			`assign temp_wb_err_o = wb_stb_i & wb_cyc_i & (~ByteSelected \| CsMiss);`
328	408	julius
329			`ifdef ETH_REGISTERED_OUTPUTS
330	439	julius	`assign wb_ack_o = temp_wb_ack_o_reg;`
331			`assign wb_dat_o[31:0] = temp_wb_dat_o_reg;`
332			`assign wb_err_o = temp_wb_err_o_reg;`
333	408	julius	`else
334	439	julius	`assign wb_ack_o = temp_wb_ack_o;`
335			`assign wb_dat_o[31:0] = temp_wb_dat_o;`
336			`assign wb_err_o = temp_wb_err_o;`
337	408	julius	`endif
338
339			`ifdef ETH_AVALON_BUS
340	439	julius	`// As Avalon has no corresponding "error" signal, I (erroneously) will`
341			`// send an ack to Avalon, even when accessing undefined memory. This`
342			`// is a grey area in Avalon vs. Wishbone specs: My understanding`
343			`// is that Avalon expects all memory addressable by the addr bus feeding`
344			`// a slave to be, at the very minimum, readable.`
345			`assign temp_wb_ack_o = (\|RegCs) \| BDAck \| CsMiss;`
346	408	julius	`else // WISHBONE
347	439	julius	`assign temp_wb_ack_o = (\|RegCs) \| BDAck;`
348	408	julius	`endif
349
350			`ifdef ETH_REGISTERED_OUTPUTS
351	439	julius	`always @ (posedge wb_clk_i or posedge wb_rst_i)`
352			`begin`
353			`if(wb_rst_i)`
354			`begin`
355			`temp_wb_ack_o_reg <= 1'b0;`
356			`temp_wb_dat_o_reg <= 32'h0;`
357			`temp_wb_err_o_reg <= 1'b0;`
358			`end`
359			`else`
360			`begin`
361			`temp_wb_ack_o_reg <= temp_wb_ack_o & ~temp_wb_ack_o_reg;`
362			`temp_wb_dat_o_reg <= temp_wb_dat_o;`
363			`temp_wb_err_o_reg <= temp_wb_err_o & ~temp_wb_err_o_reg;`
364			`end`
365			`end`
366	408	julius	`endif
367
368
369	439	julius	`// Connecting Ethernet registers`
370			`eth_registers ethreg1`
371			`(`
372			`.DataIn(wb_dat_i),`
373			`.Address(wb_adr_i[9:2]),`
374			`.Rw(wb_we_i),`
375
376			`.Cs(RegCs),`
377			`.Clk(wb_clk_i),`
378			`.Reset(wb_rst_i),`
379
380			`.DataOut(RegDataOut),`
381			`.r_RecSmall(r_RecSmall),`
382
383			`.r_Pad(r_Pad),`
384			`.r_HugEn(r_HugEn),`
385			`.r_CrcEn(r_CrcEn),`
386
387			`.r_DlyCrcEn(r_DlyCrcEn),`
388			`.r_FullD(r_FullD),`
389
390			`.r_ExDfrEn(r_ExDfrEn),`
391			`.r_NoBckof(r_NoBckof),`
392			`.r_LoopBck(r_LoopBck),`
393
394			`.r_IFG(r_IFG),`
395			`.r_Pro(r_Pro),`
396			`.r_Iam(),`
397
398			`.r_Bro(r_Bro),`
399			`.r_NoPre(r_NoPre),`
400			`.r_TxEn(r_TxEn),`
401
402			`.r_RxEn(r_RxEn),`
403			`.Busy_IRQ(Busy_IRQ),`
404			`.RxE_IRQ(RxE_IRQ),`
405
406			`.RxB_IRQ(RxB_IRQ),`
407			`.TxE_IRQ(TxE_IRQ),`
408			`.TxB_IRQ(TxB_IRQ),`
409
410			`.r_IPGT(r_IPGT),`
411
412			`.r_IPGR1(r_IPGR1),`
413			`.r_IPGR2(r_IPGR2),`
414			`.r_MinFL(r_MinFL),`
415
416			`.r_MaxFL(r_MaxFL),`
417			`.r_MaxRet(r_MaxRet),`
418			`.r_CollValid(r_CollValid),`
419
420			`.r_TxFlow(r_TxFlow),`
421			`.r_RxFlow(r_RxFlow),`
422			`.r_PassAll(r_PassAll),`
423
424			`.r_MiiNoPre(r_MiiNoPre),`
425			`.r_ClkDiv(r_ClkDiv),`
426
427			`.r_WCtrlData(r_WCtrlData),`
428			`.r_RStat(r_RStat),`
429			`.r_ScanStat(r_ScanStat),`
430
431			`.r_RGAD(r_RGAD),`
432			`.r_FIAD(r_FIAD),`
433			`.r_CtrlData(r_CtrlData),`
434
435			`.NValid_stat(NValid_stat),`
436			`.Busy_stat(Busy_stat),`
437
438			`.LinkFail(LinkFail),`
439			`.r_MAC(r_MAC),`
440			`.WCtrlDataStart(WCtrlDataStart),`
441
442			`.RStatStart(RStatStart),`
443			`.UpdateMIIRX_DATAReg(UpdateMIIRX_DATAReg),`
444			`.Prsd(Prsd),`
445
446			`.r_TxBDNum(r_TxBDNum),`
447			`.int_o(int_o),`
448
449			`.r_HASH0(r_HASH0),`
450			`.r_HASH1(r_HASH1),`
451			`.r_TxPauseRq(r_TxPauseRq),`
452
453			`.r_TxPauseTV(r_TxPauseTV),`
454			`.RstTxPauseRq(RstTxPauseRq),`
455			`.TxCtrlEndFrm(TxCtrlEndFrm),`
456
457			`.StartTxDone(StartTxDone),`
458			`.TxClk(mtx_clk_pad_i),`
459			`.RxClk(mrx_clk_pad_i),`
460
461			`.dbg_dat(wb_dbg_dat0),`
462
463			`.SetPauseTimer(SetPauseTimer)`
464
465			`);`
466	408	julius
467
468
469	439	julius	`wire [7:0] RxData;`
470			`wire RxValid;`
471			`wire RxStartFrm;`
472			`wire RxEndFrm;`
473			`wire RxAbort;`
474	408	julius
475	439	julius	`wire WillTransmit; // Will transmit (to RxEthMAC)`
476			`wire ResetCollision; // Reset Collision (for synchronizing`
477			`// collision)`
478			`wire [7:0] TxDataOut; // Transmit Packet Data (to TxEthMAC)`
479			`wire WillSendControlFrame;`
480			`wire ReceiveEnd;`
481			`wire ReceivedPacketGood;`
482			`wire ReceivedLengthOK;`
483			`wire InvalidSymbol;`
484			`wire LatchedCrcError;`
485			`wire RxLateCollision;`
486			`wire [3:0] RetryCntLatched;`
487			`wire [3:0] RetryCnt;`
488			`wire StartTxAbort;`
489			`wire MaxCollisionOccured;`
490			`wire RetryLimit;`
491			`wire StatePreamble;`
492			`wire [1:0] StateData;`
493	408	julius
494	439	julius	`// Connecting MACControl`
495			`eth_maccontrol maccontrol1`
496			`(`
497			`.MTxClk(mtx_clk_pad_i),`
498			`.TPauseRq(TPauseRq),`
499
500			`.TxPauseTV(r_TxPauseTV),`

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