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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [i2c_master_slave/] [README] - Blame information for rev 426

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i2c master and slave
 
This core is based on the i2c master by Richard Herveille from OpenCores.org,
with added slave capability by ORSoC. See the driver software in sw/drivers
for details on use of the core.
 

Line No.	Rev	Author	Line
1	408	julius	`i2c master and slave`
2
3			`This core is based on the i2c master by Richard Herveille from OpenCores.org,`
4			`with added slave capability by ORSoC. See the driver software in sw/drivers`
5			`for details on use of the core.`
6

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [i2c_master_slave/] [README] - Blame information for rev 426