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//////////////////////////////////////////////////////////////////////
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//// ////
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//// orpsoc-defines ////
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//// ////
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//// Top level ORPSoC defines file ////
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//// ////
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//// Included in toplevel and testbench ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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// Define board clock - main system clock period
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// 20ns period = 50MHz freq.
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julius |
`define BOARD_CLOCK_PERIOD 20
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julius |
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// Included modules: define to include
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julius |
`define JTAG_DEBUG
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julius |
`define UART0
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julius |
`define RAM_WB
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`define INTGEN
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julius |
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// end of included module defines - keep this comment line here
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//
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// Arbiter defines
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//
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// Uncomment to register things through arbiter (hopefully quicker design)
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// Instruction bus arbiter
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//`define ARBITER_IBUS_REGISTERING
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`define ARBITER_IBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12
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// Data bus arbiter
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//`define ARBITER_DBUS_REGISTERING
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`define ARBITER_DBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12
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// Byte bus (peripheral bus) arbiter
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// Don't really need the watchdog here - the databus will pick it up
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//`define ARBITER_BYTEBUS_WATCHDOG
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// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
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`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
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