1 |
361 |
julius |
//////////////////////////////////////////////////////////////////////
|
2 |
|
|
//// ////
|
3 |
|
|
//// orpsoc-defines ////
|
4 |
|
|
//// ////
|
5 |
|
|
//// Top level ORPSoC defines file ////
|
6 |
|
|
//// ////
|
7 |
|
|
//// Included in toplevel and testbench ////
|
8 |
|
|
//// ////
|
9 |
|
|
//////////////////////////////////////////////////////////////////////
|
10 |
|
|
//// ////
|
11 |
|
|
//// Copyright (C) 2009, 2010 Authors and OPENCORES.ORG ////
|
12 |
|
|
//// ////
|
13 |
|
|
//// This source file may be used and distributed without ////
|
14 |
|
|
//// restriction provided that this copyright statement is not ////
|
15 |
|
|
//// removed from the file and that any derivative work contains ////
|
16 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
17 |
|
|
//// ////
|
18 |
|
|
//// This source file is free software; you can redistribute it ////
|
19 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
20 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
21 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
22 |
|
|
//// later version. ////
|
23 |
|
|
//// ////
|
24 |
|
|
//// This source is distributed in the hope that it will be ////
|
25 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
26 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
27 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
28 |
|
|
//// details. ////
|
29 |
|
|
//// ////
|
30 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
31 |
|
|
//// Public License along with this source; if not, download it ////
|
32 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
33 |
|
|
//// ////
|
34 |
|
|
//////////////////////////////////////////////////////////////////////
|
35 |
|
|
|
36 |
|
|
// Define board clock - main system clock period
|
37 |
|
|
// 20ns period = 50MHz freq.
|
38 |
|
|
`define BOARD_CLOCK_PERIOD_NS 20
|
39 |
|
|
|
40 |
|
|
// Included modules: define to include
|
41 |
397 |
julius |
`define JTAG_DEBUG
|
42 |
361 |
julius |
`define UART0
|
43 |
|
|
|
44 |
|
|
// end of included module defines - keep this comment line here
|
45 |
|
|
|
46 |
|
|
//
|
47 |
|
|
// Arbiter defines
|
48 |
|
|
//
|
49 |
|
|
|
50 |
|
|
// Uncomment to register things through arbiter (hopefully quicker design)
|
51 |
|
|
// Instruction bus arbiter
|
52 |
|
|
//`define ARBITER_IBUS_REGISTERING
|
53 |
|
|
`define ARBITER_IBUS_WATCHDOG
|
54 |
|
|
// Watchdog timeout: 2^(ARBITER_IBUS_WATCHDOG_TIMER_WIDTH+1) cycles
|
55 |
|
|
`define ARBITER_IBUS_WATCHDOG_TIMER_WIDTH 12
|
56 |
|
|
|
57 |
|
|
// Data bus arbiter
|
58 |
|
|
|
59 |
|
|
//`define ARBITER_DBUS_REGISTERING
|
60 |
|
|
`define ARBITER_DBUS_WATCHDOG
|
61 |
|
|
// Watchdog timeout: 2^(ARBITER_DBUS_WATCHDOG_TIMER_WIDTH+1) cycles
|
62 |
|
|
`define ARBITER_DBUS_WATCHDOG_TIMER_WIDTH 12
|
63 |
|
|
|
64 |
|
|
// Byte bus (peripheral bus) arbiter
|
65 |
|
|
// Don't really need the watchdog here - the databus will pick it up
|
66 |
|
|
//`define ARBITER_BYTEBUS_WATCHDOG
|
67 |
|
|
// Watchdog timeout: 2^(ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH+1) cycles
|
68 |
|
|
`define ARBITER_BYTEBUS_WATCHDOG_TIMER_WIDTH 9
|
69 |
|
|
|