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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [usbhostslave_hostcontrol_h.v] - Blame information for rev 439

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Line No. Rev Author Line
1 408 julius
//////////////////////////////////////////////////////////////////////
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// usbHostControl_h.v                                          
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//////////////////////////////////////////////////////////////////////
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`ifdef usbHostControl_h_vdefined
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`else
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`define usbHostControl_h_vdefined
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//HCRegIndices
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`define TX_CONTROL_REG 4'h0
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`define TX_TRANS_TYPE_REG 4'h1
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`define TX_LINE_CONTROL_REG 4'h2
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`define TX_SOF_ENABLE_REG 4'h3
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`define TX_ADDR_REG 4'h4
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`define TX_ENDP_REG 4'h5
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`define FRAME_NUM_MSB_REG 4'h6
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`define FRAME_NUM_LSB_REG 4'h7
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`define INTERRUPT_STATUS_REG 4'h8
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`define INTERRUPT_MASK_REG 4'h9
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`define RX_STATUS_REG 4'ha
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`define RX_PID_REG 4'hb
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`define RX_ADDR_REG 4'hc
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`define RX_ENDP_REG 4'hd
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`define RX_CONNECT_STATE_REG 4'he
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`define HOST_SOF_TIMER_MSB_REG 4'hf
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`define HCREG_BUFFER_LEN 4'hf
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`define HCREG_MASK 4'hf
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//TXControlRegIndices
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`define TRANS_REQ_BIT 0
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`define SOF_SYNC_BIT 1
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`define PREAMBLE_ENABLE_BIT 2
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`define ISO_ENABLE_BIT 3
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//interruptRegIndices
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`define TRANS_DONE_BIT 0
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`define RESUME_INT_BIT 1
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`define CONNECTION_EVENT_BIT 2
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`define SOF_SENT_BIT 3
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//TXTransactionTypes
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`define SETUP_TRANS 0
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`define IN_TRANS 1
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`define OUTDATA0_TRANS 2
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`define OUTDATA1_TRANS 3
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 //TXLineControlIndices
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`define TX_LINE_STATE_LSBIT 0
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`define TX_LINE_STATE_MSBIT 1
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`define DIRECT_CONTROL_BIT 2
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`define FULL_SPEED_LINE_POLARITY_BIT 3
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`define FULL_SPEED_LINE_RATE_BIT 4
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//TXSOFEnableIndices
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`define SOF_EN_BIT 0
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//SOFTimeConstants 
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//`define SOF_TX_TIME 80     //Fix this. Need correct SOF TX interval   
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//Note that 'SOF_TX_TIME' is 48000 - 3. This is to account for the delay in resetting the SOF timer 
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`define SOF_TX_TIME 16'hbb7d     //Correct SOF interval for 48MHz clock.
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//`define SOF_TX_MARGIN 2 
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`define SOF_TX_MARGIN 16'h0190 //This is the transmission time for 100 bytes. May need to tweak
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//Host RXStatusRegIndices 
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`define HC_CRC_ERROR_BIT 0
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`define HC_BIT_STUFF_ERROR_BIT 1
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`define HC_RX_OVERFLOW_BIT 2
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`define HC_RX_TIME_OUT_BIT 3
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`define HC_NAK_RXED_BIT 4
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`define HC_STALL_RXED_BIT 5
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`define HC_ACK_RXED_BIT 6
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`define HC_DATA_SEQUENCE_BIT 7
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`endif //usbHostControl_h_vdefined 

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