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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [usbhostslave_wishbonebus_h.v] - Blame information for rev 522

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//////////////////////////////////////////////////////////////////////
// wishBoneBus_h.v                                              
//////////////////////////////////////////////////////////////////////
 
`ifdef wishBoneBus_h_vdefined
`else
`define wishBoneBus_h_vdefined
 
//memoryMap
`define HCREG_BASE 8'h00
`define HCREG_BASE_PLUS_0X10 8'h10
`define HOST_RX_FIFO_BASE 8'h20
`define HOST_TX_FIFO_BASE 8'h30
`define SCREG_BASE 8'h40
`define SCREG_BASE_PLUS_0X10 8'h50
`define EP0_RX_FIFO_BASE 8'h60
`define EP0_TX_FIFO_BASE 8'h70
`define EP1_RX_FIFO_BASE 8'h80
`define EP1_TX_FIFO_BASE 8'h90
`define EP2_RX_FIFO_BASE 8'ha0
`define EP2_TX_FIFO_BASE 8'hb0
`define EP3_RX_FIFO_BASE 8'hc0
`define EP3_TX_FIFO_BASE 8'hd0
`define HOST_SLAVE_CONTROL_BASE 8'he0
`define ADDRESS_DECODE_MASK 8'hf0
 
//FifoAddresses
`define FIFO_DATA_REG 3'b000
`define FIFO_STATUS_REG 3'b001
`define FIFO_DATA_COUNT_MSB 3'b010
`define FIFO_DATA_COUNT_LSB 3'b011
`define FIFO_CONTROL_REG 3'b100
 
`endif //wishBoneBus_h_vdefined
 

Line No.	Rev	Author	Line
1	408	julius	`//////////////////////////////////////////////////////////////////////`
2			`// wishBoneBus_h.v`
3			`//////////////////////////////////////////////////////////////////////`
4
5			`ifdef wishBoneBus_h_vdefined
6			`else
7			`define wishBoneBus_h_vdefined
8
9			`//memoryMap`
10			`define HCREG_BASE 8'h00
11			`define HCREG_BASE_PLUS_0X10 8'h10
12			`define HOST_RX_FIFO_BASE 8'h20
13			`define HOST_TX_FIFO_BASE 8'h30
14			`define SCREG_BASE 8'h40
15			`define SCREG_BASE_PLUS_0X10 8'h50
16			`define EP0_RX_FIFO_BASE 8'h60
17			`define EP0_TX_FIFO_BASE 8'h70
18			`define EP1_RX_FIFO_BASE 8'h80
19			`define EP1_TX_FIFO_BASE 8'h90
20			`define EP2_RX_FIFO_BASE 8'ha0
21			`define EP2_TX_FIFO_BASE 8'hb0
22			`define EP3_RX_FIFO_BASE 8'hc0
23			`define EP3_TX_FIFO_BASE 8'hd0
24			`define HOST_SLAVE_CONTROL_BASE 8'he0
25			`define ADDRESS_DECODE_MASK 8'hf0
26
27			`//FifoAddresses`
28			`define FIFO_DATA_REG 3'b000
29			`define FIFO_STATUS_REG 3'b001
30			`define FIFO_DATA_COUNT_MSB 3'b010
31			`define FIFO_DATA_COUNT_LSB 3'b011
32			`define FIFO_CONTROL_REG 3'b100
33
34			`endif //wishBoneBus_h_vdefined
35

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [usbhostslave_wishbonebus_h.v] - Blame information for rev 522