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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [include/] [usbhostslave_wishbonebus_h.v] - Blame information for rev 408

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Line No. Rev Author Line
1 408 julius
//////////////////////////////////////////////////////////////////////
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// wishBoneBus_h.v                                              
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//////////////////////////////////////////////////////////////////////
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`ifdef wishBoneBus_h_vdefined
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`else
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`define wishBoneBus_h_vdefined
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//memoryMap
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`define HCREG_BASE 8'h00
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`define HCREG_BASE_PLUS_0X10 8'h10
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`define HOST_RX_FIFO_BASE 8'h20
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`define HOST_TX_FIFO_BASE 8'h30
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`define SCREG_BASE 8'h40
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`define SCREG_BASE_PLUS_0X10 8'h50
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`define EP0_RX_FIFO_BASE 8'h60
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`define EP0_TX_FIFO_BASE 8'h70
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`define EP1_RX_FIFO_BASE 8'h80
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`define EP1_TX_FIFO_BASE 8'h90
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`define EP2_RX_FIFO_BASE 8'ha0
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`define EP2_TX_FIFO_BASE 8'hb0
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`define EP3_RX_FIFO_BASE 8'hc0
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`define EP3_TX_FIFO_BASE 8'hd0
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`define HOST_SLAVE_CONTROL_BASE 8'he0
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`define ADDRESS_DECODE_MASK 8'hf0
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//FifoAddresses
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`define FIFO_DATA_REG 3'b000
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`define FIFO_STATUS_REG 3'b001
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`define FIFO_DATA_COUNT_MSB 3'b010
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`define FIFO_DATA_COUNT_LSB 3'b011
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`define FIFO_CONTROL_REG 3'b100
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`endif //wishBoneBus_h_vdefined
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