URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Blame information for rev 643

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_alu.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Defines added, flags are corrected. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, alu_op2, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        ovforw, ov_we,
        cyforw, cy_we, carry, flag
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
output                          ovforw;
output                          ov_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              extended;
reg     [width-1:0]              result_cust5;
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cyforw;
reg                             cy_we;
reg                             ovforw;
reg                             ov_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
wire                            a_eq_b;
wire                            a_lt_b;
wire    [width-1:0]              result_sum;
wire    [width-1:0]              result_and;
wire                            cy_sum;
`ifdef OR1200_IMPL_SUB
wire                            cy_sub;
`endif
wire                            ov_sum;
wire    [width-1:0]              carry_in;
 
wire    [width-1:0]              b_mux;
 
 
 
//
// Combinatorial logic
//
 
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`ifdef OR1200_IMPL_ALU_COMP3
assign a_eq_b = !(|result_sum);
// signed compare when comp_op[3] is set
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
                              (!a[width-1] & !b[width-1] & result_sum[width-1])|
                              (a[width-1] & b[width-1] & result_sum[width-1])):
// a < b if (a - b) subtraction wrapped and a[width-1] wasn't set
                (result_sum[width-1] & !a[width-1]) |
// or if (a - b) wrapped and both a[width-1] and b[width-1] were set
                (result_sum[width-1] & a[width-1] & b[width-1] );
`endif
 
`ifdef OR1200_IMPL_SUB
 `ifdef OR1200_IMPL_ALU_COMP3
assign cy_sub = a_lt_b;
 `else
assign cy_sub = (comp_a < comp_b);
 `endif
`endif
 
`ifdef OR1200_IMPL_ADDC
assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
                  {{width-1{1'b0}},carry} : {width{1'b0}};
`else
assign carry_in = {width-1{1'b0}};
`endif
 
`ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
                (~b)+1 : b;
`else
assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
`endif
`else // ! `ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
`else
assign b_mux = b;
`endif
`endif
assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
// Numbers either both +ve and bit 31 of result set
assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
// or both -ve and bit 31 of result clear
                ((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
         or shifted_rotated or mult_mac_result or flag or result_cust5 or carry
`ifdef OR1200_IMPL_ALU_EXT
         or extended
`endif
) begin
`ifdef OR1200_CASE_DEFAULT
        casez (alu_op)          // synopsys parallel_case
`else
        casez (alu_op)          // synopsys full_case parallel_case
`endif
`ifdef OR1200_IMPL_ALU_FFL1
                `OR1200_ALUOP_FFL1: begin
`ifdef OR1200_CASE_DEFAULT
                   casez (alu_op2) // synopsys parallel_case
`else
                   casez (alu_op2) // synopsys full_case parallel_case
`endif
                     0: begin // FF1
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
                     end
                     default: begin // FL1
                        result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
                     end
                   endcase // casez (alu_op2)
                end // case: `OR1200_ALUOP_FFL1
`endif //  `ifdef OR1200_IMPL_ALU_FFL1
`ifdef OR1200_IMPL_ALU_CUST5
 
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5;
                end
`endif
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC,
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB,
`endif
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
`ifdef OR1200_IMPL_ALU_EXT
                `OR1200_ALUOP_EXTHB  : begin
                                result = extended;
                end
                `OR1200_ALUOP_EXTW  : begin
                                result = extended;
                end
`endif
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL,
                `OR1200_ALUOP_MULU : begin
                                result = mult_mac_result;
                end
`endif
                `OR1200_ALUOP_CMOV: begin
                        result = flag ? a : b;
                end
 
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
`endif
                        result=result_and;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp
) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC,
`endif
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                end
                default: begin
                        flagforw = flagcomp;
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_SUB
        or cy_sub
`endif
`endif
) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC,
`endif
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB: begin
                        cyforw = cy_sub;
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                        cy_we = 1'b0;
                end
        endcase
end
 
 
//
// Generate SR[OV] write enable
//
always @(alu_op or ov_sum) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_OV
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC,
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB,
`endif
                `OR1200_ALUOP_ADD : begin
                        ovforw = ov_sum;
                        ov_we = 1'b1;
                end
`endif
                default: begin
                        ovforw = 1'b0;
                        ov_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(alu_op2 or a or b) begin
        case (alu_op2)          // synopsys parallel_case
          `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
          `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
          `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
                                                  (a >> b[4:0]);
`endif
          default:
                                shifted_rotated = ({32{a[31]}} <<
                                                   (6'd32-{1'b0, b[4:0]})) |
                                                  a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif //  `ifdef OR1200_IMPL_ALU_COMP2
 
`ifdef OR1200_IMPL_ALU_COMP3
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
 
`ifdef OR1200_IMPL_ALU_EXT
   always @(alu_op or alu_op2 or a) begin
      casez (alu_op2)
        `OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
        `OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
        `OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
        `OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
        default: extended = a; // Used for l.extw instructions
      endcase // casez (alu_op2)
   end
`endif
 
 
//
// l.cust5 custom instructions
//
`ifdef OR1200_IMPL_ALU_CUST5
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casez (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casez (cust5_limm[1:0])
                          2'h0: result_cust5 = {a[31:8], b[7:0]};
                          2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                          2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                          2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end // always @ (cust5_op or cust5_limm or a or b)
`endif
 
endmodule

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Log: or1200_alu.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Minor update:`
47			`// Defines added, flags are corrected.`
48
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_alu(`
55			`a, b, mult_mac_result, macrc_op,`
56	499	julius	`alu_op, alu_op2, comp_op,`
57	350	julius	`cust5_op, cust5_limm,`
58			`result, flagforw, flag_we,`
59	502	julius	`ovforw, ov_we,`
60	350	julius	`cyforw, cy_we, carry, flag`
61			`);`
62
63			parameter width = `OR1200_OPERAND_WIDTH;
64
65			`//`
66			`// I/O`
67			`//`
68			`input [width-1:0] a;`
69			`input [width-1:0] b;`
70			`input [width-1:0] mult_mac_result;`
71			`input macrc_op;`
72			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
73	403	julius	input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
74	350	julius	input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
75			`input [4:0] cust5_op;`
76			`input [5:0] cust5_limm;`
77			`output [width-1:0] result;`
78			`output flagforw;`
79			`output flag_we;`
80			`output cyforw;`
81			`output cy_we;`
82	502	julius	`output ovforw;`
83			`output ov_we;`
84	350	julius	`input carry;`
85			`input flag;`
86
87			`//`
88			`// Internal wires and regs`
89			`//`
90			`reg [width-1:0] result;`
91			`reg [width-1:0] shifted_rotated;`
92	499	julius	`reg [width-1:0] extended;`
93	350	julius	`reg [width-1:0] result_cust5;`
94			`reg flagforw;`
95			`reg flagcomp;`
96			`reg flag_we;`
97	502	julius	`reg cyforw;`
98	350	julius	`reg cy_we;`
99	502	julius	`reg ovforw;`
100			`reg ov_we;`
101	350	julius	`wire [width-1:0] comp_a;`
102			`wire [width-1:0] comp_b;`
103			`wire a_eq_b;`
104			`wire a_lt_b;`
105			`wire [width-1:0] result_sum;`
106			`wire [width-1:0] result_and;`
107			`wire cy_sum;`
108			`ifdef OR1200_IMPL_SUB
109			`wire cy_sub;`
110			`endif
111	502	julius	`wire ov_sum;`
112			`wire [width-1:0] carry_in;`
113	350	julius
114	502	julius	`wire [width-1:0] b_mux;`
115
116
117
118	350	julius	`//`
119			`// Combinatorial logic`
120			`//`
121	504	julius
122	350	julius	`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
123			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
124			`ifdef OR1200_IMPL_ALU_COMP1
125			`assign a_eq_b = (comp_a == comp_b);`
126			`assign a_lt_b = (comp_a < comp_b);`
127			`endif
128	504	julius	`ifdef OR1200_IMPL_ALU_COMP3
129			`assign a_eq_b = !(\|result_sum);`
130	619	julius	`// signed compare when comp_op[3] is set`
131	504	julius	`assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) \|`
132			`(!a[width-1] & !b[width-1] & result_sum[width-1])\|`
133			`(a[width-1] & b[width-1] & result_sum[width-1])):`
134	619	julius	`// a < b if (a - b) subtraction wrapped and a[width-1] wasn't set`
135			`(result_sum[width-1] & !a[width-1]) \|`
136			`// or if (a - b) wrapped and both a[width-1] and b[width-1] were set`
137			`(result_sum[width-1] & a[width-1] & b[width-1] );`
138	504	julius	`endif
139
140	350	julius	`ifdef OR1200_IMPL_SUB
141	504	julius	`ifdef OR1200_IMPL_ALU_COMP3
142			`assign cy_sub = a_lt_b;`
143			`else
144	502	julius	`assign cy_sub = (comp_a < comp_b);`
145	504	julius	`endif
146	350	julius	`endif
147	504	julius
148	502	julius	`ifdef OR1200_IMPL_ADDC
149			assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
150			`{{width-1{1'b0}},carry} : {width{1'b0}};`
151			`else
152			`assign carry_in = {width-1{1'b0}};`
153	350	julius	`endif
154	504	julius
155			`ifdef OR1200_IMPL_ALU_COMP3
156	502	julius	`ifdef OR1200_IMPL_SUB
157	504	julius	assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) \| (alu_op==`OR1200_ALUOP_COMP)) ?
158			`(~b)+1 : b;`
159			`else
160			assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
161			`endif
162			`else // ! `ifdef OR1200_IMPL_ALU_COMP3
163			`ifdef OR1200_IMPL_SUB
164	502	julius	assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
165			`else
166			`assign b_mux = b;`
167	504	julius	`endif
168			`endif
169	502	julius	`assign {cy_sum, result_sum} = (a + b_mux) + carry_in;`
170			`// Numbers either both +ve and bit 31 of result set`
171			`assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) \|`
172			`// or both -ve and bit 31 of result clear`
173			`((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);`
174	350	julius	`assign result_and = a & b;`
175
176			`//`
177			`// Simulation check for bad ALU behavior`
178			`//`
179			`ifdef OR1200_WARNINGS
180			`// synopsys translate_off`
181			`always @(result) begin`
182			`if (result === 32'bx)`
183			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
184			`end`
185			`// synopsys translate_on`
186			`endif
187
188			`//`
189			`// Central part of the ALU`
190			`//`
191	403	julius	`always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op`
192			`or shifted_rotated or mult_mac_result or flag or result_cust5 or carry`
193	499	julius	`ifdef OR1200_IMPL_ALU_EXT
194			`or extended`
195			`endif
196	350	julius	`) begin`
197			`ifdef OR1200_CASE_DEFAULT
198	363	julius	`casez (alu_op) // synopsys parallel_case`
199	350	julius	`else
200	363	julius	`casez (alu_op) // synopsys full_case parallel_case`
201	350	julius	`endif
202	403	julius	`ifdef OR1200_IMPL_ALU_FFL1
203			`OR1200_ALUOP_FFL1: begin
204			`ifdef OR1200_CASE_DEFAULT
205			`casez (alu_op2) // synopsys parallel_case`
206			`else
207			`casez (alu_op2) // synopsys full_case parallel_case`
208			`endif
209			`0: begin // FF1`
210	350	julius	`result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;`
211	403	julius	`end`
212			`default: begin // FL1`
213			`result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;`
214			`end`
215			`endcase // casez (alu_op2)`
216			end // case: `OR1200_ALUOP_FFL1
217	499	julius	`endif // `ifdef OR1200_IMPL_ALU_FFL1
218			`ifdef OR1200_IMPL_ALU_CUST5
219
220	350	julius	`OR1200_ALUOP_CUST5 : begin
221			`result = result_cust5;`
222			`end`
223	499	julius	`endif
224	350	julius	`OR1200_ALUOP_SHROT : begin
225			`result = shifted_rotated;`
226			`end`
227			`ifdef OR1200_IMPL_ADDC
228	502	julius	`OR1200_ALUOP_ADDC,
229	350	julius	`endif
230			`ifdef OR1200_IMPL_SUB
231	502	julius	`OR1200_ALUOP_SUB,
232			`endif
233			`OR1200_ALUOP_ADD : begin
234			`result = result_sum;`
235	350	julius	`end`
236			`OR1200_ALUOP_XOR : begin
237			`result = a ^ b;`
238			`end`
239			`OR1200_ALUOP_OR : begin
240			`result = a \| b;`
241			`end`
242	499	julius	`ifdef OR1200_IMPL_ALU_EXT
243			`OR1200_ALUOP_EXTHB : begin
244			`result = extended;`
245			`end`
246			`OR1200_ALUOP_EXTW : begin
247			`result = extended;`
248			`end`
249			`endif
250	350	julius	`OR1200_ALUOP_MOVHI : begin
251			`if (macrc_op) begin`
252			`result = mult_mac_result;`
253			`end`
254			`else begin`
255			`result = b << 16;`
256			`end`
257			`end`
258			`ifdef OR1200_MULT_IMPLEMENTED
259			`ifdef OR1200_DIV_IMPLEMENTED
260			`OR1200_ALUOP_DIV,
261			`OR1200_ALUOP_DIVU,
262			`endif
263	435	julius	`OR1200_ALUOP_MUL,
264			`OR1200_ALUOP_MULU : begin
265	350	julius	`result = mult_mac_result;`
266			`end`
267			`endif
268			`OR1200_ALUOP_CMOV: begin
269			`result = flag ? a : b;`
270			`end`
271
272			`ifdef OR1200_CASE_DEFAULT
273			`default: begin`
274			`else
275			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
276			`endif
277			`result=result_and;`
278			`end`
279			`endcase`
280			`end`
281
282			`//`
283			`// Generate flag and flag write enable`
284			`//`
285			`always @(alu_op or result_sum or result_and or flagcomp`
286			`) begin`
287	363	julius	`casez (alu_op) // synopsys parallel_case`
288	350	julius	`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
289	502	julius	`ifdef OR1200_IMPL_ADDC
290			`OR1200_ALUOP_ADDC,
291			`endif
292	350	julius	`OR1200_ALUOP_ADD : begin
293			`flagforw = (result_sum == 32'h0000_0000);`
294			`flag_we = 1'b1;`
295			`end`
296			`OR1200_ALUOP_AND: begin
297			`flagforw = (result_and == 32'h0000_0000);`
298			`flag_we = 1'b1;`
299			`end`
300			`endif
301			`OR1200_ALUOP_COMP: begin
302			`flagforw = flagcomp;`
303			`flag_we = 1'b1;`
304			`end`
305			`default: begin`
306			`flagforw = flagcomp;`
307			`flag_we = 1'b0;`
308			`end`
309			`endcase`
310			`end`
311
312			`//`
313			`// Generate SR[CY] write enable`
314			`//`
315			`always @(alu_op or cy_sum`
316			`ifdef OR1200_IMPL_CY
317			`ifdef OR1200_IMPL_SUB
318			`or cy_sub`
319			`endif
320			`endif
321			`) begin`
322	363	julius	`casez (alu_op) // synopsys parallel_case`
323	350	julius	`ifdef OR1200_IMPL_CY
324	502	julius	`ifdef OR1200_IMPL_ADDC
325			`OR1200_ALUOP_ADDC,
326			`endif
327	350	julius	`OR1200_ALUOP_ADD : begin
328			`cyforw = cy_sum;`
329			`cy_we = 1'b1;`
330			`end`
331			`ifdef OR1200_IMPL_SUB
332			`OR1200_ALUOP_SUB: begin
333			`cyforw = cy_sub;`
334			`cy_we = 1'b1;`
335			`end`
336			`endif
337			`endif
338			`default: begin`
339			`cyforw = 1'b0;`
340			`cy_we = 1'b0;`
341			`end`
342			`endcase`
343			`end`
344
345	502	julius
346	350	julius	`//`
347	502	julius	`// Generate SR[OV] write enable`
348			`//`
349			`always @(alu_op or ov_sum) begin`
350			`casez (alu_op) // synopsys parallel_case`
351			`ifdef OR1200_IMPL_OV
352			`ifdef OR1200_IMPL_ADDC
353			`OR1200_ALUOP_ADDC,
354			`endif
355			`ifdef OR1200_IMPL_SUB
356			`OR1200_ALUOP_SUB,
357			`endif
358			`OR1200_ALUOP_ADD : begin
359			`ovforw = ov_sum;`
360			`ov_we = 1'b1;`
361			`end`
362			`endif
363			`default: begin`
364			`ovforw = 1'b0;`
365			`ov_we = 1'b0;`
366			`end`
367			`endcase`
368			`end`
369
370			`//`
371	350	julius	`// Shifts and rotation`
372			`//`
373	499	julius	`always @(alu_op2 or a or b) begin`
374			`case (alu_op2) // synopsys parallel_case`
375			`OR1200_SHROTOP_SLL :
376	350	julius	`shifted_rotated = (a << b[4:0]);`
377	499	julius	`OR1200_SHROTOP_SRL :
378	350	julius	`shifted_rotated = (a >> b[4:0]);`
379
380			`ifdef OR1200_IMPL_ALU_ROTATE
381	499	julius	`OR1200_SHROTOP_ROR :
382			`shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) \|`
383			`(a >> b[4:0]);`
384	350	julius	`endif
385	499	julius	`default:`
386			`shifted_rotated = ({32{a[31]}} <<`
387			`(6'd32-{1'b0, b[4:0]})) \|`
388			`a >> b[4:0];`
389	350	julius	`endcase`
390			`end`
391
392			`//`
393			`// First type of compare implementation`
394			`//`
395			`ifdef OR1200_IMPL_ALU_COMP1
396			`always @(comp_op or a_eq_b or a_lt_b) begin`
397			`case(comp_op[2:0]) // synopsys parallel_case`
398			`OR1200_COP_SFEQ:
399			`flagcomp = a_eq_b;`
400			`OR1200_COP_SFNE:
401			`flagcomp = ~a_eq_b;`
402			`OR1200_COP_SFGT:
403			`flagcomp = ~(a_eq_b \| a_lt_b);`
404			`OR1200_COP_SFGE:
405			`flagcomp = ~a_lt_b;`
406			`OR1200_COP_SFLT:
407			`flagcomp = a_lt_b;`
408			`OR1200_COP_SFLE:
409			`flagcomp = a_eq_b \| a_lt_b;`
410			`default:`
411			`flagcomp = 1'b0;`
412			`endcase`
413			`end`
414			`endif
415
416			`//`
417			`// Second type of compare implementation`
418			`//`
419			`ifdef OR1200_IMPL_ALU_COMP2
420			`always @(comp_op or comp_a or comp_b) begin`
421			`case(comp_op[2:0]) // synopsys parallel_case`
422			`OR1200_COP_SFEQ:
423			`flagcomp = (comp_a == comp_b);`
424			`OR1200_COP_SFNE:
425			`flagcomp = (comp_a != comp_b);`
426			`OR1200_COP_SFGT:
427			`flagcomp = (comp_a > comp_b);`
428			`OR1200_COP_SFGE:
429			`flagcomp = (comp_a >= comp_b);`
430			`OR1200_COP_SFLT:
431			`flagcomp = (comp_a < comp_b);`
432			`OR1200_COP_SFLE:
433			`flagcomp = (comp_a <= comp_b);`
434			`default:`
435			`flagcomp = 1'b0;`
436			`endcase`
437			`end`
438	504	julius	`endif // `ifdef OR1200_IMPL_ALU_COMP2
439
440			`ifdef OR1200_IMPL_ALU_COMP3
441			`always @(comp_op or a_eq_b or a_lt_b) begin`
442			`case(comp_op[2:0]) // synopsys parallel_case`
443			`OR1200_COP_SFEQ:
444			`flagcomp = a_eq_b;`
445			`OR1200_COP_SFNE:
446			`flagcomp = ~a_eq_b;`
447			`OR1200_COP_SFGT:
448			`flagcomp = ~(a_eq_b \| a_lt_b);`
449			`OR1200_COP_SFGE:
450			`flagcomp = ~a_lt_b;`
451			`OR1200_COP_SFLT:
452			`flagcomp = a_lt_b;`
453			`OR1200_COP_SFLE:
454			`flagcomp = a_eq_b \| a_lt_b;`
455			`default:`
456			`flagcomp = 1'b0;`
457			`endcase`
458			`end`
459	350	julius	`endif
460	504	julius
461	350	julius
462	499	julius	`ifdef OR1200_IMPL_ALU_EXT
463			`always @(alu_op or alu_op2 or a) begin`
464			`casez (alu_op2)`
465			`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
466			`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
467			`OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
468			`OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
469			`default: extended = a; // Used for l.extw instructions`
470			`endcase // casez (alu_op2)`
471			`end`
472			`endif
473
474
475			`//`
476			`// l.cust5 custom instructions`
477			`//`
478			`ifdef OR1200_IMPL_ALU_CUST5
479			`// Examples for move byte, set bit and clear bit`
480			`//`
481			`always @(cust5_op or cust5_limm or a or b) begin`
482			`casez (cust5_op) // synopsys parallel_case`
483			`5'h1 : begin`
484			`casez (cust5_limm[1:0])`
485			`2'h0: result_cust5 = {a[31:8], b[7:0]};`
486			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
487			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
488			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
489			`endcase`
490			`end`
491			`5'h2 :`
492			`result_cust5 = a \| (1 << cust5_limm);`
493			`5'h3 :`
494			`result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));`
495			`//`
496			`// * Put here new l.cust5 custom instructions *`
497			`//`
498			`default: begin`
499			`result_cust5 = a;`
500			`end`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Blame information for rev 643