URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Blame information for rev 805

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's ALU                                                ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  ALU                                                         ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_alu.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Defines added, flags are corrected. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_alu(
        a, b, mult_mac_result, macrc_op,
        alu_op, alu_op2, comp_op,
        cust5_op, cust5_limm,
        result, flagforw, flag_we,
        ovforw, ov_we,
        cyforw, cy_we, carry, flag
);
 
parameter width = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
input   [width-1:0]              a;
input   [width-1:0]              b;
input   [width-1:0]              mult_mac_result;
input                           macrc_op;
input   [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
input   [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
input   [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
input   [4:0]                    cust5_op;
input   [5:0]                    cust5_limm;
output  [width-1:0]              result;
output                          flagforw;
output                          flag_we;
output                          cyforw;
output                          cy_we;
output                          ovforw;
output                          ov_we;
input                           carry;
input         flag;
 
//
// Internal wires and regs
//
reg     [width-1:0]              result;
reg     [width-1:0]              shifted_rotated;
reg     [width-1:0]              extended;
`ifdef OR1200_IMPL_ALU_CUST5
reg     [width-1:0]              result_cust5;
`endif
reg                             flagforw;
reg                             flagcomp;
reg                             flag_we;
reg                             cyforw;
reg                             cy_we;
reg                             ovforw;
reg                             ov_we;
wire    [width-1:0]              comp_a;
wire    [width-1:0]              comp_b;
wire                            a_eq_b;
wire                            a_lt_b;
wire    [width-1:0]              result_sum;
wire    [width-1:0]              result_and;
wire                            cy_sum;
`ifdef OR1200_IMPL_SUB
wire                            cy_sub;
`endif
wire                            ov_sum;
wire    [width-1:0]              carry_in;
 
wire    [width-1:0]              b_mux;
 
 
 
//
// Combinatorial logic
//
 
assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};
assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};
`ifdef OR1200_IMPL_ALU_COMP1
assign a_eq_b = (comp_a == comp_b);
assign a_lt_b = (comp_a < comp_b);
`endif
`ifdef OR1200_IMPL_ALU_COMP3
assign a_eq_b = !(|result_sum);
// signed compare when comp_op[3] is set
assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) |
                              (!a[width-1] & !b[width-1] & result_sum[width-1])|
                              (a[width-1] & b[width-1] & result_sum[width-1])):
                (a < b);
 
`endif
 
`ifdef OR1200_IMPL_SUB
 `ifdef OR1200_IMPL_ALU_COMP3
assign cy_sub = a_lt_b;
 `else
assign cy_sub = (comp_a < comp_b);
 `endif
`endif
 
`ifdef OR1200_IMPL_ADDC
assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
                  {{width-1{1'b0}},carry} : {width{1'b0}};
`else
assign carry_in = {width-1{1'b0}};
`endif
 
`ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) | (alu_op==`OR1200_ALUOP_COMP)) ?
                (~b)+1 : b;
`else
assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
`endif
`else // ! `ifdef OR1200_IMPL_ALU_COMP3
`ifdef OR1200_IMPL_SUB
assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
`else
assign b_mux = b;
`endif
`endif
assign {cy_sum, result_sum} = (a + b_mux) + carry_in;
// Numbers either both +ve and bit 31 of result set
assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) |
`ifdef OR1200_IMPL_SUB
                // Subtract larger negative from smaller positive
                ((!a[width-1] & b_mux[width-1]) & result_sum[width-1] &
                 alu_op==`OR1200_ALUOP_SUB) |
`endif
// or both -ve and bit 31 of result clear
                ((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);
assign result_and = a & b;
 
//
// Simulation check for bad ALU behavior
//
`ifdef OR1200_WARNINGS
// synopsys translate_off
always @(result) begin
        if (result === 32'bx)
                $display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);
end
// synopsys translate_on
`endif
 
//
// Central part of the ALU
//
always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op
         or shifted_rotated or mult_mac_result or flag or carry
`ifdef OR1200_IMPL_ALU_EXT
         or extended
`endif
`ifdef OR1200_IMPL_ALU_CUST5
         or result_cust5
`endif
) begin
`ifdef OR1200_CASE_DEFAULT
        casez (alu_op)          // synopsys parallel_case
`else
        casez (alu_op)          // synopsys full_case parallel_case
`endif
`ifdef OR1200_IMPL_ALU_FFL1
                `OR1200_ALUOP_FFL1: begin
`ifdef OR1200_CASE_DEFAULT
                   casez (alu_op2) // synopsys parallel_case
`else
                   casez (alu_op2) // synopsys full_case parallel_case
`endif
                     0: begin // FF1
                        result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;
                     end
                     default: begin // FL1
                        result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;
                     end
                   endcase // casez (alu_op2)
                end // case: `OR1200_ALUOP_FFL1
`endif //  `ifdef OR1200_IMPL_ALU_FFL1
`ifdef OR1200_IMPL_ALU_CUST5
 
                `OR1200_ALUOP_CUST5 : begin
                                result = result_cust5;
                end
`endif
                `OR1200_ALUOP_SHROT : begin
                                result = shifted_rotated;
                end
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC,
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB,
`endif
                `OR1200_ALUOP_ADD : begin
                                result = result_sum;
                end
                `OR1200_ALUOP_XOR : begin
                                result = a ^ b;
                end
                `OR1200_ALUOP_OR  : begin
                                result = a | b;
                end
`ifdef OR1200_IMPL_ALU_EXT
                `OR1200_ALUOP_EXTHB  : begin
                                result = extended;
                end
                `OR1200_ALUOP_EXTW  : begin
                                result = a;
                end
`endif
                `OR1200_ALUOP_MOVHI : begin
                                if (macrc_op) begin
                                        result = mult_mac_result;
                                end
                                else begin
                                        result = b << 16;
                                end
                end
`ifdef OR1200_MULT_IMPLEMENTED
`ifdef OR1200_DIV_IMPLEMENTED
                `OR1200_ALUOP_DIV,
                `OR1200_ALUOP_DIVU,
`endif
                `OR1200_ALUOP_MUL,
                `OR1200_ALUOP_MULU : begin
                                result = mult_mac_result;
                end
`endif
                `OR1200_ALUOP_CMOV: begin
                        result = flag ? a : b;
                end
 
`ifdef OR1200_CASE_DEFAULT
                default: begin
`else
                `OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
`endif
                        result=result_and;
                end
        endcase
end
 
//
// Generate flag and flag write enable
//
always @(alu_op or result_sum or result_and or flagcomp
) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC,
`endif
                `OR1200_ALUOP_ADD : begin
                        flagforw = (result_sum == 32'h0000_0000);
                        flag_we = 1'b1;
                end
                `OR1200_ALUOP_AND: begin
                        flagforw = (result_and == 32'h0000_0000);
                        flag_we = 1'b1;
                end
`endif
                `OR1200_ALUOP_COMP: begin
                        flagforw = flagcomp;
                        flag_we = 1'b1;
                end
                default: begin
                        flagforw = flagcomp;
                        flag_we = 1'b0;
                end
        endcase
end
 
//
// Generate SR[CY] write enable
//
always @(alu_op or cy_sum
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_SUB
        or cy_sub
`endif
`endif
) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_CY
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC,
`endif
                `OR1200_ALUOP_ADD : begin
                        cyforw = cy_sum;
                        cy_we = 1'b1;
                end
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB: begin
                        cyforw = cy_sub;
                        cy_we = 1'b1;
                end
`endif
`endif
                default: begin
                        cyforw = 1'b0;
                        cy_we = 1'b0;
                end
        endcase
end
 
 
//
// Generate SR[OV] write enable
//
always @(alu_op or ov_sum) begin
        casez (alu_op)          // synopsys parallel_case
`ifdef OR1200_IMPL_OV
`ifdef OR1200_IMPL_ADDC
                `OR1200_ALUOP_ADDC,
`endif
`ifdef OR1200_IMPL_SUB
                `OR1200_ALUOP_SUB,
`endif
                `OR1200_ALUOP_ADD : begin
                        ovforw = ov_sum;
                        ov_we = 1'b1;
                end
`endif
                default: begin
                        ovforw = 1'b0;
                        ov_we = 1'b0;
                end
        endcase
end
 
//
// Shifts and rotation
//
always @(alu_op2 or a or b) begin
        case (alu_op2)          // synopsys parallel_case
          `OR1200_SHROTOP_SLL :
                                shifted_rotated = (a << b[4:0]);
          `OR1200_SHROTOP_SRL :
                                shifted_rotated = (a >> b[4:0]);
 
`ifdef OR1200_IMPL_ALU_ROTATE
          `OR1200_SHROTOP_ROR :
                                shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) |
                                                  (a >> b[4:0]);
`endif
          default:
                                shifted_rotated = ({32{a[31]}} <<
                                                   (6'd32-{1'b0, b[4:0]})) |
                                                  a >> b[4:0];
        endcase
end
 
//
// First type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP1
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
//
// Second type of compare implementation
//
`ifdef OR1200_IMPL_ALU_COMP2
always @(comp_op or comp_a or comp_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = (comp_a == comp_b);
                `OR1200_COP_SFNE:
                        flagcomp = (comp_a != comp_b);
                `OR1200_COP_SFGT:
                        flagcomp = (comp_a > comp_b);
                `OR1200_COP_SFGE:
                        flagcomp = (comp_a >= comp_b);
                `OR1200_COP_SFLT:
                        flagcomp = (comp_a < comp_b);
                `OR1200_COP_SFLE:
                        flagcomp = (comp_a <= comp_b);
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif //  `ifdef OR1200_IMPL_ALU_COMP2
 
`ifdef OR1200_IMPL_ALU_COMP3
always @(comp_op or a_eq_b or a_lt_b) begin
        case(comp_op[2:0])       // synopsys parallel_case
                `OR1200_COP_SFEQ:
                        flagcomp = a_eq_b;
                `OR1200_COP_SFNE:
                        flagcomp = ~a_eq_b;
                `OR1200_COP_SFGT:
                        flagcomp = ~(a_eq_b | a_lt_b);
                `OR1200_COP_SFGE:
                        flagcomp = ~a_lt_b;
                `OR1200_COP_SFLT:
                        flagcomp = a_lt_b;
                `OR1200_COP_SFLE:
                        flagcomp = a_eq_b | a_lt_b;
                default:
                        flagcomp = 1'b0;
        endcase
end
`endif
 
 
`ifdef OR1200_IMPL_ALU_EXT
   always @(alu_op or alu_op2 or a) begin
      casez (alu_op2)
        `OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
        `OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
        `OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
        `OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
        default: extended = a; // Used for l.extw instructions
      endcase // casez (alu_op2)
   end
`endif
 
 
//
// l.cust5 custom instructions
//
`ifdef OR1200_IMPL_ALU_CUST5
// Examples for move byte, set bit and clear bit
//
always @(cust5_op or cust5_limm or a or b) begin
        casez (cust5_op)                // synopsys parallel_case
                5'h1 : begin
                        casez (cust5_limm[1:0])
                          2'h0: result_cust5 = {a[31:8], b[7:0]};
                          2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};
                          2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};
                          2'h3: result_cust5 = {b[7:0], a[23:0]};
                        endcase
                end
                5'h2 :
                        result_cust5 = a | (1 << cust5_limm);
                5'h3 :
                        result_cust5 = a & (32'hffffffff ^ (1 << cust5_limm));
//
// *** Put here new l.cust5 custom instructions ***
//
                default: begin
                        result_cust5 = a;
                end
        endcase
end // always @ (cust5_op or cust5_limm or a or b)
`endif
 
endmodule

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's ALU ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// ALU ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Log: or1200_alu.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Minor update:`
47			`// Defines added, flags are corrected.`
48
49			`// synopsys translate_off`
50			`include "timescale.v"
51			`// synopsys translate_on`
52			`include "or1200_defines.v"
53
54			`module or1200_alu(`
55			`a, b, mult_mac_result, macrc_op,`
56	499	julius	`alu_op, alu_op2, comp_op,`
57	350	julius	`cust5_op, cust5_limm,`
58			`result, flagforw, flag_we,`
59	502	julius	`ovforw, ov_we,`
60	350	julius	`cyforw, cy_we, carry, flag`
61			`);`
62
63			parameter width = `OR1200_OPERAND_WIDTH;
64
65			`//`
66			`// I/O`
67			`//`
68			`input [width-1:0] a;`
69			`input [width-1:0] b;`
70			`input [width-1:0] mult_mac_result;`
71			`input macrc_op;`
72			input [`OR1200_ALUOP_WIDTH-1:0] alu_op;
73	403	julius	input [`OR1200_ALUOP2_WIDTH-1:0] alu_op2;
74	350	julius	input [`OR1200_COMPOP_WIDTH-1:0] comp_op;
75			`input [4:0] cust5_op;`
76			`input [5:0] cust5_limm;`
77			`output [width-1:0] result;`
78			`output flagforw;`
79			`output flag_we;`
80			`output cyforw;`
81			`output cy_we;`
82	502	julius	`output ovforw;`
83			`output ov_we;`
84	350	julius	`input carry;`
85			`input flag;`
86
87			`//`
88			`// Internal wires and regs`
89			`//`
90			`reg [width-1:0] result;`
91			`reg [width-1:0] shifted_rotated;`
92	499	julius	`reg [width-1:0] extended;`
93	788	julius	`ifdef OR1200_IMPL_ALU_CUST5
94	350	julius	`reg [width-1:0] result_cust5;`
95	788	julius	`endif
96	350	julius	`reg flagforw;`
97			`reg flagcomp;`
98			`reg flag_we;`
99	502	julius	`reg cyforw;`
100	350	julius	`reg cy_we;`
101	502	julius	`reg ovforw;`
102			`reg ov_we;`
103	350	julius	`wire [width-1:0] comp_a;`
104			`wire [width-1:0] comp_b;`
105			`wire a_eq_b;`
106			`wire a_lt_b;`
107			`wire [width-1:0] result_sum;`
108			`wire [width-1:0] result_and;`
109			`wire cy_sum;`
110			`ifdef OR1200_IMPL_SUB
111			`wire cy_sub;`
112			`endif
113	502	julius	`wire ov_sum;`
114			`wire [width-1:0] carry_in;`
115	350	julius
116	502	julius	`wire [width-1:0] b_mux;`
117
118
119
120	350	julius	`//`
121			`// Combinatorial logic`
122			`//`
123	504	julius
124	350	julius	`assign comp_a = {a[width-1] ^ comp_op[3] , a[width-2:0]};`
125			`assign comp_b = {b[width-1] ^ comp_op[3] , b[width-2:0]};`
126			`ifdef OR1200_IMPL_ALU_COMP1
127			`assign a_eq_b = (comp_a == comp_b);`
128			`assign a_lt_b = (comp_a < comp_b);`
129			`endif
130	504	julius	`ifdef OR1200_IMPL_ALU_COMP3
131			`assign a_eq_b = !(\|result_sum);`
132	619	julius	`// signed compare when comp_op[3] is set`
133	504	julius	`assign a_lt_b = comp_op[3] ? ((a[width-1] & !b[width-1]) \|`
134			`(!a[width-1] & !b[width-1] & result_sum[width-1])\|`
135			`(a[width-1] & b[width-1] & result_sum[width-1])):`
136	672	julius	`(a < b);`
137
138	504	julius	`endif
139
140	350	julius	`ifdef OR1200_IMPL_SUB
141	504	julius	`ifdef OR1200_IMPL_ALU_COMP3
142			`assign cy_sub = a_lt_b;`
143			`else
144	502	julius	`assign cy_sub = (comp_a < comp_b);`
145	504	julius	`endif
146	350	julius	`endif
147	504	julius
148	502	julius	`ifdef OR1200_IMPL_ADDC
149			assign carry_in = (alu_op==`OR1200_ALUOP_ADDC) ?
150			`{{width-1{1'b0}},carry} : {width{1'b0}};`
151			`else
152			`assign carry_in = {width-1{1'b0}};`
153	350	julius	`endif
154	504	julius
155			`ifdef OR1200_IMPL_ALU_COMP3
156	502	julius	`ifdef OR1200_IMPL_SUB
157	504	julius	assign b_mux = ((alu_op==`OR1200_ALUOP_SUB) \| (alu_op==`OR1200_ALUOP_COMP)) ?
158			`(~b)+1 : b;`
159			`else
160			assign b_mux = (alu_op==`OR1200_ALUOP_COMP) ? (~b)+1 : b;
161			`endif
162			`else // ! `ifdef OR1200_IMPL_ALU_COMP3
163			`ifdef OR1200_IMPL_SUB
164	502	julius	assign b_mux = (alu_op==`OR1200_ALUOP_SUB) ? (~b)+1 : b;
165			`else
166			`assign b_mux = b;`
167	504	julius	`endif
168			`endif
169	502	julius	`assign {cy_sum, result_sum} = (a + b_mux) + carry_in;`
170			`// Numbers either both +ve and bit 31 of result set`
171			`assign ov_sum = ((!a[width-1] & !b_mux[width-1]) & result_sum[width-1]) \|`
172	803	julius	`ifdef OR1200_IMPL_SUB
173			`// Subtract larger negative from smaller positive`
174			`((!a[width-1] & b_mux[width-1]) & result_sum[width-1] &`
175			alu_op==`OR1200_ALUOP_SUB) \|
176			`endif
177	502	julius	`// or both -ve and bit 31 of result clear`
178			`((a[width-1] & b_mux[width-1]) & !result_sum[width-1]);`
179	350	julius	`assign result_and = a & b;`
180
181			`//`
182			`// Simulation check for bad ALU behavior`
183			`//`
184			`ifdef OR1200_WARNINGS
185			`// synopsys translate_off`
186			`always @(result) begin`
187			`if (result === 32'bx)`
188			`$display("%t: WARNING: 32'bx detected on ALU result bus. Please check !", $time);`
189			`end`
190			`// synopsys translate_on`
191			`endif
192
193			`//`
194			`// Central part of the ALU`
195			`//`
196	403	julius	`always @(alu_op or alu_op2 or a or b or result_sum or result_and or macrc_op`
197	788	julius	`or shifted_rotated or mult_mac_result or flag or carry`
198	499	julius	`ifdef OR1200_IMPL_ALU_EXT
199			`or extended`
200			`endif
201	788	julius	`ifdef OR1200_IMPL_ALU_CUST5
202			`or result_cust5`
203			`endif
204	350	julius	`) begin`
205			`ifdef OR1200_CASE_DEFAULT
206	363	julius	`casez (alu_op) // synopsys parallel_case`
207	350	julius	`else
208	363	julius	`casez (alu_op) // synopsys full_case parallel_case`
209	350	julius	`endif
210	403	julius	`ifdef OR1200_IMPL_ALU_FFL1
211			`OR1200_ALUOP_FFL1: begin
212			`ifdef OR1200_CASE_DEFAULT
213			`casez (alu_op2) // synopsys parallel_case`
214			`else
215			`casez (alu_op2) // synopsys full_case parallel_case`
216			`endif
217			`0: begin // FF1`
218	350	julius	`result = a[0] ? 1 : a[1] ? 2 : a[2] ? 3 : a[3] ? 4 : a[4] ? 5 : a[5] ? 6 : a[6] ? 7 : a[7] ? 8 : a[8] ? 9 : a[9] ? 10 : a[10] ? 11 : a[11] ? 12 : a[12] ? 13 : a[13] ? 14 : a[14] ? 15 : a[15] ? 16 : a[16] ? 17 : a[17] ? 18 : a[18] ? 19 : a[19] ? 20 : a[20] ? 21 : a[21] ? 22 : a[22] ? 23 : a[23] ? 24 : a[24] ? 25 : a[25] ? 26 : a[26] ? 27 : a[27] ? 28 : a[28] ? 29 : a[29] ? 30 : a[30] ? 31 : a[31] ? 32 : 0;`
219	403	julius	`end`
220			`default: begin // FL1`
221			`result = a[31] ? 32 : a[30] ? 31 : a[29] ? 30 : a[28] ? 29 : a[27] ? 28 : a[26] ? 27 : a[25] ? 26 : a[24] ? 25 : a[23] ? 24 : a[22] ? 23 : a[21] ? 22 : a[20] ? 21 : a[19] ? 20 : a[18] ? 19 : a[17] ? 18 : a[16] ? 17 : a[15] ? 16 : a[14] ? 15 : a[13] ? 14 : a[12] ? 13 : a[11] ? 12 : a[10] ? 11 : a[9] ? 10 : a[8] ? 9 : a[7] ? 8 : a[6] ? 7 : a[5] ? 6 : a[4] ? 5 : a[3] ? 4 : a[2] ? 3 : a[1] ? 2 : a[0] ? 1 : 0 ;`
222			`end`
223			`endcase // casez (alu_op2)`
224			end // case: `OR1200_ALUOP_FFL1
225	499	julius	`endif // `ifdef OR1200_IMPL_ALU_FFL1
226			`ifdef OR1200_IMPL_ALU_CUST5
227
228	350	julius	`OR1200_ALUOP_CUST5 : begin
229			`result = result_cust5;`
230			`end`
231	499	julius	`endif
232	350	julius	`OR1200_ALUOP_SHROT : begin
233			`result = shifted_rotated;`
234			`end`
235			`ifdef OR1200_IMPL_ADDC
236	502	julius	`OR1200_ALUOP_ADDC,
237	350	julius	`endif
238			`ifdef OR1200_IMPL_SUB
239	502	julius	`OR1200_ALUOP_SUB,
240			`endif
241			`OR1200_ALUOP_ADD : begin
242			`result = result_sum;`
243	350	julius	`end`
244			`OR1200_ALUOP_XOR : begin
245			`result = a ^ b;`
246			`end`
247			`OR1200_ALUOP_OR : begin
248			`result = a \| b;`
249			`end`
250	499	julius	`ifdef OR1200_IMPL_ALU_EXT
251			`OR1200_ALUOP_EXTHB : begin
252			`result = extended;`
253			`end`
254			`OR1200_ALUOP_EXTW : begin
255	801	julius	`result = a;`
256	499	julius	`end`
257			`endif
258	350	julius	`OR1200_ALUOP_MOVHI : begin
259			`if (macrc_op) begin`
260			`result = mult_mac_result;`
261			`end`
262			`else begin`
263			`result = b << 16;`
264			`end`
265			`end`
266			`ifdef OR1200_MULT_IMPLEMENTED
267			`ifdef OR1200_DIV_IMPLEMENTED
268			`OR1200_ALUOP_DIV,
269			`OR1200_ALUOP_DIVU,
270			`endif
271	435	julius	`OR1200_ALUOP_MUL,
272			`OR1200_ALUOP_MULU : begin
273	350	julius	`result = mult_mac_result;`
274			`end`
275			`endif
276			`OR1200_ALUOP_CMOV: begin
277			`result = flag ? a : b;`
278			`end`
279
280			`ifdef OR1200_CASE_DEFAULT
281			`default: begin`
282			`else
283			`OR1200_ALUOP_COMP, `OR1200_ALUOP_AND: begin
284			`endif
285			`result=result_and;`
286			`end`
287			`endcase`
288			`end`
289
290			`//`
291			`// Generate flag and flag write enable`
292			`//`
293			`always @(alu_op or result_sum or result_and or flagcomp`
294			`) begin`
295	363	julius	`casez (alu_op) // synopsys parallel_case`
296	350	julius	`ifdef OR1200_ADDITIONAL_FLAG_MODIFIERS
297	502	julius	`ifdef OR1200_IMPL_ADDC
298			`OR1200_ALUOP_ADDC,
299			`endif
300	350	julius	`OR1200_ALUOP_ADD : begin
301			`flagforw = (result_sum == 32'h0000_0000);`
302			`flag_we = 1'b1;`
303			`end`
304			`OR1200_ALUOP_AND: begin
305			`flagforw = (result_and == 32'h0000_0000);`
306			`flag_we = 1'b1;`
307			`end`
308			`endif
309			`OR1200_ALUOP_COMP: begin
310			`flagforw = flagcomp;`
311			`flag_we = 1'b1;`
312			`end`
313			`default: begin`
314			`flagforw = flagcomp;`
315			`flag_we = 1'b0;`
316			`end`
317			`endcase`
318			`end`
319
320			`//`
321			`// Generate SR[CY] write enable`
322			`//`
323			`always @(alu_op or cy_sum`
324			`ifdef OR1200_IMPL_CY
325			`ifdef OR1200_IMPL_SUB
326			`or cy_sub`
327			`endif
328			`endif
329			`) begin`
330	363	julius	`casez (alu_op) // synopsys parallel_case`
331	350	julius	`ifdef OR1200_IMPL_CY
332	502	julius	`ifdef OR1200_IMPL_ADDC
333			`OR1200_ALUOP_ADDC,
334			`endif
335	350	julius	`OR1200_ALUOP_ADD : begin
336			`cyforw = cy_sum;`
337			`cy_we = 1'b1;`
338			`end`
339			`ifdef OR1200_IMPL_SUB
340			`OR1200_ALUOP_SUB: begin
341			`cyforw = cy_sub;`
342			`cy_we = 1'b1;`
343			`end`
344			`endif
345			`endif
346			`default: begin`
347			`cyforw = 1'b0;`
348			`cy_we = 1'b0;`
349			`end`
350			`endcase`
351			`end`
352
353	502	julius
354	350	julius	`//`
355	502	julius	`// Generate SR[OV] write enable`
356			`//`
357			`always @(alu_op or ov_sum) begin`
358			`casez (alu_op) // synopsys parallel_case`
359			`ifdef OR1200_IMPL_OV
360			`ifdef OR1200_IMPL_ADDC
361			`OR1200_ALUOP_ADDC,
362			`endif
363			`ifdef OR1200_IMPL_SUB
364			`OR1200_ALUOP_SUB,
365			`endif
366			`OR1200_ALUOP_ADD : begin
367			`ovforw = ov_sum;`
368			`ov_we = 1'b1;`
369			`end`
370			`endif
371			`default: begin`
372			`ovforw = 1'b0;`
373			`ov_we = 1'b0;`
374			`end`
375			`endcase`
376			`end`
377
378			`//`
379	350	julius	`// Shifts and rotation`
380			`//`
381	499	julius	`always @(alu_op2 or a or b) begin`
382			`case (alu_op2) // synopsys parallel_case`
383			`OR1200_SHROTOP_SLL :
384	350	julius	`shifted_rotated = (a << b[4:0]);`
385	499	julius	`OR1200_SHROTOP_SRL :
386	350	julius	`shifted_rotated = (a >> b[4:0]);`
387
388			`ifdef OR1200_IMPL_ALU_ROTATE
389	499	julius	`OR1200_SHROTOP_ROR :
390			`shifted_rotated = (a << (6'd32-{1'b0,b[4:0]})) \|`
391			`(a >> b[4:0]);`
392	350	julius	`endif
393	499	julius	`default:`
394			`shifted_rotated = ({32{a[31]}} <<`
395			`(6'd32-{1'b0, b[4:0]})) \|`
396			`a >> b[4:0];`
397	350	julius	`endcase`
398			`end`
399
400			`//`
401			`// First type of compare implementation`
402			`//`
403			`ifdef OR1200_IMPL_ALU_COMP1
404			`always @(comp_op or a_eq_b or a_lt_b) begin`
405			`case(comp_op[2:0]) // synopsys parallel_case`
406			`OR1200_COP_SFEQ:
407			`flagcomp = a_eq_b;`
408			`OR1200_COP_SFNE:
409			`flagcomp = ~a_eq_b;`
410			`OR1200_COP_SFGT:
411			`flagcomp = ~(a_eq_b \| a_lt_b);`
412			`OR1200_COP_SFGE:
413			`flagcomp = ~a_lt_b;`
414			`OR1200_COP_SFLT:
415			`flagcomp = a_lt_b;`
416			`OR1200_COP_SFLE:
417			`flagcomp = a_eq_b \| a_lt_b;`
418			`default:`
419			`flagcomp = 1'b0;`
420			`endcase`
421			`end`
422			`endif
423
424			`//`
425			`// Second type of compare implementation`
426			`//`
427			`ifdef OR1200_IMPL_ALU_COMP2
428			`always @(comp_op or comp_a or comp_b) begin`
429			`case(comp_op[2:0]) // synopsys parallel_case`
430			`OR1200_COP_SFEQ:
431			`flagcomp = (comp_a == comp_b);`
432			`OR1200_COP_SFNE:
433			`flagcomp = (comp_a != comp_b);`
434			`OR1200_COP_SFGT:
435			`flagcomp = (comp_a > comp_b);`
436			`OR1200_COP_SFGE:
437			`flagcomp = (comp_a >= comp_b);`
438			`OR1200_COP_SFLT:
439			`flagcomp = (comp_a < comp_b);`
440			`OR1200_COP_SFLE:
441			`flagcomp = (comp_a <= comp_b);`
442			`default:`
443			`flagcomp = 1'b0;`
444			`endcase`
445			`end`
446	504	julius	`endif // `ifdef OR1200_IMPL_ALU_COMP2
447
448			`ifdef OR1200_IMPL_ALU_COMP3
449			`always @(comp_op or a_eq_b or a_lt_b) begin`
450			`case(comp_op[2:0]) // synopsys parallel_case`
451			`OR1200_COP_SFEQ:
452			`flagcomp = a_eq_b;`
453			`OR1200_COP_SFNE:
454			`flagcomp = ~a_eq_b;`
455			`OR1200_COP_SFGT:
456			`flagcomp = ~(a_eq_b \| a_lt_b);`
457			`OR1200_COP_SFGE:
458			`flagcomp = ~a_lt_b;`
459			`OR1200_COP_SFLT:
460			`flagcomp = a_lt_b;`
461			`OR1200_COP_SFLE:
462			`flagcomp = a_eq_b \| a_lt_b;`
463			`default:`
464			`flagcomp = 1'b0;`
465			`endcase`
466			`end`
467	350	julius	`endif
468	504	julius
469	350	julius
470	499	julius	`ifdef OR1200_IMPL_ALU_EXT
471			`always @(alu_op or alu_op2 or a) begin`
472			`casez (alu_op2)`
473			`OR1200_EXTHBOP_HS : extended = {{16{a[15]}},a[15:0]};
474			`OR1200_EXTHBOP_BS : extended = {{24{a[7]}},a[7:0]};
475			`OR1200_EXTHBOP_HZ : extended = {16'd0,a[15:0]};
476			`OR1200_EXTHBOP_BZ : extended = {24'd0,a[7:0]};
477			`default: extended = a; // Used for l.extw instructions`
478			`endcase // casez (alu_op2)`
479			`end`
480			`endif
481
482
483			`//`
484			`// l.cust5 custom instructions`
485			`//`
486			`ifdef OR1200_IMPL_ALU_CUST5
487			`// Examples for move byte, set bit and clear bit`
488			`//`
489			`always @(cust5_op or cust5_limm or a or b) begin`
490			`casez (cust5_op) // synopsys parallel_case`
491			`5'h1 : begin`
492			`casez (cust5_limm[1:0])`
493			`2'h0: result_cust5 = {a[31:8], b[7:0]};`
494			`2'h1: result_cust5 = {a[31:16], b[7:0], a[7:0]};`
495			`2'h2: result_cust5 = {a[31:24], b[7:0], a[15:0]};`
496			`2'h3: result_cust5 = {b[7:0], a[23:0]};`
497			`endcase`
498			`end`
499			`5'h2 :`
500			`result_cust5 = a \| (1 << cust5_limm);`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_alu.v] - Blame information for rev 805