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julius |
//////////////////////////////////////////////////////////////////////
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//// ////
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//// OR1200's VR, UPR and Configuration Registers ////
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//// ////
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//// This file is part of the OpenRISC 1200 project ////
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//// http://www.opencores.org/project,or1k ////
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//// ////
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//// Description ////
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//// According to OR1K architectural and OR1200 specifications. ////
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//// ////
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//// To Do: ////
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//// - done ////
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//// ////
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//// Author(s): ////
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//// - Damjan Lampret, lampret@opencores.org ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// $Log: or1200_cfgr.v,v $
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// Revision 2.0 2010/06/30 11:00:00 ORSoC
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// No update
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_cfgr(
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// RISC Internal Interface
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spr_addr, spr_dat_o
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);
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//
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// RISC Internal Interface
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//
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input [31:0] spr_addr; // SPR Address
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output [31:0] spr_dat_o; // SPR Read Data
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//
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// Internal wires & registers
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//
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reg [31:0] spr_dat_o; // SPR Read Data
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`ifdef OR1200_CFGR_IMPLEMENTED
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//
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// Implementation of VR, UPR and configuration registers
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//
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always @(spr_addr)
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`ifdef OR1200_SYS_FULL_DECODE
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if (~|spr_addr[31:4])
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`endif
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case(spr_addr[3:0]) // synopsys parallel_case
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`OR1200_SPRGRP_SYS_VR: begin
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spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV;
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spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1;
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spr_dat_o[`OR1200_VR_CFG_BITS] = `OR1200_VR_CFG;
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spr_dat_o[`OR1200_VR_VER_BITS] = `OR1200_VR_VER;
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end
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`OR1200_SPRGRP_SYS_UPR: begin
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spr_dat_o[`OR1200_UPR_UP_BITS] = `OR1200_UPR_UP;
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spr_dat_o[`OR1200_UPR_DCP_BITS] = `OR1200_UPR_DCP;
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spr_dat_o[`OR1200_UPR_ICP_BITS] = `OR1200_UPR_ICP;
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spr_dat_o[`OR1200_UPR_DMP_BITS] = `OR1200_UPR_DMP;
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spr_dat_o[`OR1200_UPR_IMP_BITS] = `OR1200_UPR_IMP;
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spr_dat_o[`OR1200_UPR_MP_BITS] = `OR1200_UPR_MP;
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spr_dat_o[`OR1200_UPR_DUP_BITS] = `OR1200_UPR_DUP;
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spr_dat_o[`OR1200_UPR_PCUP_BITS] = `OR1200_UPR_PCUP;
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spr_dat_o[`OR1200_UPR_PMP_BITS] = `OR1200_UPR_PMP;
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spr_dat_o[`OR1200_UPR_PICP_BITS] = `OR1200_UPR_PICP;
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spr_dat_o[`OR1200_UPR_TTP_BITS] = `OR1200_UPR_TTP;
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spr_dat_o[`OR1200_UPR_FPP_BITS] = `OR1200_UPR_FPP;
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spr_dat_o[`OR1200_UPR_RES1_BITS] = `OR1200_UPR_RES1;
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spr_dat_o[`OR1200_UPR_CUP_BITS] = `OR1200_UPR_CUP;
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end
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`OR1200_SPRGRP_SYS_CPUCFGR: begin
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spr_dat_o[`OR1200_CPUCFGR_NSGF_BITS] = `OR1200_CPUCFGR_NSGF;
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spr_dat_o[`OR1200_CPUCFGR_HGF_BITS] = `OR1200_CPUCFGR_HGF;
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spr_dat_o[`OR1200_CPUCFGR_OB32S_BITS] = `OR1200_CPUCFGR_OB32S;
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spr_dat_o[`OR1200_CPUCFGR_OB64S_BITS] = `OR1200_CPUCFGR_OB64S;
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spr_dat_o[`OR1200_CPUCFGR_OF32S_BITS] = `OR1200_CPUCFGR_OF32S;
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spr_dat_o[`OR1200_CPUCFGR_OF64S_BITS] = `OR1200_CPUCFGR_OF64S;
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spr_dat_o[`OR1200_CPUCFGR_OV64S_BITS] = `OR1200_CPUCFGR_OV64S;
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spr_dat_o[`OR1200_CPUCFGR_RES1_BITS] = `OR1200_CPUCFGR_RES1;
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end
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`OR1200_SPRGRP_SYS_DMMUCFGR: begin
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spr_dat_o[`OR1200_DMMUCFGR_NTW_BITS] = `OR1200_DMMUCFGR_NTW;
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spr_dat_o[`OR1200_DMMUCFGR_NTS_BITS] = `OR1200_DMMUCFGR_NTS;
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spr_dat_o[`OR1200_DMMUCFGR_NAE_BITS] = `OR1200_DMMUCFGR_NAE;
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spr_dat_o[`OR1200_DMMUCFGR_CRI_BITS] = `OR1200_DMMUCFGR_CRI;
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spr_dat_o[`OR1200_DMMUCFGR_PRI_BITS] = `OR1200_DMMUCFGR_PRI;
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spr_dat_o[`OR1200_DMMUCFGR_TEIRI_BITS] = `OR1200_DMMUCFGR_TEIRI;
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spr_dat_o[`OR1200_DMMUCFGR_HTR_BITS] = `OR1200_DMMUCFGR_HTR;
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spr_dat_o[`OR1200_DMMUCFGR_RES1_BITS] = `OR1200_DMMUCFGR_RES1;
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end
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`OR1200_SPRGRP_SYS_IMMUCFGR: begin
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spr_dat_o[`OR1200_IMMUCFGR_NTW_BITS] = `OR1200_IMMUCFGR_NTW;
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spr_dat_o[`OR1200_IMMUCFGR_NTS_BITS] = `OR1200_IMMUCFGR_NTS;
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spr_dat_o[`OR1200_IMMUCFGR_NAE_BITS] = `OR1200_IMMUCFGR_NAE;
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spr_dat_o[`OR1200_IMMUCFGR_CRI_BITS] = `OR1200_IMMUCFGR_CRI;
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spr_dat_o[`OR1200_IMMUCFGR_PRI_BITS] = `OR1200_IMMUCFGR_PRI;
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spr_dat_o[`OR1200_IMMUCFGR_TEIRI_BITS] = `OR1200_IMMUCFGR_TEIRI;
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spr_dat_o[`OR1200_IMMUCFGR_HTR_BITS] = `OR1200_IMMUCFGR_HTR;
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spr_dat_o[`OR1200_IMMUCFGR_RES1_BITS] = `OR1200_IMMUCFGR_RES1;
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end
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`OR1200_SPRGRP_SYS_DCCFGR: begin
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spr_dat_o[`OR1200_DCCFGR_NCW_BITS] = `OR1200_DCCFGR_NCW;
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spr_dat_o[`OR1200_DCCFGR_NCS_BITS] = `OR1200_DCCFGR_NCS;
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spr_dat_o[`OR1200_DCCFGR_CBS_BITS] = `OR1200_DCCFGR_CBS;
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spr_dat_o[`OR1200_DCCFGR_CWS_BITS] = `OR1200_DCCFGR_CWS;
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spr_dat_o[`OR1200_DCCFGR_CCRI_BITS] = `OR1200_DCCFGR_CCRI;
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spr_dat_o[`OR1200_DCCFGR_CBIRI_BITS] = `OR1200_DCCFGR_CBIRI;
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spr_dat_o[`OR1200_DCCFGR_CBPRI_BITS] = `OR1200_DCCFGR_CBPRI;
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spr_dat_o[`OR1200_DCCFGR_CBLRI_BITS] = `OR1200_DCCFGR_CBLRI;
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spr_dat_o[`OR1200_DCCFGR_CBFRI_BITS] = `OR1200_DCCFGR_CBFRI;
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spr_dat_o[`OR1200_DCCFGR_CBWBRI_BITS] = `OR1200_DCCFGR_CBWBRI;
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spr_dat_o[`OR1200_DCCFGR_RES1_BITS] = `OR1200_DCCFGR_RES1;
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end
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`OR1200_SPRGRP_SYS_ICCFGR: begin
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spr_dat_o[`OR1200_ICCFGR_NCW_BITS] = `OR1200_ICCFGR_NCW;
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spr_dat_o[`OR1200_ICCFGR_NCS_BITS] = `OR1200_ICCFGR_NCS;
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spr_dat_o[`OR1200_ICCFGR_CBS_BITS] = `OR1200_ICCFGR_CBS;
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spr_dat_o[`OR1200_ICCFGR_CWS_BITS] = `OR1200_ICCFGR_CWS;
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spr_dat_o[`OR1200_ICCFGR_CCRI_BITS] = `OR1200_ICCFGR_CCRI;
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spr_dat_o[`OR1200_ICCFGR_CBIRI_BITS] = `OR1200_ICCFGR_CBIRI;
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spr_dat_o[`OR1200_ICCFGR_CBPRI_BITS] = `OR1200_ICCFGR_CBPRI;
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spr_dat_o[`OR1200_ICCFGR_CBLRI_BITS] = `OR1200_ICCFGR_CBLRI;
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spr_dat_o[`OR1200_ICCFGR_CBFRI_BITS] = `OR1200_ICCFGR_CBFRI;
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spr_dat_o[`OR1200_ICCFGR_CBWBRI_BITS] = `OR1200_ICCFGR_CBWBRI;
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spr_dat_o[`OR1200_ICCFGR_RES1_BITS] = `OR1200_ICCFGR_RES1;
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end
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`OR1200_SPRGRP_SYS_DCFGR: begin
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spr_dat_o[`OR1200_DCFGR_NDP_BITS] = `OR1200_DCFGR_NDP;
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spr_dat_o[`OR1200_DCFGR_WPCI_BITS] = `OR1200_DCFGR_WPCI;
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spr_dat_o[`OR1200_DCFGR_RES1_BITS] = `OR1200_DCFGR_RES1;
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end
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default: spr_dat_o = 32'h0000_0000;
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endcase
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`ifdef OR1200_SYS_FULL_DECODE
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else
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spr_dat_o = 32'h0000_0000;
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`endif
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`else
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//
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// When configuration registers are not implemented, only
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// implement VR and UPR
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//
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always @(spr_addr)
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`ifdef OR1200_SYS_FULL_DECODE
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if (spr_addr[31:4] == 28'h0)
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`endif
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case(spr_addr[3:0])
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`OR1200_SPRGRP_SYS_VR: begin
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spr_dat_o[`OR1200_VR_REV_BITS] = `OR1200_VR_REV;
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spr_dat_o[`OR1200_VR_RES1_BITS] = `OR1200_VR_RES1;
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spr_dat_o[`OR1200_VR_CFG_BITS] = `OR1200_VR_CFG;
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spr_dat_o[`OR1200_VR_VER_BITS] = `OR1200_VR_VER;
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end
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`OR1200_SPRGRP_SYS_UPR: begin
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spr_dat_o[`OR1200_UPR_UP_BITS] = `OR1200_UPR_UP;
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spr_dat_o[`OR1200_UPR_DCP_BITS] = `OR1200_UPR_DCP;
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spr_dat_o[`OR1200_UPR_ICP_BITS] = `OR1200_UPR_ICP;
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spr_dat_o[`OR1200_UPR_DMP_BITS] = `OR1200_UPR_DMP;
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spr_dat_o[`OR1200_UPR_IMP_BITS] = `OR1200_UPR_IMP;
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spr_dat_o[`OR1200_UPR_MP_BITS] = `OR1200_UPR_MP;
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spr_dat_o[`OR1200_UPR_DUP_BITS] = `OR1200_UPR_DUP;
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spr_dat_o[`OR1200_UPR_PCUP_BITS] = `OR1200_UPR_PCUP;
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spr_dat_o[`OR1200_UPR_PMP_BITS] = `OR1200_UPR_PMP;
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spr_dat_o[`OR1200_UPR_PICP_BITS] = `OR1200_UPR_PICP;
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spr_dat_o[`OR1200_UPR_TTP_BITS] = `OR1200_UPR_TTP;
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spr_dat_o[`OR1200_UPR_RES1_BITS] = `OR1200_UPR_RES1;
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spr_dat_o[`OR1200_UPR_CUP_BITS] = `OR1200_UPR_CUP;
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end
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default: spr_dat_o = 32'h0000_0000;
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endcase
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`ifdef OR1200_SYS_FULL_DECODE
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else
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spr_dat_o = 32'h0000_0000;
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`endif
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`endif
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endmodule
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