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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_cpu.v] - Blame information for rev 499

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1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's CPU                                                ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/project,or1k                       ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Instantiation of internal CPU blocks. IFETCH, SPRS, FRZ,    ////
10
////  ALU, EXCEPT, ID, WBMUX, OPERANDMUX, RF etc.                 ////
11
////                                                              ////
12
////  To Do:                                                      ////
13
////   - make it smaller and faster                               ////
14
////                                                              ////
15
////  Author(s):                                                  ////
16
////      - Damjan Lampret, lampret@opencores.org                 ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
// $Log: or1200_cpu.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
module or1200_cpu(
56
        // Clk & Rst
57
        clk, rst,
58
 
59
        // Insn interface
60
        ic_en,
61
        icpu_adr_o, icpu_cycstb_o, icpu_sel_o, icpu_tag_o,
62
        icpu_dat_i, icpu_ack_i, icpu_rty_i, icpu_err_i, icpu_adr_i, icpu_tag_i,
63
        immu_en,
64
 
65
        // Debug unit
66
        id_void, id_insn, ex_void,
67
        ex_insn, ex_freeze, wb_insn, wb_freeze, id_pc, ex_pc, wb_pc, branch_op,
68
        spr_dat_npc, rf_dataw, ex_flushpipe,
69
        du_stall, du_addr, du_dat_du, du_read, du_write, du_except_stop,
70
        du_except_trig, du_dsr, du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, du_dat_cpu,
71
        du_lsu_store_dat, du_lsu_load_dat,
72
        abort_mvspr, abort_ex,
73
 
74
        // Data interface
75
        dc_en,
76
        dcpu_adr_o, dcpu_cycstb_o, dcpu_we_o, dcpu_sel_o, dcpu_tag_o,
77
        dcpu_dat_o, dcpu_dat_i, dcpu_ack_i, dcpu_rty_i, dcpu_err_i, dcpu_tag_i,
78
        sb_en, dmmu_en, dc_no_writethrough,
79
 
80
        // SR Interface
81
        boot_adr_sel_i,
82
 
83
        // Interrupt & tick exceptions
84
        sig_int, sig_tick,
85
 
86
        // SPR interface
87
        supv, spr_addr, spr_dat_cpu, spr_dat_pic, spr_dat_tt, spr_dat_pm,
88
        spr_dat_dmmu, spr_dat_immu, spr_dat_du, spr_cs, spr_we, mtspr_dc_done
89
);
90
 
91
parameter dw = `OR1200_OPERAND_WIDTH;
92
parameter aw = `OR1200_REGFILE_ADDR_WIDTH;
93
 
94
//
95
// I/O ports
96
//
97
 
98
//
99
// Clk & Rst
100
//
101
input                           clk;
102
input                           rst;
103
 
104
//
105
// Insn (IC) interface
106
//
107
output                          ic_en;
108
output  [31:0]                   icpu_adr_o;
109
output                          icpu_cycstb_o;
110
output  [3:0]                    icpu_sel_o;
111
output  [3:0]                    icpu_tag_o;
112
input   [31:0]                   icpu_dat_i;
113
input                           icpu_ack_i;
114
input                           icpu_rty_i;
115
input                           icpu_err_i;
116
input   [31:0]                   icpu_adr_i;
117
input   [3:0]                    icpu_tag_i;
118
 
119
//
120
// Insn (IMMU) interface
121
//
122
output                          immu_en;
123
 
124
//
125
// Debug interface
126
//
127
output                          id_void;
128
output  [31:0]                   id_insn;
129
output                          ex_void;
130
output  [31:0]                   ex_insn;
131
output                          ex_freeze;
132
output  [31:0]                   wb_insn;
133
output                          wb_freeze;
134
output  [31:0]                   id_pc;
135
output  [31:0]                   ex_pc;
136
output  [31:0]                   wb_pc;
137
output                          ex_flushpipe;
138
output  [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
139
 
140
input                           du_stall;
141
input   [dw-1:0]         du_addr;
142
input   [dw-1:0]         du_dat_du;
143
input                           du_read;
144
input                           du_write;
145
input   [`OR1200_DU_DSR_WIDTH-1:0]       du_dsr;
146
input   [24:0]                   du_dmr1;
147
input                           du_hwbkpt;
148
input                           du_hwbkpt_ls_r;
149
output  [13:0]                   du_except_trig;
150
output  [13:0]                   du_except_stop;
151
output  [dw-1:0]         du_dat_cpu;
152
output  [dw-1:0]         rf_dataw;
153
output  [dw-1:0]         du_lsu_store_dat;
154
output  [dw-1:0]         du_lsu_load_dat;
155
 
156
//
157
// Data (DC) interface
158
//
159
output  [31:0]                   dcpu_adr_o;
160
output                          dcpu_cycstb_o;
161
output                          dcpu_we_o;
162
output  [3:0]                    dcpu_sel_o;
163
output  [3:0]                    dcpu_tag_o;
164
output  [31:0]                   dcpu_dat_o;
165
input   [31:0]                   dcpu_dat_i;
166
input                           dcpu_ack_i;
167
input                           dcpu_rty_i;
168
input                           dcpu_err_i;
169
input   [3:0]                    dcpu_tag_i;
170
output                          dc_en;
171
output                          dc_no_writethrough;
172
 
173
//
174
// Data (DMMU) interface
175
//
176
output                          sb_en;
177
output                          dmmu_en;
178
output                          abort_ex;
179
output                          abort_mvspr;
180
 
181
//
182
// SR Interface 
183
//
184
input                           boot_adr_sel_i;
185
 
186
//
187
// SPR interface
188
//
189
output                          supv;
190
input   [dw-1:0]         spr_dat_pic;
191
input   [dw-1:0]         spr_dat_tt;
192
input   [dw-1:0]         spr_dat_pm;
193
input   [dw-1:0]         spr_dat_dmmu;
194
input   [dw-1:0]         spr_dat_immu;
195
input   [dw-1:0]         spr_dat_du;
196
output  [dw-1:0]         spr_addr;
197
output  [dw-1:0]         spr_dat_cpu;
198
output  [dw-1:0]         spr_dat_npc;
199
output  [31:0]                   spr_cs;
200
output                          spr_we;
201
input                           mtspr_dc_done;
202
 
203
//
204
// Interrupt exceptions
205
//
206
input                           sig_int;
207
input                           sig_tick;
208
 
209
//
210
// Internal wires
211
//
212
wire    [31:0]                   if_insn;
213
wire                            saving_if_insn;
214
wire    [31:0]                   if_pc;
215
wire    [aw-1:0]         rf_addrw;
216
wire    [aw-1:0]                 rf_addra;
217
wire    [aw-1:0]                 rf_addrb;
218
wire                            rf_rda;
219
wire                            rf_rdb;
220
wire    [dw-1:0]         id_simm;
221
wire    [dw-1:2]                id_branch_addrtarget;
222
wire    [dw-1:2]                ex_branch_addrtarget;
223
wire    [`OR1200_ALUOP_WIDTH-1:0]        alu_op;
224 403 julius
wire    [`OR1200_ALUOP2_WIDTH-1:0]       alu_op2;
225 350 julius
wire    [`OR1200_COMPOP_WIDTH-1:0]       comp_op;
226
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     pre_branch_op;
227
wire    [`OR1200_BRANCHOP_WIDTH-1:0]     branch_op;
228
wire    [`OR1200_LSUOP_WIDTH-1:0]        id_lsu_op;
229
wire                            genpc_freeze;
230
wire                            if_freeze;
231
wire                            id_freeze;
232
wire                            ex_freeze;
233
wire                            wb_freeze;
234
wire    [`OR1200_SEL_WIDTH-1:0]  sel_a;
235
wire    [`OR1200_SEL_WIDTH-1:0]  sel_b;
236
wire    [`OR1200_RFWBOP_WIDTH-1:0]       rfwb_op;
237
wire    [`OR1200_FPUOP_WIDTH-1:0]       fpu_op;
238
wire    [dw-1:0]         rf_dataw;
239
wire    [dw-1:0]         rf_dataa;
240
wire    [dw-1:0]         rf_datab;
241
wire    [dw-1:0]         muxed_a;
242
wire    [dw-1:0]         muxed_b;
243
wire    [dw-1:0]         wb_forw;
244
wire                            wbforw_valid;
245
wire    [dw-1:0]         operand_a;
246
wire    [dw-1:0]         operand_b;
247
wire    [dw-1:0]         alu_dataout;
248
wire    [dw-1:0]         lsu_dataout;
249
wire    [dw-1:0]         sprs_dataout;
250
wire    [dw-1:0]         fpu_dataout;
251
wire                            fpu_done;
252
wire    [31:0]                   ex_simm;
253
wire    [`OR1200_MULTICYCLE_WIDTH-1:0]   multicycle;
254
wire    [`OR1200_WAIT_ON_WIDTH-1:0]      wait_on;
255
wire    [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
256
wire    [4:0]                    cust5_op;
257
wire    [5:0]                    cust5_limm;
258
wire                            if_flushpipe;
259
wire                            id_flushpipe;
260
wire                            ex_flushpipe;
261
wire                            wb_flushpipe;
262
wire                            extend_flush;
263
wire                            ex_branch_taken;
264
wire                            flag;
265
wire                            flagforw;
266
wire                            flag_we;
267
wire                            flagforw_alu;
268
wire                            flag_we_alu;
269
wire                            flagforw_fpu;
270
wire                            flag_we_fpu;
271
wire                            carry;
272
wire                            cyforw;
273
wire                            cy_we_alu;
274
wire                            cy_we_rf;
275
wire                            lsu_stall;
276
wire                            epcr_we;
277
wire                            eear_we;
278
wire                            esr_we;
279
wire                            pc_we;
280
wire    [31:0]                   epcr;
281
wire    [31:0]                   eear;
282
wire    [`OR1200_SR_WIDTH-1:0]   esr;
283
wire    [`OR1200_FPCSR_WIDTH-1:0]       fpcsr;
284
wire                            fpcsr_we;
285
wire                            sr_we;
286
wire    [`OR1200_SR_WIDTH-1:0]   to_sr;
287
wire    [`OR1200_SR_WIDTH-1:0]   sr;
288
wire                            except_flushpipe;
289
wire                            except_start;
290
wire                            except_started;
291
wire                            fpu_except_started;
292
wire    [31:0]                   wb_insn;
293
wire                            sig_syscall;
294
wire                            sig_trap;
295
wire                            sig_fp;
296
wire    [31:0]                   spr_dat_cfgr;
297
wire    [31:0]                   spr_dat_rf;
298
wire    [31:0]                  spr_dat_npc;
299
wire    [31:0]                   spr_dat_ppc;
300
wire    [31:0]                   spr_dat_mac;
301
wire [31:0]                      spr_dat_fpu;
302
wire                            mtspr_done;
303
wire                            force_dslot_fetch;
304
wire                            no_more_dslot;
305
wire                            ex_void;
306
wire                            ex_spr_read;
307
wire                            ex_spr_write;
308
wire                            if_stall;
309
wire                            id_macrc_op;
310
wire                            ex_macrc_op;
311
wire    [`OR1200_MACOP_WIDTH-1:0] id_mac_op;
312
wire    [`OR1200_MACOP_WIDTH-1:0] mac_op;
313
wire    [31:0]                   mult_mac_result;
314 435 julius
wire                            mult_mac_stall;
315 350 julius
wire    [13:0]                   except_trig;
316
wire    [13:0]                   except_stop;
317
wire                            genpc_refetch;
318
wire                            rfe;
319
wire                            lsu_unstall;
320
wire                            except_align;
321
wire                            except_dtlbmiss;
322
wire                            except_dmmufault;
323
wire                            except_illegal;
324
wire                            except_itlbmiss;
325
wire                            except_immufault;
326
wire                            except_ibuserr;
327
wire                            except_dbuserr;
328
wire                            abort_ex;
329
wire                            abort_mvspr;
330
 
331
//
332
// Send exceptions to Debug Unit
333
//
334
assign du_except_trig = except_trig;
335
assign du_except_stop = except_stop;
336
assign du_lsu_store_dat = operand_b;
337
assign du_lsu_load_dat  = lsu_dataout;
338
 
339
//
340
// Data cache enable
341
//
342
`ifdef OR1200_NO_DC
343
assign dc_en = 1'b0;
344
`else
345
   assign dc_en = sr[`OR1200_SR_DCE];
346
`endif
347
 
348
//
349
// Instruction cache enable
350
//
351
`ifdef OR1200_NO_IC
352
assign ic_en = 1'b0;
353
`else
354
assign ic_en = sr[`OR1200_SR_ICE];
355
`endif
356
 
357
//
358
// SB enable
359
//
360
`ifdef OR1200_SB_IMPLEMENTED
361
//assign sb_en = sr[`OR1200_SR_SBE]; // SBE not defined  -- jb
362
`else
363
assign sb_en = 1'b0;
364
`endif
365
 
366
//
367
// DMMU enable
368
//
369
`ifdef OR1200_NO_DMMU
370
assign dmmu_en = 1'b0;
371
`else
372
assign dmmu_en = sr[`OR1200_SR_DME];
373
`endif
374
 
375
//
376
// IMMU enable
377
//
378
`ifdef OR1200_NO_IMMU
379
assign immu_en = 1'b0;
380
`else
381
assign immu_en = sr[`OR1200_SR_IME] & ~except_started;
382
`endif
383
 
384
//
385
// SUPV bit
386
//
387
assign supv = sr[`OR1200_SR_SM];
388
 
389
//
390
// FLAG write enable
391
//
392
assign flagforw = (flag_we_alu & flagforw_alu) | (flagforw_fpu & flag_we_fpu);
393
assign flag_we = (flag_we_alu | flag_we_fpu) & ~abort_mvspr;
394
 
395
//
396
//  Flag for any MTSPR instructions, that must block execution, to indicate done
397
//
398
assign mtspr_done = mtspr_dc_done;
399
 
400
 
401
//
402
// Instantiation of instruction fetch block
403
//
404
or1200_genpc or1200_genpc(
405
        .clk(clk),
406
        .rst(rst),
407
        .icpu_adr_o(icpu_adr_o),
408
        .icpu_cycstb_o(icpu_cycstb_o),
409
        .icpu_sel_o(icpu_sel_o),
410
        .icpu_tag_o(icpu_tag_o),
411
        .icpu_rty_i(icpu_rty_i),
412
        .icpu_adr_i(icpu_adr_i),
413
 
414
        .pre_branch_op(pre_branch_op),
415
        .branch_op(branch_op),
416
        .except_type(except_type),
417
        .except_start(except_start),
418
        .except_prefix(sr[`OR1200_SR_EPH]),
419
        .id_branch_addrtarget(id_branch_addrtarget),
420
        .ex_branch_addrtarget(ex_branch_addrtarget),
421
        .muxed_b(muxed_b),
422
        .operand_b(operand_b),
423
        .flag(flag),
424
        .flagforw(flagforw),
425
        .ex_branch_taken(ex_branch_taken),
426
        .epcr(epcr),
427
        .spr_dat_i(spr_dat_cpu),
428
        .spr_pc_we(pc_we),
429
        .genpc_refetch(genpc_refetch),
430
        .genpc_freeze(genpc_freeze),
431
        .no_more_dslot(no_more_dslot)
432
);
433
 
434
//
435
// Instantiation of instruction fetch block
436
//
437
or1200_if or1200_if(
438
        .clk(clk),
439
        .rst(rst),
440
        .icpu_dat_i(icpu_dat_i),
441
        .icpu_ack_i(icpu_ack_i),
442
        .icpu_err_i(icpu_err_i),
443
        .icpu_adr_i(icpu_adr_i),
444
        .icpu_tag_i(icpu_tag_i),
445
 
446
        .if_freeze(if_freeze),
447
        .if_insn(if_insn),
448
        .if_pc(if_pc),
449
        .saving_if_insn(saving_if_insn),
450
        .if_flushpipe(if_flushpipe),
451
        .if_stall(if_stall),
452
        .no_more_dslot(no_more_dslot),
453
        .genpc_refetch(genpc_refetch),
454
        .rfe(rfe),
455
        .except_itlbmiss(except_itlbmiss),
456
        .except_immufault(except_immufault),
457
        .except_ibuserr(except_ibuserr)
458
);
459
 
460
//
461
// Instantiation of instruction decode/control logic
462
//
463
or1200_ctrl or1200_ctrl(
464
        .clk(clk),
465
        .rst(rst),
466
        .id_freeze(id_freeze),
467
        .ex_freeze(ex_freeze),
468
        .wb_freeze(wb_freeze),
469
        .if_flushpipe(if_flushpipe),
470
        .id_flushpipe(id_flushpipe),
471
        .ex_flushpipe(ex_flushpipe),
472
        .wb_flushpipe(wb_flushpipe),
473
        .extend_flush(extend_flush),
474
        .except_flushpipe(except_flushpipe),
475
        .abort_mvspr(abort_mvspr),
476
        .if_insn(if_insn),
477
        .id_insn(id_insn),
478
        .ex_insn(ex_insn),
479
        .id_branch_op(pre_branch_op),
480
        .ex_branch_op(branch_op),
481
        .ex_branch_taken(ex_branch_taken),
482
        .rf_addra(rf_addra),
483
        .rf_addrb(rf_addrb),
484
        .rf_rda(rf_rda),
485
        .rf_rdb(rf_rdb),
486
        .alu_op(alu_op),
487 403 julius
        .alu_op2(alu_op2),
488 350 julius
        .mac_op(mac_op),
489
        .comp_op(comp_op),
490
        .rf_addrw(rf_addrw),
491
        .rfwb_op(rfwb_op),
492
        .fpu_op(fpu_op),
493
        .pc_we(pc_we),
494
        .wb_insn(wb_insn),
495
        .id_simm(id_simm),
496
        .id_branch_addrtarget(id_branch_addrtarget),
497
        .ex_branch_addrtarget(ex_branch_addrtarget),
498
        .ex_simm(ex_simm),
499
        .sel_a(sel_a),
500
        .sel_b(sel_b),
501
        .id_lsu_op(id_lsu_op),
502
        .cust5_op(cust5_op),
503
        .cust5_limm(cust5_limm),
504
        .id_pc(id_pc),
505
        .ex_pc(ex_pc),
506
        .multicycle(multicycle),
507
        .wait_on(wait_on),
508
        .wbforw_valid(wbforw_valid),
509
        .sig_syscall(sig_syscall),
510
        .sig_trap(sig_trap),
511
        .force_dslot_fetch(force_dslot_fetch),
512
        .no_more_dslot(no_more_dslot),
513
        .id_void(id_void),
514
        .ex_void(ex_void),
515
        .ex_spr_read(ex_spr_read),
516
        .ex_spr_write(ex_spr_write),
517
        .id_mac_op(id_mac_op),
518
        .id_macrc_op(id_macrc_op),
519
        .ex_macrc_op(ex_macrc_op),
520
        .rfe(rfe),
521
        .du_hwbkpt(du_hwbkpt),
522
        .except_illegal(except_illegal),
523
        .dc_no_writethrough(dc_no_writethrough)
524
);
525
 
526
//
527
// Instantiation of register file
528
//
529
or1200_rf or1200_rf(
530
        .clk(clk),
531
        .rst(rst),
532
        .cy_we_i(cy_we_alu),
533
        .cy_we_o(cy_we_rf),
534
        .supv(sr[`OR1200_SR_SM]),
535
        .wb_freeze(wb_freeze),
536
        .addrw(rf_addrw),
537
        .dataw(rf_dataw),
538
        .id_freeze(id_freeze),
539
        .we(rfwb_op[0]),
540
        .flushpipe(wb_flushpipe),
541
        .addra(rf_addra),
542
        .rda(rf_rda),
543
        .dataa(rf_dataa),
544
        .addrb(rf_addrb),
545
        .rdb(rf_rdb),
546
        .datab(rf_datab),
547
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_SYS]),
548
        .spr_write(spr_we),
549
        .spr_addr(spr_addr),
550
        .spr_dat_i(spr_dat_cpu),
551
        .spr_dat_o(spr_dat_rf),
552
        .du_read(du_read)
553
);
554
 
555
//
556
// Instantiation of operand muxes
557
//
558
or1200_operandmuxes or1200_operandmuxes(
559
        .clk(clk),
560
        .rst(rst),
561
        .id_freeze(id_freeze),
562
        .ex_freeze(ex_freeze),
563
        .rf_dataa(rf_dataa),
564
        .rf_datab(rf_datab),
565
        .ex_forw(rf_dataw),
566
        .wb_forw(wb_forw),
567
        .simm(id_simm),
568
        .sel_a(sel_a),
569
        .sel_b(sel_b),
570
        .operand_a(operand_a),
571
        .operand_b(operand_b),
572
        .muxed_a(muxed_a),
573
        .muxed_b(muxed_b)
574
);
575
 
576
//
577
// Instantiation of CPU's ALU
578
//
579
or1200_alu or1200_alu(
580
        .a(operand_a),
581
        .b(operand_b),
582
        .mult_mac_result(mult_mac_result),
583
        .macrc_op(ex_macrc_op),
584
        .alu_op(alu_op),
585 403 julius
        .alu_op2(alu_op2),
586 350 julius
        .comp_op(comp_op),
587
        .cust5_op(cust5_op),
588
        .cust5_limm(cust5_limm),
589
        .result(alu_dataout),
590
        .flagforw(flagforw_alu),
591
        .flag_we(flag_we_alu),
592
        .cyforw(cyforw),
593
        .cy_we(cy_we_alu),
594
        .flag(flag),
595
        .carry(carry)
596
);
597
 
598
 
599
//
600
// FPU's exception is being dealt with
601
//    
602
assign fpu_except_started = except_started && (except_type == `OR1200_EXCEPT_FLOAT);
603
 
604
//
605
// Instantiation of FPU
606
//
607
or1200_fpu or1200_fpu(
608
        .clk(clk),
609
        .rst(rst),
610
        .ex_freeze(ex_freeze),
611
        .a(operand_a),
612
        .b(operand_b),
613
        .fpu_op(fpu_op),
614
        .result(fpu_dataout),
615
        .done(fpu_done),
616
        .flagforw(flagforw_fpu),
617
        .flag_we(flag_we_fpu),
618
        .sig_fp(sig_fp),
619
        .except_started(fpu_except_started),
620
        .fpcsr_we(fpcsr_we),
621
        .fpcsr(fpcsr),
622
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_FPU]),
623
        .spr_write(spr_we),
624
        .spr_addr(spr_addr),
625
        .spr_dat_i(spr_dat_cpu),
626
        .spr_dat_o(spr_dat_fpu)
627
);
628
 
629
 
630
//
631
// Instantiation of CPU's multiply unit
632
//
633
or1200_mult_mac or1200_mult_mac(
634
        .clk(clk),
635
        .rst(rst),
636
        .ex_freeze(ex_freeze),
637
        .id_macrc_op(id_macrc_op),
638
        .macrc_op(ex_macrc_op),
639
        .a(operand_a),
640
        .b(operand_b),
641
        .mac_op(mac_op),
642
        .alu_op(alu_op),
643
        .result(mult_mac_result),
644 435 julius
        .mult_mac_stall(mult_mac_stall),
645 350 julius
        .spr_cs(spr_cs[`OR1200_SPR_GROUP_MAC]),
646
        .spr_write(spr_we),
647
        .spr_addr(spr_addr),
648
        .spr_dat_i(spr_dat_cpu),
649
        .spr_dat_o(spr_dat_mac)
650
);
651
 
652
//
653
// Instantiation of CPU's SPRS block
654
//
655
or1200_sprs or1200_sprs(
656
        .clk(clk),
657
        .rst(rst),
658
        .addrbase(operand_a),
659
        .addrofs(ex_simm[15:0]),
660
        .dat_i(operand_b),
661
        .ex_spr_read(ex_spr_read),
662
        .ex_spr_write(ex_spr_write),
663
        .flagforw(flagforw),
664
        .flag_we(flag_we),
665
        .flag(flag),
666
        .cyforw(cyforw),
667
        .cy_we(cy_we_rf),
668
        .carry(carry),
669
        .to_wbmux(sprs_dataout),
670
 
671
        .du_addr(du_addr),
672
        .du_dat_du(du_dat_du),
673
        .du_read(du_read),
674
        .du_write(du_write),
675
        .du_dat_cpu(du_dat_cpu),
676
        .boot_adr_sel_i(boot_adr_sel_i),
677
        .spr_addr(spr_addr),
678
        .spr_dat_pic(spr_dat_pic),
679
        .spr_dat_tt(spr_dat_tt),
680
        .spr_dat_pm(spr_dat_pm),
681
        .spr_dat_cfgr(spr_dat_cfgr),
682
        .spr_dat_rf(spr_dat_rf),
683
        .spr_dat_npc(spr_dat_npc),
684
        .spr_dat_ppc(spr_dat_ppc),
685
        .spr_dat_mac(spr_dat_mac),
686
        .spr_dat_dmmu(spr_dat_dmmu),
687
        .spr_dat_immu(spr_dat_immu),
688
        .spr_dat_du(spr_dat_du),
689
        .spr_dat_o(spr_dat_cpu),
690
        .spr_cs(spr_cs),
691
        .spr_we(spr_we),
692
 
693
        .epcr_we(epcr_we),
694
        .eear_we(eear_we),
695
        .esr_we(esr_we),
696
        .pc_we(pc_we),
697
        .epcr(epcr),
698
        .eear(eear),
699
        .esr(esr),
700
        .except_started(except_started),
701
 
702
        .fpcsr(fpcsr),
703
        .fpcsr_we(fpcsr_we),
704
        .spr_dat_fpu(spr_dat_fpu),
705
 
706
        .sr_we(sr_we),
707
        .to_sr(to_sr),
708
        .sr(sr),
709
        .branch_op(branch_op)
710
);
711
 
712
//
713
// Instantiation of load/store unit
714
//
715
or1200_lsu or1200_lsu(
716
        .clk(clk),
717
        .rst(rst),
718
        .id_addrbase(muxed_a),
719
        .id_addrofs(id_simm),
720
        .ex_addrbase(operand_a),
721
        .ex_addrofs(ex_simm),
722
        .id_lsu_op(id_lsu_op),
723
        .lsu_datain(operand_b),
724
        .lsu_dataout(lsu_dataout),
725
        .lsu_stall(lsu_stall),
726
        .lsu_unstall(lsu_unstall),
727
        .du_stall(du_stall),
728
        .except_align(except_align),
729
        .except_dtlbmiss(except_dtlbmiss),
730
        .except_dmmufault(except_dmmufault),
731
        .except_dbuserr(except_dbuserr),
732
        .id_freeze(id_freeze),
733
        .ex_freeze(ex_freeze),
734
        .flushpipe(ex_flushpipe),
735
 
736
        .dcpu_adr_o(dcpu_adr_o),
737
        .dcpu_cycstb_o(dcpu_cycstb_o),
738
        .dcpu_we_o(dcpu_we_o),
739
        .dcpu_sel_o(dcpu_sel_o),
740
        .dcpu_tag_o(dcpu_tag_o),
741
        .dcpu_dat_o(dcpu_dat_o),
742
        .dcpu_dat_i(dcpu_dat_i),
743
        .dcpu_ack_i(dcpu_ack_i),
744
        .dcpu_rty_i(dcpu_rty_i),
745
        .dcpu_err_i(dcpu_err_i),
746
        .dcpu_tag_i(dcpu_tag_i)
747
);
748
 
749
//
750
// Instantiation of write-back muxes
751
//
752
or1200_wbmux or1200_wbmux(
753
        .clk(clk),
754
        .rst(rst),
755
        .wb_freeze(wb_freeze),
756
        .rfwb_op(rfwb_op),
757
        .muxin_a(alu_dataout),
758
        .muxin_b(lsu_dataout),
759
        .muxin_c(sprs_dataout),
760
        .muxin_d(ex_pc),
761
        .muxin_e(fpu_dataout),
762
        .muxout(rf_dataw),
763
        .muxreg(wb_forw),
764
        .muxreg_valid(wbforw_valid)
765
);
766
 
767
//
768
// Instantiation of freeze logic
769
//
770
or1200_freeze or1200_freeze(
771
        .clk(clk),
772
        .rst(rst),
773
        .multicycle(multicycle),
774
        .wait_on(wait_on),
775
        .fpu_done(fpu_done),
776
        .mtspr_done(mtspr_done),
777
        .flushpipe(wb_flushpipe),
778
        .extend_flush(extend_flush),
779
        .lsu_stall(lsu_stall),
780
        .if_stall(if_stall),
781
        .lsu_unstall(lsu_unstall),
782
        .force_dslot_fetch(force_dslot_fetch),
783
        .abort_ex(abort_ex),
784
        .du_stall(du_stall),
785 435 julius
        .mac_stall(mult_mac_stall),
786 350 julius
        .saving_if_insn(saving_if_insn),
787
        .genpc_freeze(genpc_freeze),
788
        .if_freeze(if_freeze),
789
        .id_freeze(id_freeze),
790
        .ex_freeze(ex_freeze),
791
        .wb_freeze(wb_freeze),
792
        .icpu_ack_i(icpu_ack_i),
793
        .icpu_err_i(icpu_err_i)
794
);
795
 
796
//
797
// Instantiation of exception block
798
//
799
or1200_except or1200_except(
800
        .clk(clk),
801
        .rst(rst),
802
        .sig_ibuserr(except_ibuserr),
803
        .sig_dbuserr(except_dbuserr),
804
        .sig_illegal(except_illegal),
805
        .sig_align(except_align),
806
        .sig_range(1'b0),
807
        .sig_dtlbmiss(except_dtlbmiss),
808
        .sig_dmmufault(except_dmmufault),
809
        .sig_int(sig_int),
810
        .sig_syscall(sig_syscall),
811
        .sig_trap(sig_trap),
812
        .sig_itlbmiss(except_itlbmiss),
813
        .sig_immufault(except_immufault),
814
        .sig_tick(sig_tick),
815
        .sig_fp(sig_fp),
816
        .fpcsr_fpee(fpcsr[`OR1200_FPCSR_FPEE]),
817
        .ex_branch_taken(ex_branch_taken),
818
        .icpu_ack_i(icpu_ack_i),
819
        .icpu_err_i(icpu_err_i),
820
        .dcpu_ack_i(dcpu_ack_i),
821
        .dcpu_err_i(dcpu_err_i),
822
        .genpc_freeze(genpc_freeze),
823
        .id_freeze(id_freeze),
824
        .ex_freeze(ex_freeze),
825
        .wb_freeze(wb_freeze),
826
        .if_stall(if_stall),
827
        .if_pc(if_pc),
828
        .id_pc(id_pc),
829
        .ex_pc(ex_pc),
830
        .wb_pc(wb_pc),
831
        .id_flushpipe(id_flushpipe),
832
        .ex_flushpipe(ex_flushpipe),
833
        .extend_flush(extend_flush),
834
        .except_flushpipe(except_flushpipe),
835
        .abort_mvspr(abort_mvspr),
836
        .except_type(except_type),
837
        .except_start(except_start),
838
        .except_started(except_started),
839
        .except_stop(except_stop),
840
        .except_trig(except_trig),
841
        .ex_void(ex_void),
842
        .spr_dat_ppc(spr_dat_ppc),
843
        .spr_dat_npc(spr_dat_npc),
844
 
845
        .datain(spr_dat_cpu),
846
        .branch_op(branch_op),
847
        .du_dsr(du_dsr),
848
        .du_dmr1(du_dmr1),
849
        .du_hwbkpt(du_hwbkpt),
850
        .du_hwbkpt_ls_r(du_hwbkpt_ls_r),
851
        .epcr_we(epcr_we),
852
        .eear_we(eear_we),
853
        .esr_we(esr_we),
854
        .pc_we(pc_we),
855
        .epcr(epcr),
856
        .eear(eear),
857
        .esr(esr),
858
 
859
        .lsu_addr(dcpu_adr_o),
860
        .sr_we(sr_we),
861
        .to_sr(to_sr),
862
        .sr(sr),
863
        .abort_ex(abort_ex)
864
);
865
 
866
//
867
// Instantiation of configuration registers
868
//
869
or1200_cfgr or1200_cfgr(
870
        .spr_addr(spr_addr),
871
        .spr_dat_o(spr_dat_cfgr)
872
);
873
 
874
endmodule

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