OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ctrl.v] - Blame information for rev 537

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Instruction decode                                 ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/project,or1k                       ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Majority of instruction decoding is performed here.         ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
//
45
// $Log: or1200_ctrl.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
module or1200_ctrl
56
  (
57
   // Clock and reset
58
   clk, rst,
59
 
60
   // Internal i/f
61
   except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
62
   wb_flushpipe,
63
   id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
64
   id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
65 499 julius
   rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, alu_op2, mac_op,
66 403 julius
   comp_op, rf_addrw, rfwb_op, fpu_op,
67 350 julius
   wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
68
   sel_b, id_lsu_op,
69
   cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
70
   multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
71
   force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
72
   ex_spr_write,
73
   id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal, dc_no_writethrough
74
   );
75
 
76
//
77
// I/O
78
//
79
input                                   clk;
80
input                                   rst;
81
input                                   id_freeze;
82 353 julius
input                                   ex_freeze /* verilator public */;
83
input                                   wb_freeze /* verilator public */;
84 350 julius
output                                  if_flushpipe;
85
output                                  id_flushpipe;
86
output                                  ex_flushpipe;
87
output                                  wb_flushpipe;
88
input                                   extend_flush;
89
input                                   except_flushpipe;
90
input                           abort_mvspr ;
91
input   [31:0]                   if_insn;
92
output  [31:0]                   id_insn;
93 353 julius
output  [31:0]                   ex_insn /* verilator public */;
94 350 julius
output  [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
95
output  [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
96
input                                           ex_branch_taken;
97
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
98
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
99
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
100
output                                  rf_rda;
101
output                                  rf_rdb;
102
output  [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
103 403 julius
output [`OR1200_ALUOP2_WIDTH-1:0]                alu_op2;
104 350 julius
output  [`OR1200_MACOP_WIDTH-1:0]                mac_op;
105
output  [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
106
output  [`OR1200_FPUOP_WIDTH-1:0]                fpu_op;
107
input                                   pc_we;
108
output  [31:0]                           wb_insn;
109
output  [31:2]                          id_branch_addrtarget;
110
output  [31:2]                          ex_branch_addrtarget;
111
output  [`OR1200_SEL_WIDTH-1:0]          sel_a;
112
output  [`OR1200_SEL_WIDTH-1:0]          sel_b;
113
output  [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
114
output  [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
115
output  [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
116
output  [`OR1200_WAIT_ON_WIDTH-1:0]              wait_on;
117
output  [4:0]                            cust5_op;
118
output  [5:0]                            cust5_limm;
119
input   [31:0]                          id_pc;
120
input   [31:0]                          ex_pc;
121
output  [31:0]                           id_simm;
122
output  [31:0]                           ex_simm;
123
input                                   wbforw_valid;
124
input                                   du_hwbkpt;
125
output                                  sig_syscall;
126
output                                  sig_trap;
127
output                                  force_dslot_fetch;
128
output                                  no_more_dslot;
129
output                                  id_void;
130
output                                  ex_void;
131
output                                  ex_spr_read;
132
output                                  ex_spr_write;
133
output  [`OR1200_MACOP_WIDTH-1:0]        id_mac_op;
134
output                                  id_macrc_op;
135
output                                  ex_macrc_op;
136
output                                  rfe;
137
output                                  except_illegal;
138
output                                  dc_no_writethrough;
139
 
140
 
141
//
142
// Internal wires and regs
143
//
144
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
145
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
146
reg     [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
147 403 julius
reg [`OR1200_ALUOP2_WIDTH-1:0]                   alu_op2;
148 350 julius
wire                                    if_maci_op;
149
`ifdef OR1200_MAC_IMPLEMENTED
150
reg     [`OR1200_MACOP_WIDTH-1:0]                ex_mac_op;
151
reg     [`OR1200_MACOP_WIDTH-1:0]                id_mac_op;
152
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
153
reg                                     ex_macrc_op;
154
`else
155
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
156
wire                                    ex_macrc_op;
157
`endif
158 353 julius
reg     [31:0]                           id_insn /* verilator public */;
159
reg     [31:0]                           ex_insn /* verilator public */;
160
reg     [31:0]                           wb_insn /* verilator public */;
161 350 julius
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
162
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
163
reg     [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
164
reg     [`OR1200_SEL_WIDTH-1:0]          sel_a;
165
reg     [`OR1200_SEL_WIDTH-1:0]          sel_b;
166
reg                                     sel_imm;
167
reg     [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
168
reg     [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
169
reg     [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
170
reg     [`OR1200_WAIT_ON_WIDTH-1:0]              wait_on;
171
reg     [31:0]                           id_simm;
172
reg     [31:0]                           ex_simm;
173
reg                                     sig_syscall;
174
reg                                     sig_trap;
175
reg                                     except_illegal;
176
wire                                    id_void;
177
wire                                    ex_void;
178
wire                                    wb_void;
179
reg                                     ex_delayslot_dsi;
180
reg                                     ex_delayslot_nop;
181
reg                                     spr_read;
182
reg                                     spr_write;
183
reg     [31:2]                          ex_branch_addrtarget;
184
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
185
reg                                     dc_no_writethrough;
186
`endif
187
 
188
//
189
// Register file read addresses
190
//
191
assign rf_addra = if_insn[20:16];
192
assign rf_addrb = if_insn[15:11];
193
assign rf_rda = if_insn[31] || if_maci_op;
194
assign rf_rdb = if_insn[30];
195
 
196
//
197 499 julius
// Force fetch of delay slot instruction when jump/branch is preceeded by 
198
// load/store instructions
199 350 julius
//
200
assign force_dslot_fetch = 1'b0;
201 499 julius
assign no_more_dslot = (|ex_branch_op & !id_void & ex_branch_taken) |
202
                       (ex_branch_op == `OR1200_BRANCHOP_RFE);
203 350 julius
 
204
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
205
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
206
assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
207
 
208
assign ex_spr_write = spr_write && !abort_mvspr;
209
assign ex_spr_read = spr_read && !abort_mvspr;
210
 
211
//
212
// ex_delayslot_dsi: delay slot insn is in EX stage
213 499 julius
// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops 
214
//                   jump/branch was executed)
215 350 julius
//
216
//  ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
217
//  !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage, 
218
//       next different is DS insn, previous different was Jump/Branch
219
//  !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
220
//
221 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
222
        if (rst == `OR1200_RST_VALUE) begin
223 350 julius
                ex_delayslot_nop <=  1'b0;
224
                ex_delayslot_dsi <=  1'b0;
225
        end
226
        else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
227
                ex_delayslot_nop <=  id_void;
228
                ex_delayslot_dsi <=  !id_void;
229
        end
230
        else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
231
                ex_delayslot_nop <=  1'b0;
232
                ex_delayslot_dsi <=  1'b0;
233
        end
234
        else if (!ex_freeze) begin
235 499 julius
                ex_delayslot_nop <=  id_void && ex_branch_taken &&
236
                                     (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
237
                                     (ex_branch_op != `OR1200_BRANCHOP_RFE);
238
                ex_delayslot_dsi <=  !id_void && ex_branch_taken &&
239
                                     (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
240
                                     (ex_branch_op != `OR1200_BRANCHOP_RFE);
241 350 julius
        end
242
end
243
 
244
//
245
// Flush pipeline
246
//
247
assign if_flushpipe = except_flushpipe | pc_we | extend_flush;
248
assign id_flushpipe = except_flushpipe | pc_we | extend_flush;
249
assign ex_flushpipe = except_flushpipe | pc_we | extend_flush;
250
assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
251
 
252
//
253
// EX Sign/Zero extension of immediates
254
//
255 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
256
        if (rst == `OR1200_RST_VALUE)
257 350 julius
                ex_simm <=  32'h0000_0000;
258
        else if (!ex_freeze) begin
259
                ex_simm <=  id_simm;
260
        end
261
end
262
 
263
//
264
// ID Sign/Zero extension of immediate
265
//
266
always @(id_insn) begin
267
        case (id_insn[31:26])     // synopsys parallel_case
268
 
269
        // l.addi
270
        `OR1200_OR32_ADDI:
271
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
272
 
273
        // l.addic
274
        `OR1200_OR32_ADDIC:
275
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
276
 
277
        // l.lxx (load instructions)
278 499 julius
        `OR1200_OR32_LWZ, `OR1200_OR32_LBZ, `OR1200_OR32_LBS,
279
        `OR1200_OR32_LHZ, `OR1200_OR32_LHS:
280 350 julius
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
281
 
282
        // l.muli
283
        `ifdef OR1200_MULT_IMPLEMENTED
284
        `OR1200_OR32_MULI:
285
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
286
        `endif
287
 
288
        // l.maci
289
        `ifdef OR1200_MAC_IMPLEMENTED
290
        `OR1200_OR32_MACI:
291 499 julius
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
292 350 julius
        `endif
293
 
294
        // l.mtspr
295
        `OR1200_OR32_MTSPR:
296
                id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};
297
 
298
        // l.sxx (store instructions)
299
        `OR1200_OR32_SW, `OR1200_OR32_SH, `OR1200_OR32_SB:
300
                id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
301
 
302
        // l.xori
303
        `OR1200_OR32_XORI:
304
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
305
 
306
        // l.sfxxi (SFXX with immediate)
307
        `OR1200_OR32_SFXXI:
308
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
309
 
310
        // Instructions with no or zero extended immediate
311
        default:
312
                id_simm = {{16'b0}, id_insn[15:0]};
313
 
314
        endcase
315
end
316
 
317
//
318
// ID Sign extension of branch offset
319
//
320
assign id_branch_addrtarget = {{4{id_insn[25]}}, id_insn[25:0]} + id_pc[31:2];
321
 
322
//
323
// EX Sign extension of branch offset
324
//
325
 
326
// pipeline ID and EX branch target address 
327 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
328
        if (rst == `OR1200_RST_VALUE)
329 363 julius
                ex_branch_addrtarget <=  0;
330 350 julius
        else if (!ex_freeze)
331
                ex_branch_addrtarget <=  id_branch_addrtarget;
332
end
333
// not pipelined
334
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
335
 
336
//
337
// l.maci in IF stage
338
//
339
`ifdef OR1200_MAC_IMPLEMENTED
340
assign if_maci_op = (if_insn[31:26] == `OR1200_OR32_MACI);
341
`else
342
assign if_maci_op = 1'b0;
343
`endif
344
 
345
//
346
// l.macrc in ID stage
347
//
348
`ifdef OR1200_MAC_IMPLEMENTED
349 499 julius
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MACRC) & id_insn[16];
350 350 julius
`else
351
assign id_macrc_op = 1'b0;
352
`endif
353
 
354
//
355
// l.macrc in EX stage
356
//
357
`ifdef OR1200_MAC_IMPLEMENTED
358 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
359
        if (rst == `OR1200_RST_VALUE)
360 350 julius
                ex_macrc_op <=  1'b0;
361
        else if (!ex_freeze & id_freeze | ex_flushpipe)
362
                ex_macrc_op <=  1'b0;
363
        else if (!ex_freeze)
364
                ex_macrc_op <=  id_macrc_op;
365
end
366
`else
367
assign ex_macrc_op = 1'b0;
368
`endif
369
 
370
//
371
// cust5_op, cust5_limm (L immediate)
372
//
373
assign cust5_op = ex_insn[4:0];
374
assign cust5_limm = ex_insn[10:5];
375
 
376
//
377
//
378
//
379 499 julius
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) |
380
             (ex_branch_op == `OR1200_BRANCHOP_RFE);
381 350 julius
 
382 353 julius
 
383
`ifdef verilator
384
   // Function to access wb_insn (for Verilator). Have to hide this from
385
   // simulator, since functions with no inputs are not allowed in IEEE
386
   // 1364-2001.
387
   function [31:0] get_wb_insn;
388
      // verilator public
389
      get_wb_insn = wb_insn;
390
   endfunction // get_wb_insn
391
 
392
   // Function to access id_insn (for Verilator). Have to hide this from
393
   // simulator, since functions with no inputs are not allowed in IEEE
394
   // 1364-2001.
395
   function [31:0] get_id_insn;
396
      // verilator public
397
      get_id_insn = id_insn;
398
   endfunction // get_id_insn
399
 
400
   // Function to access ex_insn (for Verilator). Have to hide this from
401
   // simulator, since functions with no inputs are not allowed in IEEE
402
   // 1364-2001.
403
   function [31:0] get_ex_insn;
404
      // verilator public
405
      get_ex_insn = ex_insn;
406
   endfunction // get_ex_insn
407
 
408
`endif
409
 
410
 
411 350 julius
//
412
// Generation of sel_a
413
//
414
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
415
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
416
                sel_a = `OR1200_SEL_EX_FORW;
417
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
418
                sel_a = `OR1200_SEL_WB_FORW;
419
        else
420
                sel_a = `OR1200_SEL_RF;
421
 
422
//
423
// Generation of sel_b
424
//
425 499 julius
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or
426
         wb_rfaddrw)
427 350 julius
        if (sel_imm)
428
                sel_b = `OR1200_SEL_IMM;
429
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
430
                sel_b = `OR1200_SEL_EX_FORW;
431
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
432
                sel_b = `OR1200_SEL_WB_FORW;
433
        else
434
                sel_b = `OR1200_SEL_RF;
435
 
436
//
437
// Decode of multicycle
438
//
439
always @(id_insn) begin
440
  case (id_insn[31:26])         // synopsys parallel_case
441 537 julius
    // l.rfe
442
    `OR1200_OR32_RFE,
443 350 julius
    // l.mfspr
444
    `OR1200_OR32_MFSPR:
445
      multicycle = `OR1200_TWO_CYCLES;  // to read from ITLB/DTLB (sync RAMs)
446
    // Single cycle instructions
447
    default: begin
448
      multicycle = `OR1200_ONE_CYCLE;
449
    end
450
  endcase
451
end // always @ (id_insn)
452
 
453
//
454
// Encode wait_on signal
455
//    
456
always @(id_insn) begin
457
   case (id_insn[31:26])                // synopsys parallel_case
458 499 julius
     `OR1200_OR32_ALU:
459
       wait_on =  ( 1'b0
460
`ifdef OR1200_DIV_IMPLEMENTED
461
                     | (id_insn[4:0] == `OR1200_ALUOP_DIV)
462
                     | (id_insn[4:0] == `OR1200_ALUOP_DIVU)
463
`endif
464
`ifdef OR1200_MULT_IMPLEMENTED
465
                     | (id_insn[4:0] == `OR1200_ALUOP_MUL)
466
                     | (id_insn[4:0] == `OR1200_ALUOP_MULU)
467
`endif
468
                    ) ? `OR1200_WAIT_ON_MULTMAC : `OR1200_WAIT_ON_NOTHING;
469
`ifdef OR1200_MULT_IMPLEMENTED
470
`ifdef OR1200_MAC_IMPLEMENTED
471
     `OR1200_OR32_MACMSB,
472
     `OR1200_OR32_MACI,
473
`endif
474
     `OR1200_OR32_MULI:
475
         wait_on = `OR1200_WAIT_ON_MULTMAC;
476
`endif
477
`ifdef OR1200_MAC_IMPLEMENTED
478
     `OR1200_OR32_MACRC:
479
         wait_on = id_insn[16] ? `OR1200_WAIT_ON_MULTMAC :
480
                                 `OR1200_WAIT_ON_NOTHING;
481
`endif
482 350 julius
`ifdef OR1200_FPU_IMPLEMENTED
483
       `OR1200_OR32_FLOAT: begin
484
         wait_on = id_insn[`OR1200_FPUOP_DOUBLE_BIT] ? 0 : `OR1200_WAIT_ON_FPU;
485
       end
486
`endif
487 499 julius
`ifndef OR1200_DC_WRITEHROUGH
488 350 julius
     // l.mtspr
489
     `OR1200_OR32_MTSPR: begin
490
        wait_on = `OR1200_WAIT_ON_MTSPR;
491
     end
492
`endif
493
     default: begin
494 499 julius
        wait_on = `OR1200_WAIT_ON_NOTHING;
495 350 julius
     end
496
   endcase // case (id_insn[31:26])
497
end // always @ (id_insn)
498
 
499
 
500
 
501
 
502
//
503
// Register file write address
504
//
505 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
506
        if (rst == `OR1200_RST_VALUE)
507 350 julius
                rf_addrw <=  5'd0;
508
        else if (!ex_freeze & id_freeze)
509
                rf_addrw <=  5'd00;
510
        else if (!ex_freeze)
511
                case (id_insn[31:26])   // synopsys parallel_case
512
                        `OR1200_OR32_JAL, `OR1200_OR32_JALR:
513
                                rf_addrw <=  5'd09;     // link register r9
514
                        default:
515
                                rf_addrw <=  id_insn[25:21];
516
                endcase
517
end
518
 
519
//
520
// rf_addrw in wb stage (used in forwarding logic)
521
//
522 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
523
        if (rst == `OR1200_RST_VALUE)
524 350 julius
                wb_rfaddrw <=  5'd0;
525
        else if (!wb_freeze)
526
                wb_rfaddrw <=  rf_addrw;
527
end
528
 
529
//
530
// Instruction latch in id_insn
531
//
532 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
533
        if (rst == `OR1200_RST_VALUE)
534 350 julius
                id_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
535
        else if (id_flushpipe)
536
                id_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};        // NOP -> id_insn[16] must be 1
537
        else if (!id_freeze) begin
538
                id_insn <=  if_insn;
539
`ifdef OR1200_VERBOSE
540
// synopsys translate_off
541
                $display("%t: id_insn <= %h", $time, if_insn);
542
// synopsys translate_on
543
`endif
544
        end
545
end
546
 
547
//
548
// Instruction latch in ex_insn
549
//
550 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
551
        if (rst == `OR1200_RST_VALUE)
552 350 julius
                ex_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
553
        else if (!ex_freeze & id_freeze | ex_flushpipe)
554
                ex_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};   // NOP -> ex_insn[16] must be 1
555
        else if (!ex_freeze) begin
556
                ex_insn <=  id_insn;
557
`ifdef OR1200_VERBOSE
558
// synopsys translate_off
559
                $display("%t: ex_insn <= %h", $time, id_insn);
560
// synopsys translate_on
561
`endif
562
        end
563
end
564
 
565
//
566
// Instruction latch in wb_insn
567
//
568 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
569
        if (rst == `OR1200_RST_VALUE)
570 350 julius
                wb_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
571
        // wb_insn should not be changed by exceptions due to correct 
572
        // recording of display_arch_state in the or1200_monitor! 
573
        // wb_insn changed by exception is not used elsewhere! 
574
        else if (!wb_freeze) begin
575
                wb_insn <=  ex_insn;
576
        end
577
end
578
 
579
//
580
// Decode of sel_imm
581
//
582 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
583
        if (rst == `OR1200_RST_VALUE)
584 350 julius
                sel_imm <=  1'b0;
585
        else if (!id_freeze) begin
586
          case (if_insn[31:26])         // synopsys parallel_case
587
 
588
            // j.jalr
589
            `OR1200_OR32_JALR:
590
              sel_imm <=  1'b0;
591
 
592
            // l.jr
593
            `OR1200_OR32_JR:
594
              sel_imm <=  1'b0;
595
 
596
            // l.rfe
597
            `OR1200_OR32_RFE:
598
              sel_imm <=  1'b0;
599
 
600
            // l.mfspr
601
            `OR1200_OR32_MFSPR:
602
              sel_imm <=  1'b0;
603
 
604
            // l.mtspr
605
            `OR1200_OR32_MTSPR:
606
              sel_imm <=  1'b0;
607
 
608
            // l.sys, l.brk and all three sync insns
609
            `OR1200_OR32_XSYNC:
610
              sel_imm <=  1'b0;
611
 
612
            // l.mac/l.msb
613
`ifdef OR1200_MAC_IMPLEMENTED
614
            `OR1200_OR32_MACMSB:
615
              sel_imm <=  1'b0;
616
`endif
617
 
618
            // l.sw
619
            `OR1200_OR32_SW:
620
              sel_imm <=  1'b0;
621
 
622
            // l.sb
623
            `OR1200_OR32_SB:
624
              sel_imm <=  1'b0;
625
 
626
            // l.sh
627
            `OR1200_OR32_SH:
628
              sel_imm <=  1'b0;
629
 
630
            // ALU instructions except the one with immediate
631
            `OR1200_OR32_ALU:
632
              sel_imm <=  1'b0;
633
 
634
            // SFXX instructions
635
            `OR1200_OR32_SFXX:
636
              sel_imm <=  1'b0;
637
 
638 499 julius
`ifdef OR1200_IMPL_ALU_CUST5
639 350 julius
            // l.cust5 instructions
640
            `OR1200_OR32_CUST5:
641
              sel_imm <=  1'b0;
642
`endif
643
`ifdef OR1200_FPU_IMPLEMENTED
644
            // FPU instructions
645
            `OR1200_OR32_FLOAT:
646
              sel_imm <=  1'b0;
647
`endif
648
            // l.nop
649
            `OR1200_OR32_NOP:
650
              sel_imm <=  1'b0;
651
 
652
            // All instructions with immediates
653
            default: begin
654
              sel_imm <=  1'b1;
655
            end
656
 
657
          endcase
658
 
659
        end
660
end
661
 
662
//
663
// Decode of except_illegal
664
//
665 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
666
        if (rst == `OR1200_RST_VALUE)
667 350 julius
                except_illegal <=  1'b0;
668
        else if (!ex_freeze & id_freeze | ex_flushpipe)
669
                except_illegal <=  1'b0;
670
        else if (!ex_freeze) begin
671
                case (id_insn[31:26])           // synopsys parallel_case
672
 
673
                `OR1200_OR32_J,
674
                `OR1200_OR32_JAL,
675
                `OR1200_OR32_JALR,
676
                `OR1200_OR32_JR,
677
                `OR1200_OR32_BNF,
678
                `OR1200_OR32_BF,
679
                `OR1200_OR32_RFE,
680
                `OR1200_OR32_MOVHI,
681
                `OR1200_OR32_MFSPR,
682
                `OR1200_OR32_XSYNC,
683
`ifdef OR1200_MAC_IMPLEMENTED
684
                `OR1200_OR32_MACI,
685
`endif
686
                `OR1200_OR32_LWZ,
687
                `OR1200_OR32_LBZ,
688
                `OR1200_OR32_LBS,
689
                `OR1200_OR32_LHZ,
690
                `OR1200_OR32_LHS,
691
                `OR1200_OR32_ADDI,
692
                `OR1200_OR32_ADDIC,
693
                `OR1200_OR32_ANDI,
694
                `OR1200_OR32_ORI,
695
                `OR1200_OR32_XORI,
696
`ifdef OR1200_MULT_IMPLEMENTED
697
                `OR1200_OR32_MULI,
698
`endif
699
                `OR1200_OR32_SH_ROTI,
700
                `OR1200_OR32_SFXXI,
701
                `OR1200_OR32_MTSPR,
702
`ifdef OR1200_MAC_IMPLEMENTED
703
                `OR1200_OR32_MACMSB,
704
`endif
705
                `OR1200_OR32_SW,
706
                `OR1200_OR32_SB,
707
                `OR1200_OR32_SH,
708
                `OR1200_OR32_SFXX,
709 499 julius
`ifdef OR1200_IMPL_ALU_CUST5
710 350 julius
                `OR1200_OR32_CUST5,
711
`endif
712
        `OR1200_OR32_NOP:
713 363 julius
                except_illegal <=  1'b0;
714 350 julius
`ifdef OR1200_FPU_IMPLEMENTED
715
            `OR1200_OR32_FLOAT:
716 363 julius
                // Check it's not a double precision instruction
717
                except_illegal <=  id_insn[`OR1200_FPUOP_DOUBLE_BIT];
718 350 julius
`endif
719
 
720
        `OR1200_OR32_ALU:
721 363 julius
                except_illegal <=  1'b0
722 350 julius
 
723
`ifdef OR1200_MULT_IMPLEMENTED
724
`ifdef OR1200_DIV_IMPLEMENTED
725
`else
726 499 julius
                | (id_insn[4:0] == `OR1200_ALUOP_DIV)
727
                | (id_insn[4:0] == `OR1200_ALUOP_DIVU)
728 350 julius
`endif
729
`else
730 499 julius
                | (id_insn[4:0] == `OR1200_ALUOP_DIV)
731
                | (id_insn[4:0] == `OR1200_ALUOP_DIVU)
732
                | (id_insn[4:0] == `OR1200_ALUOP_MUL)
733 350 julius
`endif
734
 
735
`ifdef OR1200_IMPL_ADDC
736
`else
737 499 julius
                | (id_insn[4:0] == `OR1200_ALUOP_ADDC)
738 350 julius
`endif
739
 
740 403 julius
`ifdef OR1200_IMPL_ALU_FFL1
741
`else
742 499 julius
                | (id_insn[4:0] == `OR1200_ALUOP_FFL1)
743 403 julius
`endif
744
 
745 350 julius
`ifdef OR1200_IMPL_ALU_ROTATE
746
`else
747 499 julius
                | ((id_insn[4:0] == `OR1200_ALUOP_SHROT) &
748
                   (id_insn[9:6] == `OR1200_SHROTOP_ROR))
749 350 julius
`endif
750
 
751
`ifdef OR1200_IMPL_SUB
752
`else
753 499 julius
                | (id_insn[4:0] == `OR1200_ALUOP_SUB)
754 350 julius
`endif
755 499 julius
`ifdef OR1200_IMPL_ALU_EXT
756
`else
757
                | (id_insn[4:0] == `OR1200_ALUOP_EXTHB)
758
                | (id_insn[4:0] == `OR1200_ALUOP_EXTW)
759
`endif
760 363 julius
                ;
761 350 julius
 
762
                // Illegal and OR1200 unsupported instructions
763 363 julius
        default:
764
                except_illegal <=  1'b1;
765 350 julius
 
766 363 julius
        endcase
767
        end // if (!ex_freeze)
768 350 julius
end
769 363 julius
 
770 350 julius
 
771
//
772
// Decode of alu_op
773
//
774 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
775
        if (rst == `OR1200_RST_VALUE)
776 350 julius
                alu_op <=  `OR1200_ALUOP_NOP;
777
        else if (!ex_freeze & id_freeze | ex_flushpipe)
778
                alu_op <=  `OR1200_ALUOP_NOP;
779
        else if (!ex_freeze) begin
780
          case (id_insn[31:26])         // synopsys parallel_case
781
 
782
            // l.movhi
783
            `OR1200_OR32_MOVHI:
784
              alu_op <=  `OR1200_ALUOP_MOVHI;
785
 
786
            // l.addi
787
            `OR1200_OR32_ADDI:
788
              alu_op <=  `OR1200_ALUOP_ADD;
789
 
790
            // l.addic
791
            `OR1200_OR32_ADDIC:
792
              alu_op <=  `OR1200_ALUOP_ADDC;
793
 
794
            // l.andi
795
            `OR1200_OR32_ANDI:
796
              alu_op <=  `OR1200_ALUOP_AND;
797
 
798
            // l.ori
799
            `OR1200_OR32_ORI:
800
              alu_op <=  `OR1200_ALUOP_OR;
801
 
802
            // l.xori
803
            `OR1200_OR32_XORI:
804
              alu_op <=  `OR1200_ALUOP_XOR;
805
 
806
            // l.muli
807
`ifdef OR1200_MULT_IMPLEMENTED
808
            `OR1200_OR32_MULI:
809
              alu_op <=  `OR1200_ALUOP_MUL;
810
`endif
811
 
812
            // Shift and rotate insns with immediate
813
            `OR1200_OR32_SH_ROTI:
814
              alu_op <=  `OR1200_ALUOP_SHROT;
815
 
816
            // SFXX insns with immediate
817
            `OR1200_OR32_SFXXI:
818
              alu_op <=  `OR1200_ALUOP_COMP;
819
 
820
            // ALU instructions except the one with immediate
821
            `OR1200_OR32_ALU:
822 499 julius
              alu_op <=  {1'b0,id_insn[3:0]};
823 350 julius
 
824
            // SFXX instructions
825
            `OR1200_OR32_SFXX:
826
              alu_op <=  `OR1200_ALUOP_COMP;
827 499 julius
`ifdef OR1200_IMPL_ALU_CUST5
828
            // l.cust5
829 350 julius
            `OR1200_OR32_CUST5:
830
              alu_op <=  `OR1200_ALUOP_CUST5;
831 499 julius
`endif
832 350 julius
            // Default
833
            default: begin
834
              alu_op <=  `OR1200_ALUOP_NOP;
835
            end
836
 
837
          endcase
838
 
839
        end
840
end
841
 
842 403 julius
 
843 350 julius
//
844 499 julius
// Decode of second ALU operation field [9:6]
845 403 julius
//
846
always @(posedge clk or `OR1200_RST_EVENT rst) begin
847
        if (rst == `OR1200_RST_VALUE)
848
                alu_op2 <=  0;
849
        else if (!ex_freeze & id_freeze | ex_flushpipe)
850
                alu_op2 <= 0;
851
        else if (!ex_freeze) begin
852
                alu_op2 <=  id_insn[`OR1200_ALUOP2_POS];
853
        end
854
end
855
 
856
//
857 350 julius
// Decode of spr_read, spr_write
858
//
859 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
860
        if (rst == `OR1200_RST_VALUE) begin
861 350 julius
                spr_read <=  1'b0;
862
                spr_write <=  1'b0;
863
        end
864
        else if (!ex_freeze & id_freeze | ex_flushpipe) begin
865
                spr_read <=  1'b0;
866
                spr_write <=  1'b0;
867
        end
868
        else if (!ex_freeze) begin
869
                case (id_insn[31:26])     // synopsys parallel_case
870
 
871
                // l.mfspr
872
                `OR1200_OR32_MFSPR: begin
873
                        spr_read <=  1'b1;
874
                        spr_write <=  1'b0;
875
                end
876
 
877
                // l.mtspr
878
                `OR1200_OR32_MTSPR: begin
879
                        spr_read <=  1'b0;
880
                        spr_write <=  1'b1;
881
                end
882
 
883
                // Default
884
                default: begin
885
                        spr_read <=  1'b0;
886
                        spr_write <=  1'b0;
887
                end
888
 
889
                endcase
890
        end
891
end
892
 
893
//
894
// Decode of mac_op
895
//
896
`ifdef OR1200_MAC_IMPLEMENTED
897
always @(id_insn) begin
898
        case (id_insn[31:26])           // synopsys parallel_case
899
 
900
        // l.maci
901
        `OR1200_OR32_MACI:
902 353 julius
                id_mac_op =  `OR1200_MACOP_MAC;
903 350 julius
 
904
        // l.mac, l.msb
905
        `OR1200_OR32_MACMSB:
906 353 julius
                id_mac_op =  id_insn[2:0];
907 350 julius
 
908
        // Illegal and OR1200 unsupported instructions
909
        default:
910 353 julius
                id_mac_op =  `OR1200_MACOP_NOP;
911 350 julius
 
912
        endcase
913
end
914
 
915 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
916
        if (rst == `OR1200_RST_VALUE)
917 350 julius
                ex_mac_op <=  `OR1200_MACOP_NOP;
918
        else if (!ex_freeze & id_freeze | ex_flushpipe)
919
                ex_mac_op <=  `OR1200_MACOP_NOP;
920
        else if (!ex_freeze)
921
                ex_mac_op <=  id_mac_op;
922
end
923
 
924
assign mac_op = abort_mvspr ? `OR1200_MACOP_NOP : ex_mac_op;
925
`else
926
assign id_mac_op = `OR1200_MACOP_NOP;
927
assign mac_op = `OR1200_MACOP_NOP;
928
`endif
929
 
930
 
931
//
932
// Decode of rfwb_op
933
//
934 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
935
        if (rst == `OR1200_RST_VALUE)
936 350 julius
                rfwb_op <=  `OR1200_RFWBOP_NOP;
937
        else  if (!ex_freeze & id_freeze | ex_flushpipe)
938
                rfwb_op <=  `OR1200_RFWBOP_NOP;
939
        else  if (!ex_freeze) begin
940
                case (id_insn[31:26])           // synopsys parallel_case
941
 
942
                // j.jal
943
                `OR1200_OR32_JAL:
944
                        rfwb_op <=  {`OR1200_RFWBOP_LR, 1'b1};
945
 
946
                // j.jalr
947
                `OR1200_OR32_JALR:
948
                        rfwb_op <=  {`OR1200_RFWBOP_LR, 1'b1};
949
 
950
                // l.movhi
951
                `OR1200_OR32_MOVHI:
952
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
953
 
954
                // l.mfspr
955
                `OR1200_OR32_MFSPR:
956
                        rfwb_op <=  {`OR1200_RFWBOP_SPRS, 1'b1};
957
 
958
                // l.lwz
959
                `OR1200_OR32_LWZ:
960
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
961
 
962
                // l.lbz
963
                `OR1200_OR32_LBZ:
964
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
965
 
966
                // l.lbs
967
                `OR1200_OR32_LBS:
968
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
969
 
970
                // l.lhz
971
                `OR1200_OR32_LHZ:
972
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
973
 
974
                // l.lhs
975
                `OR1200_OR32_LHS:
976
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
977
 
978
                // l.addi
979
                `OR1200_OR32_ADDI:
980
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
981
 
982
                // l.addic
983
                `OR1200_OR32_ADDIC:
984
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
985
 
986
                // l.andi
987
                `OR1200_OR32_ANDI:
988
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
989
 
990
                // l.ori
991
                `OR1200_OR32_ORI:
992
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
993
 
994
                // l.xori
995
                `OR1200_OR32_XORI:
996
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
997
 
998
                // l.muli
999
`ifdef OR1200_MULT_IMPLEMENTED
1000
                `OR1200_OR32_MULI:
1001
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1002
`endif
1003
 
1004
                // Shift and rotate insns with immediate
1005
                `OR1200_OR32_SH_ROTI:
1006
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1007
 
1008
                // ALU instructions except the one with immediate
1009
                `OR1200_OR32_ALU:
1010
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1011
 
1012 499 julius
`ifdef OR1200_ALU_IMPL_CUST5
1013 350 julius
                // l.cust5 instructions
1014
                `OR1200_OR32_CUST5:
1015
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1016
`endif
1017
`ifdef OR1200_FPU_IMPLEMENTED
1018
                  // FPU instructions, lf.XXX.s, except sfxx
1019
                  `OR1200_OR32_FLOAT:
1020
                    rfwb_op <=  {`OR1200_RFWBOP_FPU,!id_insn[3]};
1021
`endif
1022
                // Instructions w/o register-file write-back
1023
                default:
1024
                        rfwb_op <=  `OR1200_RFWBOP_NOP;
1025
 
1026
 
1027
                endcase
1028
        end
1029
end
1030
 
1031
//
1032
// Decode of id_branch_op
1033
//
1034 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1035
        if (rst == `OR1200_RST_VALUE)
1036 350 julius
                id_branch_op <=  `OR1200_BRANCHOP_NOP;
1037
        else if (id_flushpipe)
1038
                id_branch_op <=  `OR1200_BRANCHOP_NOP;
1039
        else if (!id_freeze) begin
1040
                case (if_insn[31:26])           // synopsys parallel_case
1041
 
1042
                // l.j
1043
                `OR1200_OR32_J:
1044
                        id_branch_op <=  `OR1200_BRANCHOP_J;
1045
 
1046
                // j.jal
1047
                `OR1200_OR32_JAL:
1048
                        id_branch_op <=  `OR1200_BRANCHOP_J;
1049
 
1050
                // j.jalr
1051
                `OR1200_OR32_JALR:
1052
                        id_branch_op <=  `OR1200_BRANCHOP_JR;
1053
 
1054
                // l.jr
1055
                `OR1200_OR32_JR:
1056
                        id_branch_op <=  `OR1200_BRANCHOP_JR;
1057
 
1058
                // l.bnf
1059
                `OR1200_OR32_BNF:
1060
                        id_branch_op <=  `OR1200_BRANCHOP_BNF;
1061
 
1062
                // l.bf
1063
                `OR1200_OR32_BF:
1064
                        id_branch_op <=  `OR1200_BRANCHOP_BF;
1065
 
1066
                // l.rfe
1067
                `OR1200_OR32_RFE:
1068
                        id_branch_op <=  `OR1200_BRANCHOP_RFE;
1069
 
1070
                // Non branch instructions
1071
                default:
1072
                        id_branch_op <=  `OR1200_BRANCHOP_NOP;
1073
 
1074
                endcase
1075
        end
1076
end
1077
 
1078
//
1079
// Generation of ex_branch_op
1080
//
1081 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
1082
        if (rst == `OR1200_RST_VALUE)
1083 350 julius
                ex_branch_op <=  `OR1200_BRANCHOP_NOP;
1084
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1085
                ex_branch_op <=  `OR1200_BRANCHOP_NOP;
1086
        else if (!ex_freeze)
1087
                ex_branch_op <=  id_branch_op;
1088
 
1089
//
1090
// Decode of id_lsu_op
1091
//
1092
always @(id_insn) begin
1093
        case (id_insn[31:26])           // synopsys parallel_case
1094
 
1095
        // l.lwz
1096
        `OR1200_OR32_LWZ:
1097 353 julius
                id_lsu_op =  `OR1200_LSUOP_LWZ;
1098 350 julius
 
1099
        // l.lbz
1100
        `OR1200_OR32_LBZ:
1101 353 julius
                id_lsu_op =  `OR1200_LSUOP_LBZ;
1102 350 julius
 
1103
        // l.lbs
1104
        `OR1200_OR32_LBS:
1105 353 julius
                id_lsu_op =  `OR1200_LSUOP_LBS;
1106 350 julius
 
1107
        // l.lhz
1108
        `OR1200_OR32_LHZ:
1109 353 julius
                id_lsu_op =  `OR1200_LSUOP_LHZ;
1110 350 julius
 
1111
        // l.lhs
1112
        `OR1200_OR32_LHS:
1113 353 julius
                id_lsu_op =  `OR1200_LSUOP_LHS;
1114 350 julius
 
1115
        // l.sw
1116
        `OR1200_OR32_SW:
1117 353 julius
                id_lsu_op =  `OR1200_LSUOP_SW;
1118 350 julius
 
1119
        // l.sb
1120
        `OR1200_OR32_SB:
1121 353 julius
                id_lsu_op =  `OR1200_LSUOP_SB;
1122 350 julius
 
1123
        // l.sh
1124
        `OR1200_OR32_SH:
1125 353 julius
                id_lsu_op =  `OR1200_LSUOP_SH;
1126 350 julius
 
1127
        // Non load/store instructions
1128
        default:
1129 353 julius
                id_lsu_op =  `OR1200_LSUOP_NOP;
1130 350 julius
 
1131
        endcase
1132
end
1133
 
1134
//
1135
// Decode of comp_op
1136
//
1137 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1138
        if (rst == `OR1200_RST_VALUE) begin
1139 350 julius
                comp_op <=  4'd0;
1140
        end else if (!ex_freeze & id_freeze | ex_flushpipe)
1141
                comp_op <=  4'd0;
1142
        else if (!ex_freeze)
1143
                comp_op <=  id_insn[24:21];
1144
end
1145
 
1146
`ifdef OR1200_FPU_IMPLEMENTED
1147
//
1148
// Decode of FPU ops
1149
//
1150
   assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT),
1151
                    id_insn[`OR1200_FPUOP_WIDTH-2:0]};
1152
`else
1153
   assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}};
1154
`endif
1155
 
1156
 
1157
//
1158
// Decode of l.sys
1159
//
1160 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1161
        if (rst == `OR1200_RST_VALUE)
1162 350 julius
                sig_syscall <=  1'b0;
1163
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1164
                sig_syscall <=  1'b0;
1165
        else if (!ex_freeze) begin
1166
`ifdef OR1200_VERBOSE
1167
// synopsys translate_off
1168
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
1169
                        $display("Generating sig_syscall");
1170
// synopsys translate_on
1171
`endif
1172
                sig_syscall <=  (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
1173
        end
1174
end
1175
 
1176
//
1177
// Decode of l.trap
1178
//
1179 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1180
        if (rst == `OR1200_RST_VALUE)
1181 350 julius
                sig_trap <=  1'b0;
1182
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1183
                sig_trap <=  1'b0;
1184
        else if (!ex_freeze) begin
1185
`ifdef OR1200_VERBOSE
1186
// synopsys translate_off
1187
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
1188
                        $display("Generating sig_trap");
1189
// synopsys translate_on
1190
`endif
1191
                sig_trap <=  (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
1192
                        | du_hwbkpt;
1193
        end
1194
end
1195
 
1196
// Decode destination register address for data cache to check if store ops
1197
// are being done from the stack register (r1) or frame pointer register (r2)
1198
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
1199 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1200
   if (rst == `OR1200_RST_VALUE)
1201 350 julius
     dc_no_writethrough <= 0;
1202
   else if (!ex_freeze)
1203
     dc_no_writethrough <= (id_insn[20:16] == 5'd1) | (id_insn[20:16] == 5'd2);
1204
end
1205
`else
1206
 
1207
   assign dc_no_writethrough = 0;
1208
 
1209
`endif
1210
 
1211
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.