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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_ctrl.v] - Blame information for rev 403

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1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's Instruction decode                                 ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://www.opencores.org/project,or1k                       ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Majority of instruction decoding is performed here.         ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
//
45
// $Log: or1200_ctrl.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Major update: 
48
// Structure reordered and bugs fixed. 
49
 
50
// synopsys translate_off
51
`include "timescale.v"
52
// synopsys translate_on
53
`include "or1200_defines.v"
54
 
55
module or1200_ctrl
56
  (
57
   // Clock and reset
58
   clk, rst,
59
 
60
   // Internal i/f
61
   except_flushpipe, extend_flush, if_flushpipe, id_flushpipe, ex_flushpipe,
62
   wb_flushpipe,
63
   id_freeze, ex_freeze, wb_freeze, if_insn, id_insn, ex_insn, abort_mvspr,
64
   id_branch_op, ex_branch_op, ex_branch_taken, pc_we,
65 403 julius
   rf_addra, rf_addrb, rf_rda, rf_rdb, alu_op, alu_op2, mac_op, shrot_op,
66
   comp_op, rf_addrw, rfwb_op, fpu_op,
67 350 julius
   wb_insn, id_simm, ex_simm, id_branch_addrtarget, ex_branch_addrtarget, sel_a,
68
   sel_b, id_lsu_op,
69
   cust5_op, cust5_limm, id_pc, ex_pc, du_hwbkpt,
70
   multicycle, wait_on, wbforw_valid, sig_syscall, sig_trap,
71
   force_dslot_fetch, no_more_dslot, id_void, ex_void, ex_spr_read,
72
   ex_spr_write,
73
   id_mac_op, id_macrc_op, ex_macrc_op, rfe, except_illegal, dc_no_writethrough
74
   );
75
 
76
//
77
// I/O
78
//
79
input                                   clk;
80
input                                   rst;
81
input                                   id_freeze;
82 353 julius
input                                   ex_freeze /* verilator public */;
83
input                                   wb_freeze /* verilator public */;
84 350 julius
output                                  if_flushpipe;
85
output                                  id_flushpipe;
86
output                                  ex_flushpipe;
87
output                                  wb_flushpipe;
88
input                                   extend_flush;
89
input                                   except_flushpipe;
90
input                           abort_mvspr ;
91
input   [31:0]                   if_insn;
92
output  [31:0]                   id_insn;
93 353 julius
output  [31:0]                   ex_insn /* verilator public */;
94 350 julius
output  [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
95
output  [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
96
input                                           ex_branch_taken;
97
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
98
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addra;
99
output  [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrb;
100
output                                  rf_rda;
101
output                                  rf_rdb;
102
output  [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
103 403 julius
output [`OR1200_ALUOP2_WIDTH-1:0]                alu_op2;
104 350 julius
output  [`OR1200_MACOP_WIDTH-1:0]                mac_op;
105
output  [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
106
output  [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
107
output  [`OR1200_FPUOP_WIDTH-1:0]                fpu_op;
108
input                                   pc_we;
109
output  [31:0]                           wb_insn;
110
output  [31:2]                          id_branch_addrtarget;
111
output  [31:2]                          ex_branch_addrtarget;
112
output  [`OR1200_SEL_WIDTH-1:0]          sel_a;
113
output  [`OR1200_SEL_WIDTH-1:0]          sel_b;
114
output  [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
115
output  [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
116
output  [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
117
output  [`OR1200_WAIT_ON_WIDTH-1:0]              wait_on;
118
output  [4:0]                            cust5_op;
119
output  [5:0]                            cust5_limm;
120
input   [31:0]                          id_pc;
121
input   [31:0]                          ex_pc;
122
output  [31:0]                           id_simm;
123
output  [31:0]                           ex_simm;
124
input                                   wbforw_valid;
125
input                                   du_hwbkpt;
126
output                                  sig_syscall;
127
output                                  sig_trap;
128
output                                  force_dslot_fetch;
129
output                                  no_more_dslot;
130
output                                  id_void;
131
output                                  ex_void;
132
output                                  ex_spr_read;
133
output                                  ex_spr_write;
134
output  [`OR1200_MACOP_WIDTH-1:0]        id_mac_op;
135
output                                  id_macrc_op;
136
output                                  ex_macrc_op;
137
output                                  rfe;
138
output                                  except_illegal;
139
output                                  dc_no_writethrough;
140
 
141
 
142
//
143
// Internal wires and regs
144
//
145
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             id_branch_op;
146
reg     [`OR1200_BRANCHOP_WIDTH-1:0]             ex_branch_op;
147
reg     [`OR1200_ALUOP_WIDTH-1:0]                alu_op;
148 403 julius
reg [`OR1200_ALUOP2_WIDTH-1:0]                   alu_op2;
149 350 julius
wire                                    if_maci_op;
150
`ifdef OR1200_MAC_IMPLEMENTED
151
reg     [`OR1200_MACOP_WIDTH-1:0]                ex_mac_op;
152
reg     [`OR1200_MACOP_WIDTH-1:0]                id_mac_op;
153
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
154
reg                                     ex_macrc_op;
155
`else
156
wire    [`OR1200_MACOP_WIDTH-1:0]                mac_op;
157
wire                                    ex_macrc_op;
158
`endif
159
reg     [`OR1200_SHROTOP_WIDTH-1:0]              shrot_op;
160 353 julius
reg     [31:0]                           id_insn /* verilator public */;
161
reg     [31:0]                           ex_insn /* verilator public */;
162
reg     [31:0]                           wb_insn /* verilator public */;
163 350 julius
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] rf_addrw;
164
reg     [`OR1200_REGFILE_ADDR_WIDTH-1:0] wb_rfaddrw;
165
reg     [`OR1200_RFWBOP_WIDTH-1:0]               rfwb_op;
166
reg     [`OR1200_SEL_WIDTH-1:0]          sel_a;
167
reg     [`OR1200_SEL_WIDTH-1:0]          sel_b;
168
reg                                     sel_imm;
169
reg     [`OR1200_LSUOP_WIDTH-1:0]                id_lsu_op;
170
reg     [`OR1200_COMPOP_WIDTH-1:0]               comp_op;
171
reg     [`OR1200_MULTICYCLE_WIDTH-1:0]           multicycle;
172
reg     [`OR1200_WAIT_ON_WIDTH-1:0]              wait_on;
173
reg     [31:0]                           id_simm;
174
reg     [31:0]                           ex_simm;
175
reg                                     sig_syscall;
176
reg                                     sig_trap;
177
reg                                     except_illegal;
178
wire                                    id_void;
179
wire                                    ex_void;
180
wire                                    wb_void;
181
reg                                     ex_delayslot_dsi;
182
reg                                     ex_delayslot_nop;
183
reg                                     spr_read;
184
reg                                     spr_write;
185
reg     [31:2]                          ex_branch_addrtarget;
186
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
187
reg                                     dc_no_writethrough;
188
`endif
189
 
190
//
191
// Register file read addresses
192
//
193
assign rf_addra = if_insn[20:16];
194
assign rf_addrb = if_insn[15:11];
195
assign rf_rda = if_insn[31] || if_maci_op;
196
assign rf_rdb = if_insn[30];
197
 
198
//
199
// Force fetch of delay slot instruction when jump/branch is preceeded by load/store
200
// instructions
201
//
202
assign force_dslot_fetch = 1'b0;
203
assign no_more_dslot = (|ex_branch_op & !id_void & ex_branch_taken) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
204
 
205
assign id_void = (id_insn[31:26] == `OR1200_OR32_NOP) & id_insn[16];
206
assign ex_void = (ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16];
207
assign wb_void = (wb_insn[31:26] == `OR1200_OR32_NOP) & wb_insn[16];
208
 
209
assign ex_spr_write = spr_write && !abort_mvspr;
210
assign ex_spr_read = spr_read && !abort_mvspr;
211
 
212
//
213
// ex_delayslot_dsi: delay slot insn is in EX stage
214
// ex_delayslot_nop: (filler) nop insn is in EX stage (before nops jump/branch was executed)
215
//
216
//  ex_delayslot_dsi & !ex_delayslot_nop - DS insn in EX stage
217
//  !ex_delayslot_dsi & ex_delayslot_nop - NOP insn in EX stage, 
218
//       next different is DS insn, previous different was Jump/Branch
219
//  !ex_delayslot_dsi & !ex_delayslot_nop - normal insn in EX stage
220
//
221 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
222
        if (rst == `OR1200_RST_VALUE) begin
223 350 julius
                ex_delayslot_nop <=  1'b0;
224
                ex_delayslot_dsi <=  1'b0;
225
        end
226
        else if (!ex_freeze & !ex_delayslot_dsi & ex_delayslot_nop) begin
227
                ex_delayslot_nop <=  id_void;
228
                ex_delayslot_dsi <=  !id_void;
229
        end
230
        else if (!ex_freeze & ex_delayslot_dsi & !ex_delayslot_nop) begin
231
                ex_delayslot_nop <=  1'b0;
232
                ex_delayslot_dsi <=  1'b0;
233
        end
234
        else if (!ex_freeze) begin
235
                ex_delayslot_nop <=  id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
236
                                                                (ex_branch_op != `OR1200_BRANCHOP_RFE);
237
                ex_delayslot_dsi <=  !id_void && ex_branch_taken && (ex_branch_op != `OR1200_BRANCHOP_NOP) &&
238
                                                                 (ex_branch_op != `OR1200_BRANCHOP_RFE);
239
        end
240
end
241
 
242
//
243
// Flush pipeline
244
//
245
assign if_flushpipe = except_flushpipe | pc_we | extend_flush;
246
assign id_flushpipe = except_flushpipe | pc_we | extend_flush;
247
assign ex_flushpipe = except_flushpipe | pc_we | extend_flush;
248
assign wb_flushpipe = except_flushpipe | pc_we | extend_flush;
249
 
250
//
251
// EX Sign/Zero extension of immediates
252
//
253 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
254
        if (rst == `OR1200_RST_VALUE)
255 350 julius
                ex_simm <=  32'h0000_0000;
256
        else if (!ex_freeze) begin
257
                ex_simm <=  id_simm;
258
        end
259
end
260
 
261
//
262
// ID Sign/Zero extension of immediate
263
//
264
always @(id_insn) begin
265
        case (id_insn[31:26])     // synopsys parallel_case
266
 
267
        // l.addi
268
        `OR1200_OR32_ADDI:
269
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
270
 
271
        // l.addic
272
        `OR1200_OR32_ADDIC:
273
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
274
 
275
        // l.lxx (load instructions)
276
        `OR1200_OR32_LWZ, `OR1200_OR32_LBZ, `OR1200_OR32_LBS, `OR1200_OR32_LHZ, `OR1200_OR32_LHS:
277
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
278
 
279
        // l.muli
280
        `ifdef OR1200_MULT_IMPLEMENTED
281
        `OR1200_OR32_MULI:
282
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
283
        `endif
284
 
285
        // l.maci
286
        `ifdef OR1200_MAC_IMPLEMENTED
287
        `OR1200_OR32_MACI:
288
                id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
289
        `endif
290
 
291
        // l.mtspr
292
        `OR1200_OR32_MTSPR:
293
                id_simm = {16'b0, id_insn[25:21], id_insn[10:0]};
294
 
295
        // l.sxx (store instructions)
296
        `OR1200_OR32_SW, `OR1200_OR32_SH, `OR1200_OR32_SB:
297
                id_simm = {{16{id_insn[25]}}, id_insn[25:21], id_insn[10:0]};
298
 
299
        // l.xori
300
        `OR1200_OR32_XORI:
301
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
302
 
303
        // l.sfxxi (SFXX with immediate)
304
        `OR1200_OR32_SFXXI:
305
                id_simm = {{16{id_insn[15]}}, id_insn[15:0]};
306
 
307
        // Instructions with no or zero extended immediate
308
        default:
309
                id_simm = {{16'b0}, id_insn[15:0]};
310
 
311
        endcase
312
end
313
 
314
//
315
// ID Sign extension of branch offset
316
//
317
assign id_branch_addrtarget = {{4{id_insn[25]}}, id_insn[25:0]} + id_pc[31:2];
318
 
319
//
320
// EX Sign extension of branch offset
321
//
322
 
323
// pipeline ID and EX branch target address 
324 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
325
        if (rst == `OR1200_RST_VALUE)
326 363 julius
                ex_branch_addrtarget <=  0;
327 350 julius
        else if (!ex_freeze)
328
                ex_branch_addrtarget <=  id_branch_addrtarget;
329
end
330
// not pipelined
331
//assign ex_branch_addrtarget = {{4{ex_insn[25]}}, ex_insn[25:0]} + ex_pc[31:2];
332
 
333
//
334
// l.maci in IF stage
335
//
336
`ifdef OR1200_MAC_IMPLEMENTED
337
assign if_maci_op = (if_insn[31:26] == `OR1200_OR32_MACI);
338
`else
339
assign if_maci_op = 1'b0;
340
`endif
341
 
342
//
343
// l.macrc in ID stage
344
//
345
`ifdef OR1200_MAC_IMPLEMENTED
346
assign id_macrc_op = (id_insn[31:26] == `OR1200_OR32_MOVHI) & id_insn[16];
347
`else
348
assign id_macrc_op = 1'b0;
349
`endif
350
 
351
//
352
// l.macrc in EX stage
353
//
354
`ifdef OR1200_MAC_IMPLEMENTED
355 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
356
        if (rst == `OR1200_RST_VALUE)
357 350 julius
                ex_macrc_op <=  1'b0;
358
        else if (!ex_freeze & id_freeze | ex_flushpipe)
359
                ex_macrc_op <=  1'b0;
360
        else if (!ex_freeze)
361
                ex_macrc_op <=  id_macrc_op;
362
end
363
`else
364
assign ex_macrc_op = 1'b0;
365
`endif
366
 
367
//
368
// cust5_op, cust5_limm (L immediate)
369
//
370
assign cust5_op = ex_insn[4:0];
371
assign cust5_limm = ex_insn[10:5];
372
 
373
//
374
//
375
//
376
assign rfe = (id_branch_op == `OR1200_BRANCHOP_RFE) | (ex_branch_op == `OR1200_BRANCHOP_RFE);
377
 
378 353 julius
 
379
`ifdef verilator
380
   // Function to access wb_insn (for Verilator). Have to hide this from
381
   // simulator, since functions with no inputs are not allowed in IEEE
382
   // 1364-2001.
383
   function [31:0] get_wb_insn;
384
      // verilator public
385
      get_wb_insn = wb_insn;
386
   endfunction // get_wb_insn
387
 
388
   // Function to access id_insn (for Verilator). Have to hide this from
389
   // simulator, since functions with no inputs are not allowed in IEEE
390
   // 1364-2001.
391
   function [31:0] get_id_insn;
392
      // verilator public
393
      get_id_insn = id_insn;
394
   endfunction // get_id_insn
395
 
396
   // Function to access ex_insn (for Verilator). Have to hide this from
397
   // simulator, since functions with no inputs are not allowed in IEEE
398
   // 1364-2001.
399
   function [31:0] get_ex_insn;
400
      // verilator public
401
      get_ex_insn = ex_insn;
402
   endfunction // get_ex_insn
403
 
404
`endif
405
 
406
 
407 350 julius
//
408
// Generation of sel_a
409
//
410
always @(rf_addrw or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
411
        if ((id_insn[20:16] == rf_addrw) && rfwb_op[0])
412
                sel_a = `OR1200_SEL_EX_FORW;
413
        else if ((id_insn[20:16] == wb_rfaddrw) && wbforw_valid)
414
                sel_a = `OR1200_SEL_WB_FORW;
415
        else
416
                sel_a = `OR1200_SEL_RF;
417
 
418
//
419
// Generation of sel_b
420
//
421
always @(rf_addrw or sel_imm or id_insn or rfwb_op or wbforw_valid or wb_rfaddrw)
422
        if (sel_imm)
423
                sel_b = `OR1200_SEL_IMM;
424
        else if ((id_insn[15:11] == rf_addrw) && rfwb_op[0])
425
                sel_b = `OR1200_SEL_EX_FORW;
426
        else if ((id_insn[15:11] == wb_rfaddrw) && wbforw_valid)
427
                sel_b = `OR1200_SEL_WB_FORW;
428
        else
429
                sel_b = `OR1200_SEL_RF;
430
 
431
//
432
// Decode of multicycle
433
//
434
always @(id_insn) begin
435
  case (id_insn[31:26])         // synopsys parallel_case
436
`ifdef UNUSED
437
    // l.lwz
438
    `OR1200_OR32_LWZ:
439
      multicycle = `OR1200_TWO_CYCLES;
440
 
441
    // l.lbz
442
    `OR1200_OR32_LBZ:
443
      multicycle = `OR1200_TWO_CYCLES;
444
 
445
    // l.lbs
446
    `OR1200_OR32_LBS:
447
      multicycle = `OR1200_TWO_CYCLES;
448
 
449
    // l.lhz
450
    `OR1200_OR32_LHZ:
451
      multicycle = `OR1200_TWO_CYCLES;
452
 
453
    // l.lhs
454
    `OR1200_OR32_LHS:
455
      multicycle = `OR1200_TWO_CYCLES;
456
 
457
    // l.sw
458
    `OR1200_OR32_SW:
459
      multicycle = `OR1200_TWO_CYCLES;
460
 
461
    // l.sb
462
    `OR1200_OR32_SB:
463
      multicycle = `OR1200_TWO_CYCLES;
464
 
465
    // l.sh
466
    `OR1200_OR32_SH:
467
      multicycle = `OR1200_TWO_CYCLES;
468
`endif
469
    // l.mfspr
470
    `OR1200_OR32_MFSPR:
471
      multicycle = `OR1200_TWO_CYCLES;  // to read from ITLB/DTLB (sync RAMs)
472
 
473
    // ALU instructions except the one with immediate
474
    `OR1200_OR32_ALU:
475
        case (id_insn[3:0]) // synopsys parallel_case
476 363 julius
        4'h6: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mul
477
        4'h9: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.div
478
        4'hA: multicycle = `OR1200_MULTICYCLE_WIDTH'd2; // l.divu
479
        4'hB: multicycle = `OR1200_MULTICYCLE_WIDTH'd3; // l.mulu
480
        default: multicycle = `OR1200_MULTICYCLE_WIDTH'd0;
481
        endcase
482 350 julius
    `OR1200_OR32_MULI:
483 363 julius
      multicycle = `OR1200_MULTICYCLE_WIDTH'd3;
484 350 julius
 
485
    // Single cycle instructions
486
    default: begin
487
      multicycle = `OR1200_ONE_CYCLE;
488
    end
489
  endcase
490
end // always @ (id_insn)
491
 
492
//
493
// Encode wait_on signal
494
//    
495
always @(id_insn) begin
496
   case (id_insn[31:26])                // synopsys parallel_case
497
`ifdef OR1200_FPU_IMPLEMENTED
498
       `OR1200_OR32_FLOAT: begin
499
         wait_on = id_insn[`OR1200_FPUOP_DOUBLE_BIT] ? 0 : `OR1200_WAIT_ON_FPU;
500
       end
501
`endif
502
`ifndef OR1200_DC_WRITHROUGH
503
     // l.mtspr
504
     `OR1200_OR32_MTSPR: begin
505
        wait_on = `OR1200_WAIT_ON_MTSPR;
506
     end
507
`endif
508
     default: begin
509
        wait_on = 0;
510
     end
511
   endcase // case (id_insn[31:26])
512
end // always @ (id_insn)
513
 
514
 
515
 
516
 
517
//
518
// Register file write address
519
//
520 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
521
        if (rst == `OR1200_RST_VALUE)
522 350 julius
                rf_addrw <=  5'd0;
523
        else if (!ex_freeze & id_freeze)
524
                rf_addrw <=  5'd00;
525
        else if (!ex_freeze)
526
                case (id_insn[31:26])   // synopsys parallel_case
527
                        `OR1200_OR32_JAL, `OR1200_OR32_JALR:
528
                                rf_addrw <=  5'd09;     // link register r9
529
                        default:
530
                                rf_addrw <=  id_insn[25:21];
531
                endcase
532
end
533
 
534
//
535
// rf_addrw in wb stage (used in forwarding logic)
536
//
537 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
538
        if (rst == `OR1200_RST_VALUE)
539 350 julius
                wb_rfaddrw <=  5'd0;
540
        else if (!wb_freeze)
541
                wb_rfaddrw <=  rf_addrw;
542
end
543
 
544
//
545
// Instruction latch in id_insn
546
//
547 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
548
        if (rst == `OR1200_RST_VALUE)
549 350 julius
                id_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
550
        else if (id_flushpipe)
551
                id_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};        // NOP -> id_insn[16] must be 1
552
        else if (!id_freeze) begin
553
                id_insn <=  if_insn;
554
`ifdef OR1200_VERBOSE
555
// synopsys translate_off
556
                $display("%t: id_insn <= %h", $time, if_insn);
557
// synopsys translate_on
558
`endif
559
        end
560
end
561
 
562
//
563
// Instruction latch in ex_insn
564
//
565 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
566
        if (rst == `OR1200_RST_VALUE)
567 350 julius
                ex_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
568
        else if (!ex_freeze & id_freeze | ex_flushpipe)
569
                ex_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};   // NOP -> ex_insn[16] must be 1
570
        else if (!ex_freeze) begin
571
                ex_insn <=  id_insn;
572
`ifdef OR1200_VERBOSE
573
// synopsys translate_off
574
                $display("%t: ex_insn <= %h", $time, id_insn);
575
// synopsys translate_on
576
`endif
577
        end
578
end
579
 
580
//
581
// Instruction latch in wb_insn
582
//
583 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
584
        if (rst == `OR1200_RST_VALUE)
585 350 julius
                wb_insn <=  {`OR1200_OR32_NOP, 26'h041_0000};
586
        // wb_insn should not be changed by exceptions due to correct 
587
        // recording of display_arch_state in the or1200_monitor! 
588
        // wb_insn changed by exception is not used elsewhere! 
589
        else if (!wb_freeze) begin
590
                wb_insn <=  ex_insn;
591
        end
592
end
593
 
594
//
595
// Decode of sel_imm
596
//
597 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
598
        if (rst == `OR1200_RST_VALUE)
599 350 julius
                sel_imm <=  1'b0;
600
        else if (!id_freeze) begin
601
          case (if_insn[31:26])         // synopsys parallel_case
602
 
603
            // j.jalr
604
            `OR1200_OR32_JALR:
605
              sel_imm <=  1'b0;
606
 
607
            // l.jr
608
            `OR1200_OR32_JR:
609
              sel_imm <=  1'b0;
610
 
611
            // l.rfe
612
            `OR1200_OR32_RFE:
613
              sel_imm <=  1'b0;
614
 
615
            // l.mfspr
616
            `OR1200_OR32_MFSPR:
617
              sel_imm <=  1'b0;
618
 
619
            // l.mtspr
620
            `OR1200_OR32_MTSPR:
621
              sel_imm <=  1'b0;
622
 
623
            // l.sys, l.brk and all three sync insns
624
            `OR1200_OR32_XSYNC:
625
              sel_imm <=  1'b0;
626
 
627
            // l.mac/l.msb
628
`ifdef OR1200_MAC_IMPLEMENTED
629
            `OR1200_OR32_MACMSB:
630
              sel_imm <=  1'b0;
631
`endif
632
 
633
            // l.sw
634
            `OR1200_OR32_SW:
635
              sel_imm <=  1'b0;
636
 
637
            // l.sb
638
            `OR1200_OR32_SB:
639
              sel_imm <=  1'b0;
640
 
641
            // l.sh
642
            `OR1200_OR32_SH:
643
              sel_imm <=  1'b0;
644
 
645
            // ALU instructions except the one with immediate
646
            `OR1200_OR32_ALU:
647
              sel_imm <=  1'b0;
648
 
649
            // SFXX instructions
650
            `OR1200_OR32_SFXX:
651
              sel_imm <=  1'b0;
652
 
653
`ifdef OR1200_OR32_CUST5
654
            // l.cust5 instructions
655
            `OR1200_OR32_CUST5:
656
              sel_imm <=  1'b0;
657
`endif
658
`ifdef OR1200_FPU_IMPLEMENTED
659
            // FPU instructions
660
            `OR1200_OR32_FLOAT:
661
              sel_imm <=  1'b0;
662
`endif
663
            // l.nop
664
            `OR1200_OR32_NOP:
665
              sel_imm <=  1'b0;
666
 
667
            // All instructions with immediates
668
            default: begin
669
              sel_imm <=  1'b1;
670
            end
671
 
672
          endcase
673
 
674
        end
675
end
676
 
677
//
678
// Decode of except_illegal
679
//
680 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
681
        if (rst == `OR1200_RST_VALUE)
682 350 julius
                except_illegal <=  1'b0;
683
        else if (!ex_freeze & id_freeze | ex_flushpipe)
684
                except_illegal <=  1'b0;
685
        else if (!ex_freeze) begin
686
                case (id_insn[31:26])           // synopsys parallel_case
687
 
688
                `OR1200_OR32_J,
689
                `OR1200_OR32_JAL,
690
                `OR1200_OR32_JALR,
691
                `OR1200_OR32_JR,
692
                `OR1200_OR32_BNF,
693
                `OR1200_OR32_BF,
694
                `OR1200_OR32_RFE,
695
                `OR1200_OR32_MOVHI,
696
                `OR1200_OR32_MFSPR,
697
                `OR1200_OR32_XSYNC,
698
`ifdef OR1200_MAC_IMPLEMENTED
699
                `OR1200_OR32_MACI,
700
`endif
701
                `OR1200_OR32_LWZ,
702
                `OR1200_OR32_LBZ,
703
                `OR1200_OR32_LBS,
704
                `OR1200_OR32_LHZ,
705
                `OR1200_OR32_LHS,
706
                `OR1200_OR32_ADDI,
707
                `OR1200_OR32_ADDIC,
708
                `OR1200_OR32_ANDI,
709
                `OR1200_OR32_ORI,
710
                `OR1200_OR32_XORI,
711
`ifdef OR1200_MULT_IMPLEMENTED
712
                `OR1200_OR32_MULI,
713
`endif
714
                `OR1200_OR32_SH_ROTI,
715
                `OR1200_OR32_SFXXI,
716
                `OR1200_OR32_MTSPR,
717
`ifdef OR1200_MAC_IMPLEMENTED
718
                `OR1200_OR32_MACMSB,
719
`endif
720
                `OR1200_OR32_SW,
721
                `OR1200_OR32_SB,
722
                `OR1200_OR32_SH,
723
                `OR1200_OR32_SFXX,
724
`ifdef OR1200_OR32_CUST5
725
                `OR1200_OR32_CUST5,
726
`endif
727
        `OR1200_OR32_NOP:
728 363 julius
                except_illegal <=  1'b0;
729 350 julius
`ifdef OR1200_FPU_IMPLEMENTED
730
            `OR1200_OR32_FLOAT:
731 363 julius
                // Check it's not a double precision instruction
732
                except_illegal <=  id_insn[`OR1200_FPUOP_DOUBLE_BIT];
733 350 julius
`endif
734
 
735
        `OR1200_OR32_ALU:
736 363 julius
                except_illegal <=  1'b0
737 350 julius
 
738
`ifdef OR1200_MULT_IMPLEMENTED
739
`ifdef OR1200_DIV_IMPLEMENTED
740
`else
741 363 julius
                | (id_insn[3:0] == `OR1200_ALUOP_DIV)
742
                | (id_insn[3:0] == `OR1200_ALUOP_DIVU)
743 350 julius
`endif
744
`else
745 363 julius
                | (id_insn[3:0] == `OR1200_ALUOP_DIV)
746
                | (id_insn[3:0] == `OR1200_ALUOP_DIVU)
747
                | (id_insn[3:0] == `OR1200_ALUOP_MUL)
748 350 julius
`endif
749
 
750
`ifdef OR1200_IMPL_ADDC
751
`else
752 363 julius
                | (id_insn[3:0] == `OR1200_ALUOP_ADDC)
753 350 julius
`endif
754
 
755 403 julius
`ifdef OR1200_IMPL_ALU_FFL1
756
`else
757
                | (id_insn[3:0] == `OR1200_ALUOP_FFL1)
758
`endif
759
 
760 350 julius
`ifdef OR1200_IMPL_ALU_ROTATE
761
`else
762 363 julius
                | ((id_insn[3:0] == `OR1200_ALUOP_SHROT) &
763
                   (id_insn[7:6] == `OR1200_SHROTOP_ROR))
764 350 julius
`endif
765
 
766
`ifdef OR1200_IMPL_SUB
767
`else
768 363 julius
                | (id_insn[3:0] == `OR1200_ALUOP_SUB)
769 350 julius
`endif
770 363 julius
                ;
771 350 julius
 
772
                // Illegal and OR1200 unsupported instructions
773 363 julius
        default:
774
                except_illegal <=  1'b1;
775 350 julius
 
776 363 julius
        endcase
777
        end // if (!ex_freeze)
778 350 julius
end
779 363 julius
 
780 350 julius
 
781
//
782
// Decode of alu_op
783
//
784 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
785
        if (rst == `OR1200_RST_VALUE)
786 350 julius
                alu_op <=  `OR1200_ALUOP_NOP;
787
        else if (!ex_freeze & id_freeze | ex_flushpipe)
788
                alu_op <=  `OR1200_ALUOP_NOP;
789
        else if (!ex_freeze) begin
790
          case (id_insn[31:26])         // synopsys parallel_case
791
 
792
            // l.movhi
793
            `OR1200_OR32_MOVHI:
794
              alu_op <=  `OR1200_ALUOP_MOVHI;
795
 
796
            // l.addi
797
            `OR1200_OR32_ADDI:
798
              alu_op <=  `OR1200_ALUOP_ADD;
799
 
800
            // l.addic
801
            `OR1200_OR32_ADDIC:
802
              alu_op <=  `OR1200_ALUOP_ADDC;
803
 
804
            // l.andi
805
            `OR1200_OR32_ANDI:
806
              alu_op <=  `OR1200_ALUOP_AND;
807
 
808
            // l.ori
809
            `OR1200_OR32_ORI:
810
              alu_op <=  `OR1200_ALUOP_OR;
811
 
812
            // l.xori
813
            `OR1200_OR32_XORI:
814
              alu_op <=  `OR1200_ALUOP_XOR;
815
 
816
            // l.muli
817
`ifdef OR1200_MULT_IMPLEMENTED
818
            `OR1200_OR32_MULI:
819
              alu_op <=  `OR1200_ALUOP_MUL;
820
`endif
821
 
822
            // Shift and rotate insns with immediate
823
            `OR1200_OR32_SH_ROTI:
824
              alu_op <=  `OR1200_ALUOP_SHROT;
825
 
826
            // SFXX insns with immediate
827
            `OR1200_OR32_SFXXI:
828
              alu_op <=  `OR1200_ALUOP_COMP;
829
 
830
            // ALU instructions except the one with immediate
831
            `OR1200_OR32_ALU:
832
              alu_op <=  id_insn[3:0];
833
 
834
            // SFXX instructions
835
            `OR1200_OR32_SFXX:
836
              alu_op <=  `OR1200_ALUOP_COMP;
837
 
838
`ifdef OR1200_OR32_CUST5
839
            // l.cust5 instructions
840
            `OR1200_OR32_CUST5:
841
              alu_op <=  `OR1200_ALUOP_CUST5;
842
`endif
843
 
844
            // Default
845
            default: begin
846
              alu_op <=  `OR1200_ALUOP_NOP;
847
            end
848
 
849
          endcase
850
 
851
        end
852
end
853
 
854 403 julius
 
855 350 julius
//
856 403 julius
// Decode of alu_op2 (field of bits 9:8)
857
//
858
always @(posedge clk or `OR1200_RST_EVENT rst) begin
859
        if (rst == `OR1200_RST_VALUE)
860
                alu_op2 <=  0;
861
        else if (!ex_freeze & id_freeze | ex_flushpipe)
862
                alu_op2 <= 0;
863
        else if (!ex_freeze) begin
864
                alu_op2 <=  id_insn[`OR1200_ALUOP2_POS];
865
        end
866
end
867
 
868
 
869
//
870 350 julius
// Decode of spr_read, spr_write
871
//
872 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
873
        if (rst == `OR1200_RST_VALUE) begin
874 350 julius
                spr_read <=  1'b0;
875
                spr_write <=  1'b0;
876
        end
877
        else if (!ex_freeze & id_freeze | ex_flushpipe) begin
878
                spr_read <=  1'b0;
879
                spr_write <=  1'b0;
880
        end
881
        else if (!ex_freeze) begin
882
                case (id_insn[31:26])     // synopsys parallel_case
883
 
884
                // l.mfspr
885
                `OR1200_OR32_MFSPR: begin
886
                        spr_read <=  1'b1;
887
                        spr_write <=  1'b0;
888
                end
889
 
890
                // l.mtspr
891
                `OR1200_OR32_MTSPR: begin
892
                        spr_read <=  1'b0;
893
                        spr_write <=  1'b1;
894
                end
895
 
896
                // Default
897
                default: begin
898
                        spr_read <=  1'b0;
899
                        spr_write <=  1'b0;
900
                end
901
 
902
                endcase
903
        end
904
end
905
 
906
//
907
// Decode of mac_op
908
//
909
`ifdef OR1200_MAC_IMPLEMENTED
910
always @(id_insn) begin
911
        case (id_insn[31:26])           // synopsys parallel_case
912
 
913
        // l.maci
914
        `OR1200_OR32_MACI:
915 353 julius
                id_mac_op =  `OR1200_MACOP_MAC;
916 350 julius
 
917
        // l.mac, l.msb
918
        `OR1200_OR32_MACMSB:
919 353 julius
                id_mac_op =  id_insn[2:0];
920 350 julius
 
921
        // Illegal and OR1200 unsupported instructions
922
        default:
923 353 julius
                id_mac_op =  `OR1200_MACOP_NOP;
924 350 julius
 
925
        endcase
926
end
927
 
928 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
929
        if (rst == `OR1200_RST_VALUE)
930 350 julius
                ex_mac_op <=  `OR1200_MACOP_NOP;
931
        else if (!ex_freeze & id_freeze | ex_flushpipe)
932
                ex_mac_op <=  `OR1200_MACOP_NOP;
933
        else if (!ex_freeze)
934
                ex_mac_op <=  id_mac_op;
935
end
936
 
937
assign mac_op = abort_mvspr ? `OR1200_MACOP_NOP : ex_mac_op;
938
`else
939
assign id_mac_op = `OR1200_MACOP_NOP;
940
assign mac_op = `OR1200_MACOP_NOP;
941
`endif
942
 
943
//
944
// Decode of shrot_op
945
//
946 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
947
        if (rst == `OR1200_RST_VALUE)
948 350 julius
                shrot_op <=  `OR1200_SHROTOP_NOP;
949
        else if (!ex_freeze & id_freeze | ex_flushpipe)
950
                shrot_op <=  `OR1200_SHROTOP_NOP;
951
        else if (!ex_freeze) begin
952
                shrot_op <=  id_insn[`OR1200_SHROTOP_POS];
953
        end
954
end
955
 
956
//
957
// Decode of rfwb_op
958
//
959 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
960
        if (rst == `OR1200_RST_VALUE)
961 350 julius
                rfwb_op <=  `OR1200_RFWBOP_NOP;
962
        else  if (!ex_freeze & id_freeze | ex_flushpipe)
963
                rfwb_op <=  `OR1200_RFWBOP_NOP;
964
        else  if (!ex_freeze) begin
965
                case (id_insn[31:26])           // synopsys parallel_case
966
 
967
                // j.jal
968
                `OR1200_OR32_JAL:
969
                        rfwb_op <=  {`OR1200_RFWBOP_LR, 1'b1};
970
 
971
                // j.jalr
972
                `OR1200_OR32_JALR:
973
                        rfwb_op <=  {`OR1200_RFWBOP_LR, 1'b1};
974
 
975
                // l.movhi
976
                `OR1200_OR32_MOVHI:
977
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
978
 
979
                // l.mfspr
980
                `OR1200_OR32_MFSPR:
981
                        rfwb_op <=  {`OR1200_RFWBOP_SPRS, 1'b1};
982
 
983
                // l.lwz
984
                `OR1200_OR32_LWZ:
985
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
986
 
987
                // l.lbz
988
                `OR1200_OR32_LBZ:
989
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
990
 
991
                // l.lbs
992
                `OR1200_OR32_LBS:
993
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
994
 
995
                // l.lhz
996
                `OR1200_OR32_LHZ:
997
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
998
 
999
                // l.lhs
1000
                `OR1200_OR32_LHS:
1001
                        rfwb_op <=  {`OR1200_RFWBOP_LSU, 1'b1};
1002
 
1003
                // l.addi
1004
                `OR1200_OR32_ADDI:
1005
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1006
 
1007
                // l.addic
1008
                `OR1200_OR32_ADDIC:
1009
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1010
 
1011
                // l.andi
1012
                `OR1200_OR32_ANDI:
1013
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1014
 
1015
                // l.ori
1016
                `OR1200_OR32_ORI:
1017
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1018
 
1019
                // l.xori
1020
                `OR1200_OR32_XORI:
1021
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1022
 
1023
                // l.muli
1024
`ifdef OR1200_MULT_IMPLEMENTED
1025
                `OR1200_OR32_MULI:
1026
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1027
`endif
1028
 
1029
                // Shift and rotate insns with immediate
1030
                `OR1200_OR32_SH_ROTI:
1031
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1032
 
1033
                // ALU instructions except the one with immediate
1034
                `OR1200_OR32_ALU:
1035
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1036
 
1037
`ifdef OR1200_OR32_CUST5
1038
                // l.cust5 instructions
1039
                `OR1200_OR32_CUST5:
1040
                        rfwb_op <=  {`OR1200_RFWBOP_ALU, 1'b1};
1041
`endif
1042
`ifdef OR1200_FPU_IMPLEMENTED
1043
                  // FPU instructions, lf.XXX.s, except sfxx
1044
                  `OR1200_OR32_FLOAT:
1045
                    rfwb_op <=  {`OR1200_RFWBOP_FPU,!id_insn[3]};
1046
`endif
1047
                // Instructions w/o register-file write-back
1048
                default:
1049
                        rfwb_op <=  `OR1200_RFWBOP_NOP;
1050
 
1051
 
1052
                endcase
1053
        end
1054
end
1055
 
1056
//
1057
// Decode of id_branch_op
1058
//
1059 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1060
        if (rst == `OR1200_RST_VALUE)
1061 350 julius
                id_branch_op <=  `OR1200_BRANCHOP_NOP;
1062
        else if (id_flushpipe)
1063
                id_branch_op <=  `OR1200_BRANCHOP_NOP;
1064
        else if (!id_freeze) begin
1065
                case (if_insn[31:26])           // synopsys parallel_case
1066
 
1067
                // l.j
1068
                `OR1200_OR32_J:
1069
                        id_branch_op <=  `OR1200_BRANCHOP_J;
1070
 
1071
                // j.jal
1072
                `OR1200_OR32_JAL:
1073
                        id_branch_op <=  `OR1200_BRANCHOP_J;
1074
 
1075
                // j.jalr
1076
                `OR1200_OR32_JALR:
1077
                        id_branch_op <=  `OR1200_BRANCHOP_JR;
1078
 
1079
                // l.jr
1080
                `OR1200_OR32_JR:
1081
                        id_branch_op <=  `OR1200_BRANCHOP_JR;
1082
 
1083
                // l.bnf
1084
                `OR1200_OR32_BNF:
1085
                        id_branch_op <=  `OR1200_BRANCHOP_BNF;
1086
 
1087
                // l.bf
1088
                `OR1200_OR32_BF:
1089
                        id_branch_op <=  `OR1200_BRANCHOP_BF;
1090
 
1091
                // l.rfe
1092
                `OR1200_OR32_RFE:
1093
                        id_branch_op <=  `OR1200_BRANCHOP_RFE;
1094
 
1095
                // Non branch instructions
1096
                default:
1097
                        id_branch_op <=  `OR1200_BRANCHOP_NOP;
1098
 
1099
                endcase
1100
        end
1101
end
1102
 
1103
//
1104
// Generation of ex_branch_op
1105
//
1106 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst)
1107
        if (rst == `OR1200_RST_VALUE)
1108 350 julius
                ex_branch_op <=  `OR1200_BRANCHOP_NOP;
1109
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1110
                ex_branch_op <=  `OR1200_BRANCHOP_NOP;
1111
        else if (!ex_freeze)
1112
                ex_branch_op <=  id_branch_op;
1113
 
1114
//
1115
// Decode of id_lsu_op
1116
//
1117
always @(id_insn) begin
1118
        case (id_insn[31:26])           // synopsys parallel_case
1119
 
1120
        // l.lwz
1121
        `OR1200_OR32_LWZ:
1122 353 julius
                id_lsu_op =  `OR1200_LSUOP_LWZ;
1123 350 julius
 
1124
        // l.lbz
1125
        `OR1200_OR32_LBZ:
1126 353 julius
                id_lsu_op =  `OR1200_LSUOP_LBZ;
1127 350 julius
 
1128
        // l.lbs
1129
        `OR1200_OR32_LBS:
1130 353 julius
                id_lsu_op =  `OR1200_LSUOP_LBS;
1131 350 julius
 
1132
        // l.lhz
1133
        `OR1200_OR32_LHZ:
1134 353 julius
                id_lsu_op =  `OR1200_LSUOP_LHZ;
1135 350 julius
 
1136
        // l.lhs
1137
        `OR1200_OR32_LHS:
1138 353 julius
                id_lsu_op =  `OR1200_LSUOP_LHS;
1139 350 julius
 
1140
        // l.sw
1141
        `OR1200_OR32_SW:
1142 353 julius
                id_lsu_op =  `OR1200_LSUOP_SW;
1143 350 julius
 
1144
        // l.sb
1145
        `OR1200_OR32_SB:
1146 353 julius
                id_lsu_op =  `OR1200_LSUOP_SB;
1147 350 julius
 
1148
        // l.sh
1149
        `OR1200_OR32_SH:
1150 353 julius
                id_lsu_op =  `OR1200_LSUOP_SH;
1151 350 julius
 
1152
        // Non load/store instructions
1153
        default:
1154 353 julius
                id_lsu_op =  `OR1200_LSUOP_NOP;
1155 350 julius
 
1156
        endcase
1157
end
1158
 
1159
//
1160
// Decode of comp_op
1161
//
1162 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1163
        if (rst == `OR1200_RST_VALUE) begin
1164 350 julius
                comp_op <=  4'd0;
1165
        end else if (!ex_freeze & id_freeze | ex_flushpipe)
1166
                comp_op <=  4'd0;
1167
        else if (!ex_freeze)
1168
                comp_op <=  id_insn[24:21];
1169
end
1170
 
1171
`ifdef OR1200_FPU_IMPLEMENTED
1172
//
1173
// Decode of FPU ops
1174
//
1175
   assign fpu_op = {(id_insn[31:26] == `OR1200_OR32_FLOAT),
1176
                    id_insn[`OR1200_FPUOP_WIDTH-2:0]};
1177
`else
1178
   assign fpu_op = {`OR1200_FPUOP_WIDTH{1'b0}};
1179
`endif
1180
 
1181
 
1182
//
1183
// Decode of l.sys
1184
//
1185 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1186
        if (rst == `OR1200_RST_VALUE)
1187 350 julius
                sig_syscall <=  1'b0;
1188
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1189
                sig_syscall <=  1'b0;
1190
        else if (!ex_freeze) begin
1191
`ifdef OR1200_VERBOSE
1192
// synopsys translate_off
1193
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000})
1194
                        $display("Generating sig_syscall");
1195
// synopsys translate_on
1196
`endif
1197
                sig_syscall <=  (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b000});
1198
        end
1199
end
1200
 
1201
//
1202
// Decode of l.trap
1203
//
1204 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1205
        if (rst == `OR1200_RST_VALUE)
1206 350 julius
                sig_trap <=  1'b0;
1207
        else if (!ex_freeze & id_freeze | ex_flushpipe)
1208
                sig_trap <=  1'b0;
1209
        else if (!ex_freeze) begin
1210
`ifdef OR1200_VERBOSE
1211
// synopsys translate_off
1212
                if (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
1213
                        $display("Generating sig_trap");
1214
// synopsys translate_on
1215
`endif
1216
                sig_trap <=  (id_insn[31:23] == {`OR1200_OR32_XSYNC, 3'b010})
1217
                        | du_hwbkpt;
1218
        end
1219
end
1220
 
1221
// Decode destination register address for data cache to check if store ops
1222
// are being done from the stack register (r1) or frame pointer register (r2)
1223
`ifdef OR1200_DC_NOSTACKWRITETHROUGH
1224 358 julius
always @(posedge clk or `OR1200_RST_EVENT rst) begin
1225
   if (rst == `OR1200_RST_VALUE)
1226 350 julius
     dc_no_writethrough <= 0;
1227
   else if (!ex_freeze)
1228
     dc_no_writethrough <= (id_insn[20:16] == 5'd1) | (id_insn[20:16] == 5'd2);
1229
end
1230
`else
1231
 
1232
   assign dc_no_writethrough = 0;
1233
 
1234
`endif
1235
 
1236
endmodule

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