OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_ram.v] - Blame information for rev 584

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  OR1200's DC RAMs                                            ////
4
////                                                              ////
5
////  This file is part of the OpenRISC 1200 project              ////
6
////  http://opencores.org/project,or1k                           ////
7
////                                                              ////
8
////  Description                                                 ////
9
////  Instatiation of DC RAM blocks.                              ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - make it smaller and faster                               ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Damjan Lampret, lampret@opencores.org                 ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
//
45
// $Log: or1200_dc_ram.v,v $
46
// Revision 2.0  2010/06/30 11:00:00  ORSoC
47
// Minor update: 
48
// Coding style changed.
49
//
50
 
51
// synopsys translate_off
52
`include "timescale.v"
53
// synopsys translate_on
54
`include "or1200_defines.v"
55
 
56
module or1200_dc_ram(
57
        // Reset and clock
58
        clk, rst,
59
 
60
`ifdef OR1200_BIST
61
        // RAM BIST
62
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
63
`endif
64
 
65
        // Internal i/f
66
        addr, en, we, datain, dataout
67
);
68
 
69
parameter dw = `OR1200_OPERAND_WIDTH;
70
parameter aw = `OR1200_DCINDX;
71
 
72
//
73
// I/O
74
//
75
input                           clk;
76
input                           rst;
77
input   [aw-1:0]         addr;
78
input                           en;
79
input   [3:0]                    we;
80
input   [dw-1:0]         datain;
81
output  [dw-1:0]         dataout;
82
 
83
`ifdef OR1200_BIST
84
//
85
// RAM BIST
86
//
87
input                           mbist_si_i;
88
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
89
output                          mbist_so_o;
90
`endif
91
 
92
`ifdef OR1200_NO_DC
93
 
94
//
95
// Data cache not implemented
96
//
97
assign dataout = {dw{1'b0}};
98
`ifdef OR1200_BIST
99
assign mbist_so_o = mbist_si_i;
100
`endif
101
 
102
`else
103
 
104
//
105
// Instantiation of RAM block
106
//
107
   or1200_spram_32_bw #
108
     (
109 477 julius
      .aw(`OR1200_DCINDX),
110
      .dw(dw)
111 350 julius
      )
112
   dc_ram
113
     (
114
`ifdef OR1200_BIST
115
      // RAM BIST
116
      .mbist_si_i(mbist_si_i),
117
      .mbist_so_o(mbist_so_o),
118
      .mbist_ctrl_i(mbist_ctrl_i),
119
`endif
120
      .clk(clk),
121
      .ce(en),
122
      .we(we),
123
      .addr(addr),
124
      .di(datain),
125
      .doq(dataout)
126
      );
127
`endif
128
 
129
endmodule // or1200_dc_ram

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.