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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_ram.v] - Blame information for rev 483

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's DC RAMs                                            ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://opencores.org/project,or1k                           ////
////                                                              ////
////  Description                                                 ////
////  Instatiation of DC RAM blocks.                              ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//
// $Log: or1200_dc_ram.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Coding style changed.
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
module or1200_dc_ram(
        // Reset and clock
        clk, rst,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
`ifdef OR1200_RAM_PARITY
        // Parity error indicator
        p_err,
`endif
        // Internal i/f
        addr, en, we, datain, dataout
 
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_DCINDX;
 
//
// I/O
//
input                           clk;
input                           rst;
input   [aw-1:0]         addr;
input                           en;
input   [3:0]                    we;
input   [dw-1:0]         datain;
output  [dw-1:0]         dataout;
`ifdef OR1200_RAM_PARITY
output                          p_err;
`endif
 
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input                           mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
output                          mbist_so_o;
`endif
 
`ifdef OR1200_NO_DC
 
//
// Data cache not implemented
//
assign dataout = {dw{1'b0}};
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`ifdef OR1200_RAM_PARITY
assign p_err = 0;
`endif
 
`else
 
//
// Instantiation of RAM block
//
   or1200_spram_32_bw #
     (
      .aw(`OR1200_DCINDX),
      .dw(dw)
      )
   dc_ram0
     (
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(mbist_si_i),
      .mbist_so_o(mbist_so_o),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
`ifdef OR1200_RAM_PARITY
      .p_err(p_err),
`endif
      .clk(clk),
      .rst(rst),
      .ce(en),
      .we(we),
      .addr(addr),
      .di(datain),
      .doq(dataout)
      );
`endif
 
endmodule // or1200_dc_ram

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's DC RAMs ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instatiation of DC RAM blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`//`
45			`// $Log: or1200_dc_ram.v,v $`
46			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
47			`// Minor update:`
48			`// Coding style changed.`
49			`//`
50
51			`// synopsys translate_off`
52			`include "timescale.v"
53			`// synopsys translate_on`
54			`include "or1200_defines.v"
55
56			`module or1200_dc_ram(`
57			`// Reset and clock`
58			`clk, rst,`
59
60			`ifdef OR1200_BIST
61			`// RAM BIST`
62			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
63			`endif
64	483	julius	`ifdef OR1200_RAM_PARITY
65			`// Parity error indicator`
66			`p_err,`
67			`endif
68	350	julius	`// Internal i/f`
69			`addr, en, we, datain, dataout`
70	483	julius
71	350	julius	`);`
72
73			parameter dw = `OR1200_OPERAND_WIDTH;
74			parameter aw = `OR1200_DCINDX;
75
76			`//`
77			`// I/O`
78			`//`
79			`input clk;`
80			`input rst;`
81			`input [aw-1:0] addr;`
82			`input en;`
83			`input [3:0] we;`
84			`input [dw-1:0] datain;`
85			`output [dw-1:0] dataout;`
86	483	julius	`ifdef OR1200_RAM_PARITY
87			`output p_err;`
88			`endif
89
90	350	julius
91			`ifdef OR1200_BIST
92			`//`
93			`// RAM BIST`
94			`//`
95			`input mbist_si_i;`
96			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control
97			`output mbist_so_o;`
98			`endif
99
100			`ifdef OR1200_NO_DC
101
102			`//`
103			`// Data cache not implemented`
104			`//`
105			`assign dataout = {dw{1'b0}};`
106			`ifdef OR1200_BIST
107			`assign mbist_so_o = mbist_si_i;`
108			`endif
109	483	julius	`ifdef OR1200_RAM_PARITY
110			`assign p_err = 0;`
111			`endif
112	350	julius
113			`else
114
115			`//`
116			`// Instantiation of RAM block`
117			`//`
118			`or1200_spram_32_bw #`
119			`(`
120	477	julius	.aw(`OR1200_DCINDX),
121			`.dw(dw)`
122	350	julius	`)`
123	483	julius	`dc_ram0`
124	350	julius	`(`
125			`ifdef OR1200_BIST
126			`// RAM BIST`
127			`.mbist_si_i(mbist_si_i),`
128			`.mbist_so_o(mbist_so_o),`
129			`.mbist_ctrl_i(mbist_ctrl_i),`
130			`endif
131	483	julius	`ifdef OR1200_RAM_PARITY
132			`.p_err(p_err),`
133			`endif
134	350	julius	`.clk(clk),`
135	483	julius	`.rst(rst),`
136	350	julius	`.ce(en),`
137			`.we(we),`
138			`.addr(addr),`
139			`.di(datain),`
140			`.doq(dataout)`
141			`);`
142			`endif
143
144			`endmodule // or1200_dc_ram`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_ram.v] - Blame information for rev 483