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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_top.v] - Blame information for rev 751

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Line No. Rev Author Line
1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  OR1200's Data Cache top level                               ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://opencores.org/project,or1k                           ////
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////                                                              ////
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////  Description                                                 ////
9
////  Instantiation of all DC blocks.                             ////
10
////                                                              ////
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////  To Do:                                                      ////
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////   - Test error during line read or write                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////      - Julius Baxter, julius@opencores.org                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
44
//
45
//
46
// $Log: or1200_dc_top.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Minor update: 
49
// Bugs fixed. 
50
//
51
 
52
// synopsys translate_off
53
`include "timescale.v"
54
// synopsys translate_on
55
`include "or1200_defines.v"
56
 
57
//
58
// Data cache
59
//
60
module or1200_dc_top(
61
        // Rst, clk and clock control
62
        clk, rst,
63
 
64
        // External i/f
65
        dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o,
66
        dcsb_cab_o, dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
67
 
68
        // Internal i/f
69
        dc_en,
70
        dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
71
        dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
72
        dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
73
 
74
        dc_no_writethrough,
75
 
76
`ifdef OR1200_BIST
77
        // RAM BIST
78
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
79
`endif
80
 
81
        // SPRs
82
        spr_cs, spr_write, spr_dat_i, spr_addr, mtspr_dc_done
83
);
84
 
85
parameter dw = `OR1200_OPERAND_WIDTH;
86
parameter aw = `OR1200_OPERAND_WIDTH;
87
 
88
//
89
// I/O
90
//
91
 
92
//
93
// Clock and reset
94
//
95
input                           clk;
96
input                           rst;
97
 
98
//
99
// External I/F
100
//
101
output  [dw-1:0]         dcsb_dat_o;
102
output  [31:0]                   dcsb_adr_o;
103
output                          dcsb_cyc_o;
104
output                          dcsb_stb_o;
105
output                          dcsb_we_o;
106
output  [3:0]                    dcsb_sel_o;
107
output                          dcsb_cab_o;
108
input   [dw-1:0]         dcsb_dat_i;
109
input                           dcsb_ack_i;
110
input                           dcsb_err_i;
111
 
112
//
113
// Internal I/F
114
//
115
input                           dc_en;
116
input   [31:0]                   dcqmem_adr_i;
117
input                           dcqmem_cycstb_i;
118
input                           dcqmem_ci_i;
119
input                           dcqmem_we_i;
120
input   [3:0]                    dcqmem_sel_i;
121
input   [3:0]                    dcqmem_tag_i;
122
input   [dw-1:0]         dcqmem_dat_i;
123
output  [dw-1:0]         dcqmem_dat_o;
124
output                          dcqmem_ack_o;
125
output                          dcqmem_rty_o;
126
output                          dcqmem_err_o;
127
output  [3:0]                    dcqmem_tag_o;
128
 
129
input                           dc_no_writethrough;
130
 
131
`ifdef OR1200_BIST
132
//
133
// RAM BIST
134
//
135
input mbist_si_i;
136
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
137
output mbist_so_o;
138
`endif
139
 
140
//
141
// SPR access
142
//
143
input                           spr_cs;
144
input                           spr_write;
145
input   [31:0]                   spr_dat_i;
146
input   [aw-1:0]         spr_addr;
147
output                          mtspr_dc_done;
148
 
149
`ifdef OR1200_NO_DC
150
 
151
// Bypass cache
152
 
153
// IF to external memory
154
assign dcsb_dat_o = dcqmem_dat_i;
155
assign dcsb_adr_o = dcqmem_adr_i;
156
assign dcsb_cyc_o = dcqmem_cycstb_i;
157
assign dcsb_stb_o = dcqmem_cycstb_i;
158
assign dcsb_we_o = dcqmem_we_i;
159
assign dcsb_sel_o = dcqmem_sel_i;
160
assign dcsb_cab_o = 1'b0;
161
 
162
// IF to internal memory
163
assign dcqmem_dat_o = dcsb_dat_i;
164
assign dcqmem_ack_o = dcsb_ack_i;
165
assign dcqmem_err_o = dcsb_err_i;
166
assign dcqmem_rty_o = ~dcqmem_ack_o;
167
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
168
 
169
assign mtspr_dc_done = 1'b1;
170
 
171
`else
172
 
173
//
174
// Internal wires and regs
175
//
176
wire                            tag_v;
177
wire    [`OR1200_DCTAG_W-2:0]    tag;
178
wire                            dirty;
179
wire    [dw-1:0]         to_dcram;
180
wire    [dw-1:0]         from_dcram;
181
wire    [3:0]                    dcram_we;
182
wire                            dctag_we;
183
wire    [31:0]                   dc_addr;
184
wire                            dcfsm_biu_read;
185
wire                            dcfsm_biu_write;
186
wire                            dcfsm_dcram_di_sel;
187
wire                            dcfsm_biu_do_sel;
188
reg                             tagcomp_miss;
189
wire    [`OR1200_DCINDXH:`OR1200_DCLS]  dctag_addr;
190
wire                            dctag_en;
191
wire                            dctag_v;
192
wire                            dctag_dirty;
193
 
194
wire                            dc_block_invalidate;
195
wire                            dc_block_flush;
196
wire                            dc_block_writeback;
197
wire                            dcfsm_first_hit_ack;
198
wire                            dcfsm_first_miss_ack;
199
wire                            dcfsm_first_miss_err;
200
wire                            dcfsm_burst;
201
wire                            dcfsm_tag_we;
202
wire                            dcfsm_tag_valid;
203
wire                            dcfsm_tag_dirty;
204
 
205
`ifdef OR1200_BIST
206
//
207
// RAM BIST
208
//
209
wire                            mbist_ram_so;
210
wire                            mbist_tag_so;
211
wire                            mbist_ram_si = mbist_si_i;
212
wire                            mbist_tag_si = mbist_ram_so;
213
assign                          mbist_so_o = mbist_tag_so;
214
`endif
215
 
216
// Address out to external bus - always from FSM   
217
assign dcsb_adr_o = dc_addr;
218
//
219
// SPR register decodes
220
//
221
`ifdef OR1200_DC_WRITETHROUGH
222
assign dc_block_invalidate = spr_cs & spr_write &
223
       ((spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBIR) |
224
        (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBFR));
225
assign dc_block_flush = 0;
226
assign dc_block_writeback = 0;
227
`else
228
assign dc_block_invalidate = spr_cs & spr_write &
229
          (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBIR);
230
assign dc_block_flush =    spr_cs & spr_write &
231
           (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBFR);
232
assign dc_block_writeback =    spr_cs & spr_write &
233
           (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBWR);
234
`endif // !`ifdef OR1200_DC_WRITETHROUGH
235
 
236
assign dctag_we = dcfsm_tag_we | dc_block_invalidate;
237
assign dctag_addr = dc_block_invalidate ?
238
                    spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] :
239
                    dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
240
assign dctag_en = dc_block_invalidate | dc_en;
241
 
242
assign dctag_v = dc_block_invalidate ? 1'b0 : dcfsm_tag_valid;
243
assign dctag_dirty = dc_block_invalidate ? 1'b0 : dcfsm_tag_dirty;
244
 
245
//
246
// Data to BIU is from DCRAM when bursting lines back into memory
247
//
248
assign dcsb_dat_o = dcfsm_biu_do_sel ? from_dcram : dcqmem_dat_i;
249
 
250
 
251
//
252
// Bypases of the DC when DC is disabled
253
//
254
assign dcsb_cyc_o = (dc_en) ?
255
                    dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
256
 
257
assign dcsb_stb_o = (dc_en) ?
258
                    dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
259
 
260
assign dcsb_we_o = (dc_en) ?
261
                   dcfsm_biu_write : dcqmem_we_i;
262
 
263
assign dcsb_sel_o = (dc_en & dcfsm_burst) ?
264
                    4'b1111 : dcqmem_sel_i;
265
 
266
assign dcsb_cab_o = dc_en & dcfsm_burst & dcsb_cyc_o;
267
assign dcqmem_rty_o = ~dcqmem_ack_o;
268
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
269
 
270
//
271
// DC/LSU normal and error termination
272
//
273
assign dcqmem_ack_o = dc_en ?
274
                      dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
275
 
276
assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
277
 
278
//
279
// Select between input data generated by LSU or by BIU
280
//
281
assign to_dcram = (dcfsm_dcram_di_sel) ? dcsb_dat_i : dcqmem_dat_i;
282
 
283
//
284
// Select between data generated by DCRAM or passed by BIU
285
//
286
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
287
 
288
//
289
// Tag comparison
290
//
291
   wire [31:`OR1200_DCTAGL]  dcqmem_adr_i_tag;
292
   assign dcqmem_adr_i_tag = dcqmem_adr_i[31:`OR1200_DCTAGL];
293
 
294 351 julius
always @(tag or dcqmem_adr_i_tag or tag_v) begin
295 350 julius
        if ((tag != dcqmem_adr_i_tag) || !tag_v)
296
                tagcomp_miss = 1'b1;
297
        else
298
                tagcomp_miss = 1'b0;
299
end
300
 
301
//
302
// Instantiation of DC Finite State Machine
303
//
304
or1200_dc_fsm or1200_dc_fsm(
305
        .clk(clk),
306
        .rst(rst),
307
        .dc_en(dc_en),
308
        .dcqmem_cycstb_i(dcqmem_cycstb_i),
309
        .dcqmem_ci_i(dcqmem_ci_i),
310
        .dcqmem_we_i(dcqmem_we_i),
311
        .dcqmem_sel_i(dcqmem_sel_i),
312
        .tagcomp_miss(tagcomp_miss),
313
        .tag(tag),
314
        .tag_v(tag_v),
315
        .dirty(dirty),
316
        .biudata_valid(dcsb_ack_i),
317
        .biudata_error(dcsb_err_i),
318
        .lsu_addr(dcqmem_adr_i),
319
        .dcram_we(dcram_we),
320
        .biu_read(dcfsm_biu_read),
321
        .biu_write(dcfsm_biu_write),
322
        .dcram_di_sel(dcfsm_dcram_di_sel),
323
        .biu_do_sel(dcfsm_biu_do_sel),
324
        .first_hit_ack(dcfsm_first_hit_ack),
325
        .first_miss_ack(dcfsm_first_miss_ack),
326
        .first_miss_err(dcfsm_first_miss_err),
327
        .burst(dcfsm_burst),
328
        .tag_we(dcfsm_tag_we),
329
        .tag_valid(dcfsm_tag_valid),
330
        .tag_dirty(dcfsm_tag_dirty),
331
        .dc_addr(dc_addr),
332
        .dc_no_writethrough(dc_no_writethrough),
333
        .dc_block_flush(dc_block_flush),
334
        .dc_block_writeback(dc_block_writeback),
335
        .spr_dat_i(spr_dat_i),
336
        .mtspr_dc_done(mtspr_dc_done),
337
        .spr_cswe(spr_cs & spr_write)
338
);
339
 
340
//
341
// Instantiation of DC main memory
342
//
343
or1200_dc_ram or1200_dc_ram(
344
        .clk(clk),
345
        .rst(rst),
346
`ifdef OR1200_BIST
347
        // RAM BIST
348
        .mbist_si_i(mbist_ram_si),
349
        .mbist_so_o(mbist_ram_so),
350
        .mbist_ctrl_i(mbist_ctrl_i),
351
`endif
352
        .addr(dc_addr[`OR1200_DCINDXH:2]),
353
        .en(dc_en),
354
        .we(dcram_we),
355
        .datain(to_dcram),
356
        .dataout(from_dcram)
357
);
358
 
359
//
360
// Instantiation of DC TAG memory
361
//
362
or1200_dc_tag or1200_dc_tag(
363
        .clk(clk),
364
        .rst(rst),
365
`ifdef OR1200_BIST
366
        // RAM BIST
367
        .mbist_si_i(mbist_tag_si),
368
        .mbist_so_o(mbist_tag_so),
369
        .mbist_ctrl_i(mbist_ctrl_i),
370
`endif
371
        .addr(dctag_addr),
372
        .en(dctag_en),
373
        .we(dctag_we),
374
        .datain({dc_addr[31:`OR1200_DCTAGL], dctag_v, dctag_dirty}),
375
        .tag_v(tag_v),
376
        .tag(tag),
377
        .dirty(dirty)
378
);
379
`endif // !`ifdef OR1200_NO_DC
380
 
381
endmodule

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