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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dc_top.v] - Blame information for rev 483

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1 350 julius
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  OR1200's Data Cache top level                               ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://opencores.org/project,or1k                           ////
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////                                                              ////
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////  Description                                                 ////
9
////  Instantiation of all DC blocks.                             ////
10
////                                                              ////
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////  To Do:                                                      ////
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////   - Test error during line read or write                     ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////      - Julius Baxter, julius@opencores.org                   ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000, 2010 Authors and OPENCORES.ORG           ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44
//
45
//
46
// $Log: or1200_dc_top.v,v $
47
// Revision 2.0  2010/06/30 11:00:00  ORSoC
48
// Minor update: 
49
// Bugs fixed. 
50
//
51
 
52
// synopsys translate_off
53
`include "timescale.v"
54
// synopsys translate_on
55
`include "or1200_defines.v"
56
 
57
//
58
// Data cache
59
//
60
module or1200_dc_top(
61
        // Rst, clk and clock control
62
        clk, rst,
63
 
64
        // External i/f
65
        dcsb_dat_o, dcsb_adr_o, dcsb_cyc_o, dcsb_stb_o, dcsb_we_o, dcsb_sel_o,
66
        dcsb_cab_o, dcsb_dat_i, dcsb_ack_i, dcsb_err_i,
67
 
68
        // Internal i/f
69
        dc_en,
70
        dcqmem_adr_i, dcqmem_cycstb_i, dcqmem_ci_i,
71
        dcqmem_we_i, dcqmem_sel_i, dcqmem_tag_i, dcqmem_dat_i,
72
        dcqmem_dat_o, dcqmem_ack_o, dcqmem_rty_o, dcqmem_err_o, dcqmem_tag_o,
73
 
74
        dc_no_writethrough,
75
 
76
`ifdef OR1200_BIST
77
        // RAM BIST
78
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
79
`endif
80 483 julius
 
81
`ifdef OR1200_RAM_PARITY
82
        // Parity error indicator
83
        p_err,
84
`endif
85
 
86 350 julius
        // SPRs
87
        spr_cs, spr_write, spr_dat_i, spr_addr, mtspr_dc_done
88
);
89
 
90
parameter dw = `OR1200_OPERAND_WIDTH;
91
parameter aw = `OR1200_OPERAND_WIDTH;
92
 
93
//
94
// I/O
95
//
96
 
97
//
98
// Clock and reset
99
//
100
input                           clk;
101
input                           rst;
102
 
103
//
104
// External I/F
105
//
106
output  [dw-1:0]         dcsb_dat_o;
107
output  [31:0]                   dcsb_adr_o;
108
output                          dcsb_cyc_o;
109
output                          dcsb_stb_o;
110
output                          dcsb_we_o;
111
output  [3:0]                    dcsb_sel_o;
112
output                          dcsb_cab_o;
113
input   [dw-1:0]         dcsb_dat_i;
114
input                           dcsb_ack_i;
115
input                           dcsb_err_i;
116
 
117
//
118
// Internal I/F
119
//
120
input                           dc_en;
121
input   [31:0]                   dcqmem_adr_i;
122
input                           dcqmem_cycstb_i;
123
input                           dcqmem_ci_i;
124
input                           dcqmem_we_i;
125
input   [3:0]                    dcqmem_sel_i;
126
input   [3:0]                    dcqmem_tag_i;
127
input   [dw-1:0]         dcqmem_dat_i;
128
output  [dw-1:0]         dcqmem_dat_o;
129
output                          dcqmem_ack_o;
130
output                          dcqmem_rty_o;
131
output                          dcqmem_err_o;
132
output  [3:0]                    dcqmem_tag_o;
133
 
134
input                           dc_no_writethrough;
135
 
136
`ifdef OR1200_BIST
137
//
138
// RAM BIST
139
//
140
input mbist_si_i;
141
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
142
output mbist_so_o;
143
`endif
144
 
145 483 julius
`ifdef OR1200_RAM_PARITY
146
output [1:0]                     p_err;
147
`endif
148
 
149 350 julius
//
150
// SPR access
151
//
152
input                           spr_cs;
153
input                           spr_write;
154
input   [31:0]                   spr_dat_i;
155
input   [aw-1:0]         spr_addr;
156
output                          mtspr_dc_done;
157
 
158
`ifdef OR1200_NO_DC
159
 
160
// Bypass cache
161
 
162
// IF to external memory
163
assign dcsb_dat_o = dcqmem_dat_i;
164
assign dcsb_adr_o = dcqmem_adr_i;
165
assign dcsb_cyc_o = dcqmem_cycstb_i;
166
assign dcsb_stb_o = dcqmem_cycstb_i;
167
assign dcsb_we_o = dcqmem_we_i;
168
assign dcsb_sel_o = dcqmem_sel_i;
169
assign dcsb_cab_o = 1'b0;
170
 
171
// IF to internal memory
172
assign dcqmem_dat_o = dcsb_dat_i;
173
assign dcqmem_ack_o = dcsb_ack_i;
174
assign dcqmem_err_o = dcsb_err_i;
175
assign dcqmem_rty_o = ~dcqmem_ack_o;
176
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
177
 
178
assign mtspr_dc_done = 1'b1;
179
 
180 483 julius
`ifdef OR1200_RAM_PARITY
181
assign p_err = 0;
182
`endif
183
 
184 350 julius
`else
185
 
186
//
187
// Internal wires and regs
188
//
189
wire                            tag_v;
190
wire    [`OR1200_DCTAG_W-2:0]    tag;
191
wire                            dirty;
192
wire    [dw-1:0]         to_dcram;
193
wire    [dw-1:0]         from_dcram;
194
wire    [3:0]                    dcram_we;
195
wire                            dctag_we;
196
wire    [31:0]                   dc_addr;
197
wire                            dcfsm_biu_read;
198
wire                            dcfsm_biu_write;
199
wire                            dcfsm_dcram_di_sel;
200
wire                            dcfsm_biu_do_sel;
201 483 julius
wire                            tagcomp_miss;
202 350 julius
wire    [`OR1200_DCINDXH:`OR1200_DCLS]  dctag_addr;
203
wire                            dctag_en;
204
wire                            dctag_v;
205
wire                            dctag_dirty;
206
 
207
wire                            dc_block_invalidate;
208
wire                            dc_block_flush;
209
wire                            dc_block_writeback;
210
wire                            dcfsm_first_hit_ack;
211
wire                            dcfsm_first_miss_ack;
212
wire                            dcfsm_first_miss_err;
213
wire                            dcfsm_burst;
214
wire                            dcfsm_tag_we;
215
wire                            dcfsm_tag_valid;
216
wire                            dcfsm_tag_dirty;
217
 
218
`ifdef OR1200_BIST
219
//
220
// RAM BIST
221
//
222
wire                            mbist_ram_so;
223
wire                            mbist_tag_so;
224
wire                            mbist_ram_si = mbist_si_i;
225
wire                            mbist_tag_si = mbist_ram_so;
226
assign                          mbist_so_o = mbist_tag_so;
227
`endif
228
 
229 483 julius
`ifdef OR1200_RAM_PARITY
230
wire [1:0]                       p_err_wire;
231
 
232
// Indicate an error if we're reading from the RAM (hit)
233
// Additionally, mask with tag_v as tag ram is properly cleared during
234
// init, whereas the data RAM is not.
235
assign p_err[0] = (dcqmem_ack_o & (!dcfsm_first_miss_ack | dc_en) &
236
                   !dcqmem_we_i) &
237
                  (tag_v & !p_err[1]) ? p_err_wire[0] : 0;
238
// Whenever there's a tag parity error and we have an instruction fetch
239
assign p_err[1] = (dctag_en & !dctag_we) ? p_err_wire[1] : 0;
240
 
241
 
242
`endif
243
 
244 350 julius
// Address out to external bus - always from FSM   
245
assign dcsb_adr_o = dc_addr;
246
//
247
// SPR register decodes
248
//
249
`ifdef OR1200_DC_WRITETHROUGH
250
assign dc_block_invalidate = spr_cs & spr_write &
251
       ((spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBIR) |
252
        (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBFR));
253
assign dc_block_flush = 0;
254
assign dc_block_writeback = 0;
255
`else
256
assign dc_block_invalidate = spr_cs & spr_write &
257
          (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBIR);
258
assign dc_block_flush =    spr_cs & spr_write &
259
           (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBFR);
260
assign dc_block_writeback =    spr_cs & spr_write &
261
           (spr_addr[`OR1200_SPRGRP_DC_ADR_WIDTH-1:0]==`OR1200_SPRGRP_DC_DCBWR);
262
`endif // !`ifdef OR1200_DC_WRITETHROUGH
263
 
264
assign dctag_we = dcfsm_tag_we | dc_block_invalidate;
265
assign dctag_addr = dc_block_invalidate ?
266
                    spr_dat_i[`OR1200_DCINDXH:`OR1200_DCLS] :
267
                    dc_addr[`OR1200_DCINDXH:`OR1200_DCLS];
268
assign dctag_en = dc_block_invalidate | dc_en;
269
 
270
assign dctag_v = dc_block_invalidate ? 1'b0 : dcfsm_tag_valid;
271
assign dctag_dirty = dc_block_invalidate ? 1'b0 : dcfsm_tag_dirty;
272
 
273
//
274
// Data to BIU is from DCRAM when bursting lines back into memory
275
//
276
assign dcsb_dat_o = dcfsm_biu_do_sel ? from_dcram : dcqmem_dat_i;
277
 
278
 
279
//
280
// Bypases of the DC when DC is disabled
281
//
282
assign dcsb_cyc_o = (dc_en) ?
283
                    dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
284
 
285
assign dcsb_stb_o = (dc_en) ?
286
                    dcfsm_biu_read | dcfsm_biu_write : dcqmem_cycstb_i;
287
 
288
assign dcsb_we_o = (dc_en) ?
289
                   dcfsm_biu_write : dcqmem_we_i;
290
 
291
assign dcsb_sel_o = (dc_en & dcfsm_burst) ?
292
                    4'b1111 : dcqmem_sel_i;
293
 
294
assign dcsb_cab_o = dc_en & dcfsm_burst & dcsb_cyc_o;
295
assign dcqmem_rty_o = ~dcqmem_ack_o;
296
assign dcqmem_tag_o = dcqmem_err_o ? `OR1200_DTAG_BE : dcqmem_tag_i;
297
 
298
//
299
// DC/LSU normal and error termination
300
//
301
assign dcqmem_ack_o = dc_en ?
302
                      dcfsm_first_hit_ack | dcfsm_first_miss_ack : dcsb_ack_i;
303
 
304
assign dcqmem_err_o = dc_en ? dcfsm_first_miss_err : dcsb_err_i;
305
 
306
//
307
// Select between input data generated by LSU or by BIU
308
//
309
assign to_dcram = (dcfsm_dcram_di_sel) ? dcsb_dat_i : dcqmem_dat_i;
310
 
311
//
312
// Select between data generated by DCRAM or passed by BIU
313
//
314
assign dcqmem_dat_o = dcfsm_first_miss_ack | !dc_en ? dcsb_dat_i : from_dcram;
315
 
316
//
317
// Tag comparison
318
//
319 483 julius
wire [31:`OR1200_DCTAGL]  dcqmem_adr_i_tag;
320
assign dcqmem_adr_i_tag = dcqmem_adr_i[31:`OR1200_DCTAGL];
321
/*
322 351 julius
always @(tag or dcqmem_adr_i_tag or tag_v) begin
323 483 julius
        if ((tag != dcqmem_adr_i_tag) || !tag_v
324
`ifdef OR1200_RAM_PARITY
325
              | p_err
326
`endif
327
)
328 350 julius
                tagcomp_miss = 1'b1;
329
        else
330
                tagcomp_miss = 1'b0;
331
end
332 483 julius
*/
333
assign tagcomp_miss = (tag != dcqmem_adr_i_tag) | !tag_v
334
`ifdef OR1200_RAM_PARITY
335
                       | (|p_err_wire)
336
`endif
337
                       ;
338 350 julius
//
339
// Instantiation of DC Finite State Machine
340
//
341
or1200_dc_fsm or1200_dc_fsm(
342
        .clk(clk),
343
        .rst(rst),
344
        .dc_en(dc_en),
345
        .dcqmem_cycstb_i(dcqmem_cycstb_i),
346
        .dcqmem_ci_i(dcqmem_ci_i),
347
        .dcqmem_we_i(dcqmem_we_i),
348
        .dcqmem_sel_i(dcqmem_sel_i),
349
        .tagcomp_miss(tagcomp_miss),
350
        .tag(tag),
351
        .tag_v(tag_v),
352
        .dirty(dirty),
353
        .biudata_valid(dcsb_ack_i),
354
        .biudata_error(dcsb_err_i),
355
        .lsu_addr(dcqmem_adr_i),
356
        .dcram_we(dcram_we),
357
        .biu_read(dcfsm_biu_read),
358
        .biu_write(dcfsm_biu_write),
359
        .dcram_di_sel(dcfsm_dcram_di_sel),
360
        .biu_do_sel(dcfsm_biu_do_sel),
361
        .first_hit_ack(dcfsm_first_hit_ack),
362
        .first_miss_ack(dcfsm_first_miss_ack),
363
        .first_miss_err(dcfsm_first_miss_err),
364
        .burst(dcfsm_burst),
365
        .tag_we(dcfsm_tag_we),
366
        .tag_valid(dcfsm_tag_valid),
367
        .tag_dirty(dcfsm_tag_dirty),
368
        .dc_addr(dc_addr),
369
        .dc_no_writethrough(dc_no_writethrough),
370
        .dc_block_flush(dc_block_flush),
371
        .dc_block_writeback(dc_block_writeback),
372
        .spr_dat_i(spr_dat_i),
373
        .mtspr_dc_done(mtspr_dc_done),
374
        .spr_cswe(spr_cs & spr_write)
375
);
376
 
377
//
378
// Instantiation of DC main memory
379
//
380
or1200_dc_ram or1200_dc_ram(
381
        .clk(clk),
382
        .rst(rst),
383
`ifdef OR1200_BIST
384
        // RAM BIST
385
        .mbist_si_i(mbist_ram_si),
386
        .mbist_so_o(mbist_ram_so),
387
        .mbist_ctrl_i(mbist_ctrl_i),
388
`endif
389 483 julius
`ifdef OR1200_RAM_PARITY
390
        .p_err(p_err_wire[0]),
391
`endif
392 350 julius
        .addr(dc_addr[`OR1200_DCINDXH:2]),
393
        .en(dc_en),
394
        .we(dcram_we),
395
        .datain(to_dcram),
396
        .dataout(from_dcram)
397
);
398
 
399
//
400
// Instantiation of DC TAG memory
401
//
402
or1200_dc_tag or1200_dc_tag(
403
        .clk(clk),
404
        .rst(rst),
405
`ifdef OR1200_BIST
406
        // RAM BIST
407
        .mbist_si_i(mbist_tag_si),
408
        .mbist_so_o(mbist_tag_so),
409
        .mbist_ctrl_i(mbist_ctrl_i),
410
`endif
411 483 julius
`ifdef OR1200_RAM_PARITY
412
        .p_err(p_err_wire[1]),
413
`endif
414 350 julius
        .addr(dctag_addr),
415
        .en(dctag_en),
416
        .we(dctag_we),
417
        .datain({dc_addr[31:`OR1200_DCTAGL], dctag_v, dctag_dirty}),
418
        .tag_v(tag_v),
419
        .tag(tag),
420
        .dirty(dirty)
421
);
422
`endif // !`ifdef OR1200_NO_DC
423
 
424
endmodule

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