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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dmmu_tlb.v] - Blame information for rev 522

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Data TLB                                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of DTLB.                                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//
// $Log: or1200_dmmu_tlb.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Bugs fixed, coding style changed. 
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Data TLB
//
 
module or1200_dmmu_tlb(
        // Rst and clk
        clk, rst,
 
        // I/F for translation
        tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// I/F for translation
//
input                           tlb_en;
input   [aw-1:0]         vaddr;
output                          hit;
output  [31:`OR1200_DMMU_PS]    ppn;
output                          uwe;
output                          ure;
output                          swe;
output                          sre;
output                          ci;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [`OR1200_DTLB_TAG]      vpn;
wire                            v;
wire    [`OR1200_DTLB_INDXW-1:0] tlb_index;
wire                            tlb_mr_en;
wire                            tlb_mr_we;
wire    [`OR1200_DTLBMRW-1:0]    tlb_mr_ram_in;
wire    [`OR1200_DTLBMRW-1:0]    tlb_mr_ram_out;
wire                            tlb_tr_en;
wire                            tlb_tr_we;
wire    [`OR1200_DTLBTRW-1:0]    tlb_tr_ram_in;
wire    [`OR1200_DTLBTRW-1:0]    tlb_tr_ram_out;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire                            mbist_mr_so;
wire                            mbist_tr_so;
wire                            mbist_mr_si = mbist_si_i;
wire                            mbist_tr_si = mbist_mr_so;
assign                          mbist_so_o = mbist_tr_so;
`endif
 
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-19  v 0
// dtlbwYtrX: ppn 31-13  swe 9  sre 8  uwe 7  ure 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
// 1 bit for cache inhibit
 
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]);
 
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR];
 
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]);
 
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR];
 
//
// Output to SPRS unit
//
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
                        {vpn, tlb_index, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
                (spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
                        {ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
                        32'h00000000;
 
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out;
 
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
 
//
// Assign outputs from Translate registers
//
assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out;
 
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS],
                        spr_dat_i[`OR1200_DTLBTR_SWE_BITS],
                        spr_dat_i[`OR1200_DTLBTR_SRE_BITS],
                        spr_dat_i[`OR1200_DTLBTR_UWE_BITS],
                        spr_dat_i[`OR1200_DTLBTR_URE_BITS],
                        spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
 
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v;
 
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
 
//
// Instantiation of DTLB Match Registers
//
//or1200_spram_64x14 dtlb_mr_ram(
   or1200_spram #
     (
      .aw(6),
      .dw(14)
      )
   dtlb_ram
     (
      .clk(clk),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(mbist_mr_si),
      .mbist_so_o(mbist_mr_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .ce(tlb_mr_en),
      .we(tlb_mr_we),
      .addr(tlb_index),
      .di(tlb_mr_ram_in),
      .doq(tlb_mr_ram_out)
      );
 
   //
   // Instantiation of DTLB Translate Registers
   //
   //or1200_spram_64x24 dtlb_tr_ram(
   or1200_spram #
     (
      .aw(6),
      .dw(24)
      )
   dtlb_tr_ram
     (
      .clk(clk),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(mbist_tr_si),
      .mbist_so_o(mbist_tr_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .ce(tlb_tr_en),
      .we(tlb_tr_we),
      .addr(tlb_index),
      .di(tlb_tr_ram_in),
      .doq(tlb_tr_ram_out)
      );
 
endmodule // or1200_dmmu_tlb

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dmmu_tlb.v] - Blame information for rev 522

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Data TLB ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of DTLB. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`//`
45			`// $Log: or1200_dmmu_tlb.v,v $`
46			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
47			`// Minor update:`
48			`// Bugs fixed, coding style changed.`
49			`//`
50
51			`// synopsys translate_off`
52			`include "timescale.v"
53			`// synopsys translate_on`
54			`include "or1200_defines.v"
55
56			`//`
57			`// Data TLB`
58			`//`
59
60			`module or1200_dmmu_tlb(`
61			`// Rst and clk`
62			`clk, rst,`
63
64			`// I/F for translation`
65			`tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,`
66
67			`ifdef OR1200_BIST
68			`// RAM BIST`
69			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
70			`endif
71
72			`// SPR access`
73			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
74			`);`
75
76			parameter dw = `OR1200_OPERAND_WIDTH;
77			parameter aw = `OR1200_OPERAND_WIDTH;
78
79			`//`
80			`// I/O`
81			`//`
82
83			`//`
84			`// Clock and reset`
85			`//`
86			`input clk;`
87			`input rst;`
88
89			`//`
90			`// I/F for translation`
91			`//`
92			`input tlb_en;`
93			`input [aw-1:0] vaddr;`
94			`output hit;`
95			output [31:`OR1200_DMMU_PS] ppn;
96			`output uwe;`
97			`output ure;`
98			`output swe;`
99			`output sre;`
100			`output ci;`
101
102			`ifdef OR1200_BIST
103			`//`
104			`// RAM BIST`
105			`//`
106			`input mbist_si_i;`
107			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
108			`output mbist_so_o;`
109			`endif
110
111			`//`
112			`// SPR access`
113			`//`
114			`input spr_cs;`
115			`input spr_write;`
116			`input [31:0] spr_addr;`
117			`input [31:0] spr_dat_i;`
118			`output [31:0] spr_dat_o;`
119
120			`//`
121			`// Internal wires and regs`
122			`//`
123			wire [`OR1200_DTLB_TAG] vpn;
124			`wire v;`
125			wire [`OR1200_DTLB_INDXW-1:0] tlb_index;
126			`wire tlb_mr_en;`
127			`wire tlb_mr_we;`
128			wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_in;
129			wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
130			`wire tlb_tr_en;`
131			`wire tlb_tr_we;`
132			wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
133			wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
134			`ifdef OR1200_BIST
135			`//`
136			`// RAM BIST`
137			`//`
138			`wire mbist_mr_so;`
139			`wire mbist_tr_so;`
140			`wire mbist_mr_si = mbist_si_i;`
141			`wire mbist_tr_si = mbist_mr_so;`
142			`assign mbist_so_o = mbist_tr_so;`
143			`endif
144
145			`//`
146			`// Implemented bits inside match and translate registers`
147			`//`
148			`// dtlbwYmrX: vpn 31-19 v 0`
149			`// dtlbwYtrX: ppn 31-13 swe 9 sre 8 uwe 7 ure 6`
150			`//`
151			`// dtlb memory width:`
152			`// 19 bits for ppn`
153			`// 13 bits for vpn`
154			`// 1 bit for valid`
155			`// 4 bits for protection`
156			`// 1 bit for cache inhibit`
157
158			`//`
159			`// Enable for Match registers`
160			`//`
161			assign tlb_mr_en = tlb_en \| (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]);
162
163			`//`
164			`// Write enable for Match registers`
165			`//`
166			assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR];
167
168			`//`
169			`// Enable for Translate registers`
170			`//`
171			assign tlb_tr_en = tlb_en \| (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]);
172
173			`//`
174			`// Write enable for Translate registers`
175			`//`
176			assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR];
177
178			`//`
179			`// Output to SPRS unit`
180			`//`
181			assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
182			{vpn, tlb_index, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
183			(spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
184			{ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
185			`32'h00000000;`
186
187			`//`
188			`// Assign outputs from Match registers`
189			`//`
190			`assign {vpn, v} = tlb_mr_ram_out;`
191
192			`//`
193			`// Assign to Match registers inputs`
194			`//`
195			assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
196
197			`//`
198			`// Assign outputs from Translate registers`
199			`//`
200			`assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out;`
201
202			`//`
203			`// Assign to Translate registers inputs`
204			`//`
205			assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS],
206			spr_dat_i[`OR1200_DTLBTR_SWE_BITS],
207			spr_dat_i[`OR1200_DTLBTR_SRE_BITS],
208			spr_dat_i[`OR1200_DTLBTR_UWE_BITS],
209			spr_dat_i[`OR1200_DTLBTR_URE_BITS],
210			spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
211
212			`//`
213			`// Generate hit`
214			`//`
215			assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v;
216
217			`//`
218			`// TLB index is normally vaddr[18:13]. If it is SPR access then index is`
219			`// spr_addr[5:0].`
220			`//`
221			assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] : vaddr[`OR1200_DTLB_INDX];
222
223			`//`
224			`// Instantiation of DTLB Match Registers`
225			`//`
226			`//or1200_spram_64x14 dtlb_mr_ram(`
227			`or1200_spram #`
228			`(`
229			`.aw(6),`
230			`.dw(14)`
231			`)`
232			`dtlb_ram`
233			`(`
234			`.clk(clk),`
235			`ifdef OR1200_BIST
236			`// RAM BIST`
237			`.mbist_si_i(mbist_mr_si),`
238			`.mbist_so_o(mbist_mr_so),`
239			`.mbist_ctrl_i(mbist_ctrl_i),`
240			`endif
241			`.ce(tlb_mr_en),`
242			`.we(tlb_mr_we),`
243			`.addr(tlb_index),`
244			`.di(tlb_mr_ram_in),`
245			`.doq(tlb_mr_ram_out)`
246			`);`
247
248			`//`
249			`// Instantiation of DTLB Translate Registers`
250			`//`
251			`//or1200_spram_64x24 dtlb_tr_ram(`
252			`or1200_spram #`
253			`(`
254			`.aw(6),`
255			`.dw(24)`
256			`)`
257			`dtlb_tr_ram`
258			`(`
259			`.clk(clk),`
260			`ifdef OR1200_BIST
261			`// RAM BIST`
262			`.mbist_si_i(mbist_tr_si),`
263			`.mbist_so_o(mbist_tr_so),`
264			`.mbist_ctrl_i(mbist_ctrl_i),`
265			`endif
266			`.ce(tlb_tr_en),`
267			`.we(tlb_tr_we),`
268			`.addr(tlb_index),`
269			`.di(tlb_tr_ram_in),`
270			`.doq(tlb_tr_ram_out)`
271			`);`
272
273			`endmodule // or1200_dmmu_tlb`