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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Data TLB                                           ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of DTLB.                                      ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
//
// $Log: or1200_dmmu_tlb.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Bugs fixed, coding style changed. 
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Data TLB
//
 
module or1200_dmmu_tlb(
        // Rst and clk
        clk, rst,
 
        // I/F for translation
        tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
`ifdef OR1200_RAM_PARITY
        // Parity error indicator
        p_err,
`endif
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// I/F for translation
//
input                           tlb_en;
input   [aw-1:0]         vaddr;
output                          hit;
output  [31:`OR1200_DMMU_PS]    ppn;
output                          uwe;
output                          ure;
output                          swe;
output                          sre;
output                          ci;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
`ifdef OR1200_RAM_PARITY
output [1:0]                     p_err;
`endif
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [31:0]                   spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
//
// Internal wires and regs
//
wire    [`OR1200_DTLB_TAG]      vpn;
wire                            v;
wire    [`OR1200_DTLB_INDXW-1:0] tlb_index;
wire                            tlb_mr_en;
wire                            tlb_mr_we;
wire    [`OR1200_DTLBMRW-1:0]    tlb_mr_ram_in;
`ifdef OR1200_RAM_PARITY
wire    [`OR1200_DTLBMRW-1+2:0]  tlb_mr_ram_out;
`else
wire    [`OR1200_DTLBMRW-1:0]    tlb_mr_ram_out;
`endif
wire                            tlb_tr_en;
wire                            tlb_tr_we;
wire    [`OR1200_DTLBTRW-1:0]    tlb_tr_ram_in;
wire    [`OR1200_DTLBTRW-1:0]    tlb_tr_ram_out;
`ifdef OR1200_BIST
//
// RAM BIST
//
wire                            mbist_mr_so;
wire                            mbist_tr_so;
wire                            mbist_mr_si = mbist_si_i;
wire                            mbist_tr_si = mbist_mr_so;
assign                          mbist_so_o = mbist_tr_so;
`endif
 
`ifdef OR1200_RAM_PARITY
wire [1:0]                       p_err_wire;
reg                             p_err_en;
`endif
 
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-19  v 0
// dtlbwYtrX: ppn 31-13  swe 9  sre 8  uwe 7  ure 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
// 1 bit for cache inhibit
 
//
// Enable for Match registers
//
assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]);
 
//
// Write enable for Match registers
//
assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR];
 
//
// Enable for Translate registers
//
assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]);
 
//
// Write enable for Translate registers
//
assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR];
 
//
// Output to SPRS unit
//
assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
                        {vpn, tlb_index, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
                (spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
                        {ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
                        32'h00000000;
 
//
// Assign outputs from Match registers
//
assign {vpn, v} = tlb_mr_ram_out[`OR1200_DTLBMRW-1:0];
 
//
// Assign to Match registers inputs
//
assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
 
//
// Assign outputs from Translate registers
//
assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out;
 
//
// Assign to Translate registers inputs
//
assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS],
                        spr_dat_i[`OR1200_DTLBTR_SWE_BITS],
                        spr_dat_i[`OR1200_DTLBTR_SRE_BITS],
                        spr_dat_i[`OR1200_DTLBTR_UWE_BITS],
                        spr_dat_i[`OR1200_DTLBTR_URE_BITS],
                        spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
 
//
// Generate hit
//
assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v
             `ifdef OR1200_RAM_PARITY
                         & !p_err
`endif
                           ;
 
//
// TLB index is normally vaddr[18:13]. If it is SPR access then index is
// spr_addr[5:0].
//
assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] :
                   vaddr[`OR1200_DTLB_INDX];
 
`ifdef OR1200_RAM_PARITY
   always @(posedge clk)
     if (rst)
       p_err_en <= 0;
     else
       p_err_en <= (tlb_mr_en & !tlb_mr_we) | (tlb_tr_en & !tlb_tr_we);
 
   assign p_err = (p_err_en & (tlb_mr_en & !tlb_mr_we) |
                   (tlb_tr_en & !tlb_tr_we)) ? p_err_wire : 0;
`endif
 
 
//
// Instantiation of DTLB Match Registers
//
//or1200_spram_64x14 dtlb_mr_ram(
   or1200_spram #
     (
      .aw(6),
 `ifdef OR1200_RAM_PARITY
      .dw(16)
 `else
      .dw(14)
 `endif
      )
   dtlb_mr_ram
     (
      .clk(clk),
      .rst(rst),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(mbist_mr_si),
      .mbist_so_o(mbist_mr_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
      .ce(tlb_mr_en),
      .we(tlb_mr_we),
      .addr(tlb_index),
`ifdef OR1200_RAM_PARITY
      .p_err(p_err_wire[0]),
      .di({2'b00,tlb_mr_ram_in}),
`else
      .di(tlb_mr_ram_in),
`endif
      .doq(tlb_mr_ram_out)
      );
 
   //
   // Instantiation of DTLB Translate Registers
   //
   or1200_spram #
     (
      .aw(6),
      .dw(24)
      )
   dtlb_tr_ram
     (
      .clk(clk),
      .rst(rst),
`ifdef OR1200_BIST
      // RAM BIST
      .mbist_si_i(mbist_tr_si),
      .mbist_so_o(mbist_tr_so),
      .mbist_ctrl_i(mbist_ctrl_i),
`endif
`ifdef OR1200_RAM_PARITY
      .p_err(p_err_wire[1]),
`endif
      .ce(tlb_tr_en),
      .we(tlb_tr_we),
      .addr(tlb_index),
      .di(tlb_tr_ram_in),
      .doq(tlb_tr_ram_out)
      );
 
endmodule // or1200_dmmu_tlb

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Data TLB ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of DTLB. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`//`
45			`// $Log: or1200_dmmu_tlb.v,v $`
46			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
47			`// Minor update:`
48			`// Bugs fixed, coding style changed.`
49			`//`
50
51			`// synopsys translate_off`
52			`include "timescale.v"
53			`// synopsys translate_on`
54			`include "or1200_defines.v"
55
56			`//`
57			`// Data TLB`
58			`//`
59
60			`module or1200_dmmu_tlb(`
61			`// Rst and clk`
62			`clk, rst,`
63
64			`// I/F for translation`
65			`tlb_en, vaddr, hit, ppn, uwe, ure, swe, sre, ci,`
66
67			`ifdef OR1200_BIST
68			`// RAM BIST`
69			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
70			`endif
71
72	483	julius	`ifdef OR1200_RAM_PARITY
73			`// Parity error indicator`
74			`p_err,`
75			`endif
76
77	350	julius	`// SPR access`
78			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o`
79			`);`
80
81			parameter dw = `OR1200_OPERAND_WIDTH;
82			parameter aw = `OR1200_OPERAND_WIDTH;
83
84			`//`
85			`// I/O`
86			`//`
87
88			`//`
89			`// Clock and reset`
90			`//`
91			`input clk;`
92			`input rst;`
93
94			`//`
95			`// I/F for translation`
96			`//`
97			`input tlb_en;`
98			`input [aw-1:0] vaddr;`
99			`output hit;`
100			output [31:`OR1200_DMMU_PS] ppn;
101			`output uwe;`
102			`output ure;`
103			`output swe;`
104			`output sre;`
105			`output ci;`
106
107			`ifdef OR1200_BIST
108			`//`
109			`// RAM BIST`
110			`//`
111			`input mbist_si_i;`
112			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
113			`output mbist_so_o;`
114			`endif
115
116	483	julius	`ifdef OR1200_RAM_PARITY
117			`output [1:0] p_err;`
118			`endif
119
120	350	julius	`//`
121			`// SPR access`
122			`//`
123			`input spr_cs;`
124			`input spr_write;`
125			`input [31:0] spr_addr;`
126			`input [31:0] spr_dat_i;`
127			`output [31:0] spr_dat_o;`
128
129			`//`
130			`// Internal wires and regs`
131			`//`
132			wire [`OR1200_DTLB_TAG] vpn;
133			`wire v;`
134			wire [`OR1200_DTLB_INDXW-1:0] tlb_index;
135			`wire tlb_mr_en;`
136			`wire tlb_mr_we;`
137			wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_in;
138	483	julius	`ifdef OR1200_RAM_PARITY
139			wire [`OR1200_DTLBMRW-1+2:0] tlb_mr_ram_out;
140			`else
141	350	julius	wire [`OR1200_DTLBMRW-1:0] tlb_mr_ram_out;
142	483	julius	`endif
143	350	julius	`wire tlb_tr_en;`
144			`wire tlb_tr_we;`
145			wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_in;
146			wire [`OR1200_DTLBTRW-1:0] tlb_tr_ram_out;
147			`ifdef OR1200_BIST
148			`//`
149			`// RAM BIST`
150			`//`
151			`wire mbist_mr_so;`
152			`wire mbist_tr_so;`
153			`wire mbist_mr_si = mbist_si_i;`
154			`wire mbist_tr_si = mbist_mr_so;`
155			`assign mbist_so_o = mbist_tr_so;`
156			`endif
157
158	483	julius	`ifdef OR1200_RAM_PARITY
159			`wire [1:0] p_err_wire;`
160			`reg p_err_en;`
161			`endif
162
163	350	julius	`//`
164			`// Implemented bits inside match and translate registers`
165			`//`
166			`// dtlbwYmrX: vpn 31-19 v 0`
167			`// dtlbwYtrX: ppn 31-13 swe 9 sre 8 uwe 7 ure 6`
168			`//`
169			`// dtlb memory width:`
170			`// 19 bits for ppn`
171			`// 13 bits for vpn`
172			`// 1 bit for valid`
173			`// 4 bits for protection`
174			`// 1 bit for cache inhibit`
175
176			`//`
177			`// Enable for Match registers`
178			`//`
179			assign tlb_mr_en = tlb_en \| (spr_cs & !spr_addr[`OR1200_DTLB_TM_ADDR]);
180
181			`//`
182			`// Write enable for Match registers`
183			`//`
184			assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR];
185
186			`//`
187			`// Enable for Translate registers`
188			`//`
189			assign tlb_tr_en = tlb_en \| (spr_cs & spr_addr[`OR1200_DTLB_TM_ADDR]);
190
191			`//`
192			`// Write enable for Translate registers`
193			`//`
194			assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_DTLB_TM_ADDR];
195
196			`//`
197			`// Output to SPRS unit`
198			`//`
199			assign spr_dat_o = (spr_cs & !spr_write & !spr_addr[`OR1200_DTLB_TM_ADDR]) ?
200			{vpn, tlb_index, {`OR1200_DTLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
201			(spr_cs & !spr_write & spr_addr[`OR1200_DTLB_TM_ADDR]) ?
202			{ppn, {`OR1200_DMMU_PS-10{1'b0}}, swe, sre, uwe, ure, {4{1'b0}}, ci, 1'b0} :
203			`32'h00000000;`
204
205			`//`
206			`// Assign outputs from Match registers`
207			`//`
208	483	julius	assign {vpn, v} = tlb_mr_ram_out[`OR1200_DTLBMRW-1:0];
209	350	julius
210			`//`
211			`// Assign to Match registers inputs`
212			`//`
213			assign tlb_mr_ram_in = {spr_dat_i[`OR1200_DTLB_TAG], spr_dat_i[`OR1200_DTLBMR_V_BITS]};
214
215			`//`
216			`// Assign outputs from Translate registers`
217			`//`
218			`assign {ppn, swe, sre, uwe, ure, ci} = tlb_tr_ram_out;`
219
220			`//`
221			`// Assign to Translate registers inputs`
222			`//`
223			assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_DMMU_PS],
224			spr_dat_i[`OR1200_DTLBTR_SWE_BITS],
225			spr_dat_i[`OR1200_DTLBTR_SRE_BITS],
226			spr_dat_i[`OR1200_DTLBTR_UWE_BITS],
227			spr_dat_i[`OR1200_DTLBTR_URE_BITS],
228			spr_dat_i[`OR1200_DTLBTR_CI_BITS]};
229
230			`//`
231			`// Generate hit`
232			`//`
233	483	julius	assign hit = (vpn == vaddr[`OR1200_DTLB_TAG]) & v
234			`ifdef OR1200_RAM_PARITY
235			`& !p_err`
236			`endif
237			`;`
238	350	julius
239			`//`
240			`// TLB index is normally vaddr[18:13]. If it is SPR access then index is`
241			`// spr_addr[5:0].`
242			`//`
243	483	julius	assign tlb_index = spr_cs ? spr_addr[`OR1200_DTLB_INDXW-1:0] :
244			vaddr[`OR1200_DTLB_INDX];
245	350	julius
246	483	julius	`ifdef OR1200_RAM_PARITY
247			`always @(posedge clk)`
248			`if (rst)`
249			`p_err_en <= 0;`
250			`else`
251			`p_err_en <= (tlb_mr_en & !tlb_mr_we) \| (tlb_tr_en & !tlb_tr_we);`
252
253			`assign p_err = (p_err_en & (tlb_mr_en & !tlb_mr_we) \|`
254			`(tlb_tr_en & !tlb_tr_we)) ? p_err_wire : 0;`
255			`endif
256
257
258	350	julius	`//`
259			`// Instantiation of DTLB Match Registers`
260			`//`
261			`//or1200_spram_64x14 dtlb_mr_ram(`
262			`or1200_spram #`
263			`(`
264			`.aw(6),`
265	483	julius	`ifdef OR1200_RAM_PARITY
266			`.dw(16)`
267			`else
268	350	julius	`.dw(14)`
269	483	julius	`endif
270	350	julius	`)`
271	483	julius	`dtlb_mr_ram`
272	350	julius	`(`
273			`.clk(clk),`
274	483	julius	`.rst(rst),`
275	350	julius	`ifdef OR1200_BIST
276			`// RAM BIST`
277			`.mbist_si_i(mbist_mr_si),`
278			`.mbist_so_o(mbist_mr_so),`
279			`.mbist_ctrl_i(mbist_ctrl_i),`
280			`endif
281			`.ce(tlb_mr_en),`
282			`.we(tlb_mr_we),`
283			`.addr(tlb_index),`
284	483	julius	`ifdef OR1200_RAM_PARITY
285			`.p_err(p_err_wire[0]),`
286			`.di({2'b00,tlb_mr_ram_in}),`
287			`else
288	350	julius	`.di(tlb_mr_ram_in),`
289	483	julius	`endif
290	350	julius	`.doq(tlb_mr_ram_out)`
291			`);`
292
293			`//`
294			`// Instantiation of DTLB Translate Registers`
295			`//`
296			`or1200_spram #`
297			`(`
298			`.aw(6),`
299			`.dw(24)`
300			`)`
301			`dtlb_tr_ram`
302			`(`
303			`.clk(clk),`
304	483	julius	`.rst(rst),`
305	350	julius	`ifdef OR1200_BIST
306			`// RAM BIST`
307			`.mbist_si_i(mbist_tr_si),`
308			`.mbist_so_o(mbist_tr_so),`
309			`.mbist_ctrl_i(mbist_ctrl_i),`
310			`endif
311	483	julius	`ifdef OR1200_RAM_PARITY
312			`.p_err(p_err_wire[1]),`
313			`endif
314	350	julius	`.ce(tlb_tr_en),`
315			`.we(tlb_tr_we),`
316			`.addr(tlb_index),`
317	483	julius	`.di(tlb_tr_ram_in),`
318	350	julius	`.doq(tlb_tr_ram_out)`
319			`);`
320
321			`endmodule // or1200_dmmu_tlb`

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dmmu_tlb.v] - Blame information for rev 483