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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dmmu_top.v] - Blame information for rev 751

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Data MMU top level                                 ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Instantiation of all DMMU blocks.                           ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_dmmu_top.v,v $
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Minor update: 
// Bugs fixed. 
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
//
// Data MMU
//
 
module or1200_dmmu_top(
        // Rst and clk
        clk, rst,
 
        // CPU i/f
        dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i,
        dcpu_tag_o, dcpu_err_o,
 
        // SPR access
        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
 
`ifdef OR1200_BIST
        // RAM BIST
        mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
 
        // DC i/f
        qmemdmmu_err_i, qmemdmmu_tag_i, qmemdmmu_adr_o, qmemdmmu_cycstb_o, qmemdmmu_ci_o
);
 
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
 
//
// I/O
//
 
//
// Clock and reset
//
input                           clk;
input                           rst;
 
//
// CPU I/F
//
input                           dc_en;
input                           dmmu_en;
input                           supv;
input   [aw-1:0]         dcpu_adr_i;
input                           dcpu_cycstb_i;
input                           dcpu_we_i;
output  [3:0]                    dcpu_tag_o;
output                          dcpu_err_o;
 
//
// SPR access
//
input                           spr_cs;
input                           spr_write;
input   [aw-1:0]         spr_addr;
input   [31:0]                   spr_dat_i;
output  [31:0]                   spr_dat_o;
 
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
 
//
// DC I/F
//
input                           qmemdmmu_err_i;
input   [3:0]                    qmemdmmu_tag_i;
output  [aw-1:0]         qmemdmmu_adr_o;
output                          qmemdmmu_cycstb_o;
output                          qmemdmmu_ci_o;
 
//
// Internal wires and regs
//
wire                            dtlb_spr_access;
wire    [31:`OR1200_DMMU_PS]    dtlb_ppn;
wire                            dtlb_hit;
wire                            dtlb_uwe;
wire                            dtlb_ure;
wire                            dtlb_swe;
wire                            dtlb_sre;
wire    [31:0]                   dtlb_dat_o;
wire                            dtlb_en;
wire                            dtlb_ci;
wire                            fault;
wire                            miss;
`ifdef OR1200_NO_DMMU
`else
reg                             dtlb_done;
reg     [31:`OR1200_DMMU_PS]    dcpu_vpn_r;
`endif
 
//
// Implemented bits inside match and translate registers
//
// dtlbwYmrX: vpn 31-10  v 0
// dtlbwYtrX: ppn 31-10  swe 9  sre 8  uwe 7  ure 6
//
// dtlb memory width:
// 19 bits for ppn
// 13 bits for vpn
// 1 bit for valid
// 4 bits for protection
// 1 bit for cache inhibit
 
`ifdef OR1200_NO_DMMU
 
//
// Put all outputs in inactive state
//
assign spr_dat_o = 32'h00000000;
assign qmemdmmu_adr_o = dcpu_adr_i;
assign dcpu_tag_o = qmemdmmu_tag_i;
assign qmemdmmu_cycstb_o = dcpu_cycstb_i;
assign dcpu_err_o = qmemdmmu_err_i;
assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
 
`else
 
//
// DTLB SPR access
//
// 0A00 - 0AFF  dtlbmr w0
// 0A00 - 0A3F  dtlbmr w0 [63:0]
//
// 0B00 - 0BFF  dtlbtr w0
// 0B00 - 0B3F  dtlbtr w0 [63:0]
//
assign dtlb_spr_access = spr_cs;
 
//
// Tags:
//
// OR1200_DTAG_TE - TLB miss Exception
// OR1200_DTAG_PE - Page fault Exception
//
assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemdmmu_tag_i;
 
//
// dcpu_err_o
//
assign dcpu_err_o = miss | fault | qmemdmmu_err_i;
 
//
// Assert dtlb_done one clock cycle after new address and dtlb_en must be active
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                dtlb_done <=  1'b0;
        else if (dtlb_en)
                dtlb_done <=  dcpu_cycstb_i;
        else
                dtlb_done <=  1'b0;
 
//
// Cut transfer if something goes wrong with translation. Also delayed signals 
// because of translation delay.
assign qmemdmmu_cycstb_o = (dc_en & dmmu_en) ?
                           !(miss | fault) & dtlb_done & dcpu_cycstb_i :
                           !(miss | fault) & dcpu_cycstb_i;
 
 
//
// Cache Inhibit
//
assign qmemdmmu_ci_o = dmmu_en ? dtlb_ci : `OR1200_DMMU_CI;
 
//
// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is 
// expected to come one clock cycle after offset part.
//
always @(posedge clk or `OR1200_RST_EVENT rst)
        if (rst == `OR1200_RST_VALUE)
                dcpu_vpn_r <=  {32-`OR1200_DMMU_PS{1'b0}};
        else
                dcpu_vpn_r <=  dcpu_adr_i[31:`OR1200_DMMU_PS];
 
//
// Physical address is either translated virtual address or
// simply equal when DMMU is disabled
//
assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} :
                                  dcpu_adr_i;
 
//
// Output to SPRS unit
//
assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;
 
//
// Page fault exception logic
//
assign fault = dtlb_done &
        (  (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled
           || (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled
           || (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled
           || (dcpu_we_i & supv & !dtlb_swe)); // Store in supv mode not enabled
 
//
// TLB Miss exception logic
//
assign miss = dtlb_done & !dtlb_hit;
 
//
// DTLB Enable
//
assign dtlb_en = dmmu_en & dcpu_cycstb_i;
 
//
// Instantiation of DTLB
//
or1200_dmmu_tlb or1200_dmmu_tlb(
        // Rst and clk
        .clk(clk),
        .rst(rst),
 
        // I/F for translation
        .tlb_en(dtlb_en),
        .vaddr(dcpu_adr_i),
        .hit(dtlb_hit),
        .ppn(dtlb_ppn),
        .uwe(dtlb_uwe),
        .ure(dtlb_ure),
        .swe(dtlb_swe),
        .sre(dtlb_sre),
        .ci(dtlb_ci),
 
`ifdef OR1200_BIST
        // RAM BIST
        .mbist_si_i(mbist_si_i),
        .mbist_so_o(mbist_so_o),
        .mbist_ctrl_i(mbist_ctrl_i),
`endif
 
        // SPR access
        .spr_cs(dtlb_spr_access),
        .spr_write(spr_write),
        .spr_addr(spr_addr),
        .spr_dat_i(spr_dat_i),
        .spr_dat_o(dtlb_dat_o)
);
 
`endif
 
endmodule

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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dmmu_top.v] - Blame information for rev 751

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Data MMU top level ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Instantiation of all DMMU blocks. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Log: or1200_dmmu_top.v,v $`
45			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
46			`// Minor update:`
47			`// Bugs fixed.`
48			`//`
49
50			`// synopsys translate_off`
51			`include "timescale.v"
52			`// synopsys translate_on`
53			`include "or1200_defines.v"
54
55			`//`
56			`// Data MMU`
57			`//`
58
59			`module or1200_dmmu_top(`
60			`// Rst and clk`
61			`clk, rst,`
62
63			`// CPU i/f`
64			`dc_en, dmmu_en, supv, dcpu_adr_i, dcpu_cycstb_i, dcpu_we_i,`
65			`dcpu_tag_o, dcpu_err_o,`
66
67			`// SPR access`
68			`spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,`
69
70			`ifdef OR1200_BIST
71			`// RAM BIST`
72			`mbist_si_i, mbist_so_o, mbist_ctrl_i,`
73			`endif
74
75			`// DC i/f`
76			`qmemdmmu_err_i, qmemdmmu_tag_i, qmemdmmu_adr_o, qmemdmmu_cycstb_o, qmemdmmu_ci_o`
77			`);`
78
79			parameter dw = `OR1200_OPERAND_WIDTH;
80			parameter aw = `OR1200_OPERAND_WIDTH;
81
82			`//`
83			`// I/O`
84			`//`
85
86			`//`
87			`// Clock and reset`
88			`//`
89			`input clk;`
90			`input rst;`
91
92			`//`
93			`// CPU I/F`
94			`//`
95			`input dc_en;`
96			`input dmmu_en;`
97			`input supv;`
98			`input [aw-1:0] dcpu_adr_i;`
99			`input dcpu_cycstb_i;`
100			`input dcpu_we_i;`
101			`output [3:0] dcpu_tag_o;`
102			`output dcpu_err_o;`
103
104			`//`
105			`// SPR access`
106			`//`
107			`input spr_cs;`
108			`input spr_write;`
109			`input [aw-1:0] spr_addr;`
110			`input [31:0] spr_dat_i;`
111			`output [31:0] spr_dat_o;`
112
113			`ifdef OR1200_BIST
114			`//`
115			`// RAM BIST`
116			`//`
117			`input mbist_si_i;`
118			input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
119			`output mbist_so_o;`
120			`endif
121
122			`//`
123			`// DC I/F`
124			`//`
125			`input qmemdmmu_err_i;`
126			`input [3:0] qmemdmmu_tag_i;`
127			`output [aw-1:0] qmemdmmu_adr_o;`
128			`output qmemdmmu_cycstb_o;`
129			`output qmemdmmu_ci_o;`
130
131			`//`
132			`// Internal wires and regs`
133			`//`
134			`wire dtlb_spr_access;`
135			wire [31:`OR1200_DMMU_PS] dtlb_ppn;
136			`wire dtlb_hit;`
137			`wire dtlb_uwe;`
138			`wire dtlb_ure;`
139			`wire dtlb_swe;`
140			`wire dtlb_sre;`
141			`wire [31:0] dtlb_dat_o;`
142			`wire dtlb_en;`
143			`wire dtlb_ci;`
144			`wire fault;`
145			`wire miss;`
146			`ifdef OR1200_NO_DMMU
147			`else
148			`reg dtlb_done;`
149			reg [31:`OR1200_DMMU_PS] dcpu_vpn_r;
150			`endif
151
152			`//`
153			`// Implemented bits inside match and translate registers`
154			`//`
155			`// dtlbwYmrX: vpn 31-10 v 0`
156			`// dtlbwYtrX: ppn 31-10 swe 9 sre 8 uwe 7 ure 6`
157			`//`
158			`// dtlb memory width:`
159			`// 19 bits for ppn`
160			`// 13 bits for vpn`
161			`// 1 bit for valid`
162			`// 4 bits for protection`
163			`// 1 bit for cache inhibit`
164
165			`ifdef OR1200_NO_DMMU
166
167			`//`
168			`// Put all outputs in inactive state`
169			`//`
170			`assign spr_dat_o = 32'h00000000;`
171			`assign qmemdmmu_adr_o = dcpu_adr_i;`
172			`assign dcpu_tag_o = qmemdmmu_tag_i;`
173			`assign qmemdmmu_cycstb_o = dcpu_cycstb_i;`
174			`assign dcpu_err_o = qmemdmmu_err_i;`
175			assign qmemdmmu_ci_o = `OR1200_DMMU_CI;
176			`ifdef OR1200_BIST
177			`assign mbist_so_o = mbist_si_i;`
178			`endif
179
180			`else
181
182			`//`
183			`// DTLB SPR access`
184			`//`
185			`// 0A00 - 0AFF dtlbmr w0`
186			`// 0A00 - 0A3F dtlbmr w0 [63:0]`
187			`//`
188			`// 0B00 - 0BFF dtlbtr w0`
189			`// 0B00 - 0B3F dtlbtr w0 [63:0]`
190			`//`
191			`assign dtlb_spr_access = spr_cs;`
192
193			`//`
194			`// Tags:`
195			`//`
196			`// OR1200_DTAG_TE - TLB miss Exception`
197			`// OR1200_DTAG_PE - Page fault Exception`
198			`//`
199			assign dcpu_tag_o = miss ? `OR1200_DTAG_TE : fault ? `OR1200_DTAG_PE : qmemdmmu_tag_i;
200
201			`//`
202			`// dcpu_err_o`
203			`//`
204			`assign dcpu_err_o = miss \| fault \| qmemdmmu_err_i;`
205
206			`//`
207			`// Assert dtlb_done one clock cycle after new address and dtlb_en must be active`
208			`//`
209	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
210			if (rst == `OR1200_RST_VALUE)
211	350	julius	`dtlb_done <= 1'b0;`
212			`else if (dtlb_en)`
213			`dtlb_done <= dcpu_cycstb_i;`
214			`else`
215			`dtlb_done <= 1'b0;`
216
217			`//`
218			`// Cut transfer if something goes wrong with translation. Also delayed signals`
219			`// because of translation delay.`
220			`assign qmemdmmu_cycstb_o = (dc_en & dmmu_en) ?`
221			`!(miss \| fault) & dtlb_done & dcpu_cycstb_i :`
222			`!(miss \| fault) & dcpu_cycstb_i;`
223
224
225			`//`
226			`// Cache Inhibit`
227			`//`
228			assign qmemdmmu_ci_o = dmmu_en ? dtlb_ci : `OR1200_DMMU_CI;
229
230			`//`
231			`// Register dcpu_adr_i's VPN for use when DMMU is not enabled but PPN is`
232			`// expected to come one clock cycle after offset part.`
233			`//`
234	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst)
235			if (rst == `OR1200_RST_VALUE)
236	363	julius	dcpu_vpn_r <= {32-`OR1200_DMMU_PS{1'b0}};
237	350	julius	`else`
238			dcpu_vpn_r <= dcpu_adr_i[31:`OR1200_DMMU_PS];
239
240			`//`
241			`// Physical address is either translated virtual address or`
242			`// simply equal when DMMU is disabled`
243			`//`
244			assign qmemdmmu_adr_o = dmmu_en ? {dtlb_ppn, dcpu_adr_i[`OR1200_DMMU_PS-1:0]} :
245			`dcpu_adr_i;`
246
247			`//`
248			`// Output to SPRS unit`
249			`//`
250			`assign spr_dat_o = dtlb_spr_access ? dtlb_dat_o : 32'h00000000;`
251
252			`//`
253			`// Page fault exception logic`
254			`//`
255			`assign fault = dtlb_done &`
256			`( (!dcpu_we_i & !supv & !dtlb_ure) // Load in user mode not enabled`
257			`\|\| (!dcpu_we_i & supv & !dtlb_sre) // Load in supv mode not enabled`
258			`\|\| (dcpu_we_i & !supv & !dtlb_uwe) // Store in user mode not enabled`
259			`\|\| (dcpu_we_i & supv & !dtlb_swe)); // Store in supv mode not enabled`
260
261			`//`
262			`// TLB Miss exception logic`
263			`//`
264			`assign miss = dtlb_done & !dtlb_hit;`
265
266			`//`
267			`// DTLB Enable`
268			`//`
269			`assign dtlb_en = dmmu_en & dcpu_cycstb_i;`
270
271			`//`
272			`// Instantiation of DTLB`
273			`//`
274			`or1200_dmmu_tlb or1200_dmmu_tlb(`
275			`// Rst and clk`
276			`.clk(clk),`
277			`.rst(rst),`
278
279			`// I/F for translation`
280			`.tlb_en(dtlb_en),`
281			`.vaddr(dcpu_adr_i),`
282			`.hit(dtlb_hit),`
283			`.ppn(dtlb_ppn),`
284			`.uwe(dtlb_uwe),`
285			`.ure(dtlb_ure),`
286			`.swe(dtlb_swe),`
287			`.sre(dtlb_sre),`
288			`.ci(dtlb_ci),`
289
290			`ifdef OR1200_BIST
291			`// RAM BIST`
292			`.mbist_si_i(mbist_si_i),`
293			`.mbist_so_o(mbist_so_o),`
294			`.mbist_ctrl_i(mbist_ctrl_i),`
295			`endif
296
297			`// SPR access`
298			`.spr_cs(dtlb_spr_access),`
299			`.spr_write(spr_write),`
300			`.spr_addr(spr_addr),`
301			`.spr_dat_i(spr_dat_i),`
302			`.spr_dat_o(dtlb_dat_o)`
303			`);`
304
305			`endif
306
307			`endmodule`