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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_dpram.v] - Blame information for rev 788

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1 350 julius
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Generic Double-Port Synchronous RAM                         ////
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////                                                              ////
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////  This file is part of memory library available from          ////
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////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////
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////                                                              ////
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////  Description                                                 ////
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////  This block is a wrapper with common double-port             ////
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////  synchronous memory interface for different                  ////
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////  types of ASIC and FPGA RAMs. Beside universal memory        ////
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////  interface it also provides behavioral model of generic      ////
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////  double-port synchronous RAM.                                ////
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////  It should be used in all OPENCORES designs that want to be  ////
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////  portable accross different target technologies and          ////
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////  independent of target memory.                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_dpram_32x32.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// New 
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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module or1200_dpram
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  (
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   // Generic synchronous double-port RAM interface
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   clk_a, ce_a, addr_a, do_a,
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   clk_b, ce_b, we_b, addr_b, di_b
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   );
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   //
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   // Default address and data buses width
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   //
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   parameter aw = 5;
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   parameter dw = 32;
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   //
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   // Generic synchronous double-port RAM interface
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   //
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   input                        clk_a;  // Clock
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   input                        ce_a;   // Chip enable input
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   input [aw-1:0]                addr_a; // address bus inputs
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   output [dw-1:0]               do_a;   // output data bus
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   input                        clk_b;  // Clock
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   input                        ce_b;   // Chip enable input
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   input                        we_b;   // Write enable input
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   input [aw-1:0]                addr_b; // address bus inputs
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   input [dw-1:0]                di_b;   // input data bus
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   //
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   // Internal wires and registers
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   //
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   //
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   // Generic double-port synchronous RAM model
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   //
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   //
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   // Generic RAM's registers and wires
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   //
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   reg [dw-1:0]          mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;    // RAM content
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   reg [aw-1:0]          addr_a_reg;             // RAM address registered
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   // Function to access GPRs (for use by Verilator). No need to hide this one
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   // from the simulator, since it has an input (as required by IEEE 1364-2001).
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   function [31:0] get_gpr;
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      // verilator public
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      input [aw-1:0]             gpr_no;
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      get_gpr = mem[gpr_no];
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   endfunction // get_gpr
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   function [31:0] set_gpr;
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      // verilator public
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      input [aw-1:0]             gpr_no;
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      input [dw-1:0]             value;
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      begin
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         mem[gpr_no] = value;
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         set_gpr = 0;
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      end
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   endfunction // get_gpr
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   //
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   // Data output drivers
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   //
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   //assign do_a = (oe_a) ? mem[addr_a_reg] : {dw{1'b0}};
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   assign do_a = mem[addr_a_reg];
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   //
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   // RAM read
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   //
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   always @(posedge clk_a)
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     if (ce_a)
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       addr_a_reg <=  addr_a;
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   //
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   // RAM write
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   //
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   always @(posedge clk_b)
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     if (ce_b & we_b)
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       mem[addr_b] <=  di_b;
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endmodule // or1200_dpram

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