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//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Generic Double-Port Synchronous RAM                         ////

////                                                              ////

////  This file is part of memory library available from          ////

////  http://www.opencores.org/cvsweb.shtml/generic_memories/     ////

////                                                              ////

////  Description                                                 ////

////  This block is a wrapper with common double-port             ////

////  synchronous memory interface for different                  ////

////  types of ASIC and FPGA RAMs. Beside universal memory        ////

////  interface it also provides behavioral model of generic      ////

////  double-port synchronous RAM.                                ////

////  It should be used in all OPENCORES designs that want to be  ////

////  portable accross different target technologies and          ////

////  independent of target memory.                               ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

//

// CVS Revision History

//

// $Log: or1200_dpram_32x32.v,v $

// Revision 2.0  2010/06/30 11:00:00  ORSoC

// New 

//

// synopsys translate_off

`include "timescale.v"

// synopsys translate_on

`include "or1200_defines.v"

module or1200_dpram

  (

   // Generic synchronous double-port RAM interface

   clk_a, ce_a, addr_a, do_a,

   clk_b, ce_b, we_b, addr_b, di_b

`ifdef OR1200_RAM_PARITY

   , p_err

`endif

   );

   //

   // Default address and data buses width

   //

   parameter aw = 5;

   parameter dw = 32;

   //

   // Generic synchronous double-port RAM interface

   //

   input                        clk_a;  // Clock

   input                        ce_a;   // Chip enable input

   input [aw-1:0]                addr_a; // address bus inputs

   output [dw-1:0]               do_a;   // output data bus

   input                        clk_b;  // Clock

   input                        ce_b;   // Chip enable input

   input                        we_b;   // Write enable input

   input [aw-1:0]                addr_b; // address bus inputs

   input [dw-1:0]                di_b;   // input data bus

`ifdef OR1200_RAM_PARITY

   output                       p_err; // parity error indicator

`endif

   //

   // Internal wires and registers

   //

   //

   // Generic double-port synchronous RAM model

   //

   //

   // Generic RAM's registers and wires

   //

`ifdef OR1200_RAM_PARITY

   reg [(dw+(dw/8))-1:0]                 mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;    // RAM content

`else

   reg [dw-1:0]          mem [(1<<aw)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;    // RAM content

`endif

   reg [aw-1:0]          addr_a_reg;             // RAM address registered

`ifdef OR1200_RAM_PARITY

   wire [(dw+(dw/8))-1:0]        do_a_wire;

   wire [(dw/8)-1:0]             di_p;

   wire [(dw/8)-1:0]             do_p;

   wire [(dw/8)-1:0]             parity_err;

`else

   wire [dw-1:0]         do_a_wire;

`endif

   // Function to access GPRs (for use by Verilator). No need to hide this one

   // from the simulator, since it has an input (as required by IEEE 1364-2001).

   function [31:0] get_gpr;

      // verilator public

      input [aw-1:0]             gpr_no;

      reg [(dw+(dw/8))-1:0]              gpr_temp;

      begin

`ifdef OR1200_RAM_PARITY

         gpr_temp = mem[gpr_no];

         get_gpr = gpr_temp[31:0];

`else

         get_gpr = mem[gpr_no];

`endif

      end

   endfunction // get_gpr

   task set_gpr;

      // verilator public

      input [aw-1:0]             gpr_no;

      input [dw-1:0]             value;

      mem[gpr_no] =

`ifdef OR1200_RAM_PARITY

        {(^value[(8*3)+7:(8*3)]),(^value[(8*2)+7:(8*2)]),

         (^value[(8*1)+7:(8*1)]),(^value[(8*0)+7:(8*0)]),

         value}

`else

                    value

`endif

                      ;

   endtask // get_gpr

`ifdef OR1200_RAM_PARITY

   genvar                       i;

   generate

      for (i=0;i<(dw/8);i=i+1) begin: paritygen

         or1200_parity_gen pgen(.d_i(di_b[(i*8)+7:(i*8)]), .p_o(di_p[i]));

         or1200_parity_chk pchk(.d_i(do_a_wire[(i*8)+7:(i*8)]),

                                .p_i(do_p[i]), .err_o(parity_err[i]));

      end

   endgenerate

   // Extract parity bits of data out

   assign do_p = do_a_wire[(dw+(dw/8))-1:dw];

   // Indicate error

   assign p_err = (|parity_err);

   // Inject a parity error. Can specify GPR number to affect,

   // and which parity or data bit to switch.

   task gen_parity_err;

      input [aw-1:0]             gpr_no;

      input [31:0]               parity_bit_no;

      input [31:0]               data_bit_no;

      reg [(dw+(dw/8))-1:0]      do_temp;

      begin

         do_temp = mem[gpr_no];

         // Switch parity bit

         if (parity_bit_no > 0)

           do_temp[dw+(parity_bit_no-1)] = ~do_temp[dw+(parity_bit_no-1)];

         // Switch data bit

         if (data_bit_no > 0 && data_bit_no <= dw)

           do_temp[data_bit_no-1] = ~do_temp[data_bit_no-1];

         // Write word back

         mem[gpr_no] = do_temp;

      end

   endtask // gen_parity_err

`endif

   //

   // Data output drivers

   //

   assign do_a_wire = mem[addr_a_reg];

   assign do_a = do_a_wire[dw-1:0];

   //

   // RAM read

   //

   always @(posedge clk_a)

     if (ce_a)

       addr_a_reg <=  addr_a;

   //

   // RAM write

   //

   always @(posedge clk_b)

     if (ce_b & we_b)

`ifdef OR1200_RAM_PARITY

       mem[addr_b] <=  {di_p,di_b};

`else

       mem[addr_b] <=  di_b;

`endif

endmodule // or1200_dpram