URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_except.v] - Blame information for rev 833

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  OR1200's Exception logic                                    ////
////                                                              ////
////  This file is part of the OpenRISC 1200 project              ////
////  http://www.opencores.org/project,or1k                       ////
////                                                              ////
////  Description                                                 ////
////  Handles all OR1K exceptions inside CPU block.               ////
////                                                              ////
////  To Do:                                                      ////
////   - make it smaller and faster                               ////
////                                                              ////
////  Author(s):                                                  ////
////      - Damjan Lampret, lampret@opencores.org                 ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_except.v,v $
//
// Revision 2.0  2010/06/30 11:00:00  ORSoC
// Major update: 
// Structure reordered and bugs fixed. 
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
 
`define OR1200_EXCEPTFSM_WIDTH 3
`define OR1200_EXCEPTFSM_IDLE   `OR1200_EXCEPTFSM_WIDTH'd0
`define OR1200_EXCEPTFSM_FLU1   `OR1200_EXCEPTFSM_WIDTH'd1
`define OR1200_EXCEPTFSM_FLU2   `OR1200_EXCEPTFSM_WIDTH'd2
`define OR1200_EXCEPTFSM_FLU3   `OR1200_EXCEPTFSM_WIDTH'd3
`define OR1200_EXCEPTFSM_FLU4   `OR1200_EXCEPTFSM_WIDTH'd4
`define OR1200_EXCEPTFSM_FLU5   `OR1200_EXCEPTFSM_WIDTH'd5
 
//
// Exception recognition and sequencing
//
 
module or1200_except
  (
   // Clock and reset
   clk, rst,
 
   // Internal i/f
   sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss,
   sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault,
   sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze,
   if_stall,  if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,
   extend_flush, except_flushpipe, except_type, except_start, except_started,
   except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,
   spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,
   du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,
   abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee,
   dsx
 
);
 
//
// I/O
//
input                           clk;
input                           rst;
input                           sig_ibuserr;
input                           sig_dbuserr;
input                           sig_illegal;
input                           sig_align;
input                           sig_range;
input                           sig_dtlbmiss;
input                           sig_dmmufault;
input                           sig_int;
input                           sig_syscall;
input                           sig_trap;
input                           sig_itlbmiss;
input                           sig_immufault;
input                           sig_tick;
input                           sig_fp;
input                           fpcsr_fpee;
input                           ex_branch_taken;
input                           genpc_freeze;
input                           id_freeze;
input                           ex_freeze;
input                           wb_freeze;
input                           if_stall;
input   [31:0]           if_pc;
output  [31:0]           id_pc;
output  [31:0]      ex_pc;
output  [31:0]      wb_pc;
input   [31:0]           datain;
input   [`OR1200_DU_DSR_WIDTH-1:0]     du_dsr;
input   [24:0]                       du_dmr1;
input                   du_hwbkpt;
input                   du_hwbkpt_ls_r;
input                           epcr_we;
input                           eear_we;
input                           esr_we;
input                           pc_we;
output  [31:0]                   epcr;
output  [31:0]                   eear;
output  [`OR1200_SR_WIDTH-1:0]   esr;
input   [`OR1200_SR_WIDTH-1:0]   to_sr;
input                           sr_we;
input   [`OR1200_SR_WIDTH-1:0]   sr;
input   [31:0]                   lsu_addr;
input                   id_flushpipe;
input                   ex_flushpipe;
output                          except_flushpipe;
output                          extend_flush;
output  [`OR1200_EXCEPT_WIDTH-1:0]       except_type;
output                          except_start;
output                          except_started;
output  [13:0]           except_stop;
output  [13:0]           except_trig;
input                           ex_void;
input   [`OR1200_BRANCHOP_WIDTH-1:0]    branch_op;
output  [31:0]                   spr_dat_ppc;
output  [31:0]                   spr_dat_npc;
output                          abort_ex;
output              abort_mvspr;
input                           icpu_ack_i;
input                           icpu_err_i;
input                           dcpu_ack_i;
input                           dcpu_err_i;
output                          dsx;
 
//
// Internal regs and wires
//
reg     [`OR1200_EXCEPT_WIDTH-1:0]       except_type /* verilator public */;
reg     [31:0]                   id_pc /* verilator public */;
reg                 id_pc_val;
reg     [31:0]                   ex_pc /* verilator public */;
reg                 ex_pc_val;
reg     [31:0]                   wb_pc /* verilator public */;
reg [31:0]          dl_pc;
reg     [31:0]                   epcr;
reg     [31:0]                   eear;
reg     [`OR1200_SR_WIDTH-1:0]           esr;
reg     [2:0]                    id_exceptflags;
reg     [2:0]                    ex_exceptflags;
reg     [`OR1200_EXCEPTFSM_WIDTH-1:0]    state;
reg                             extend_flush;
reg                             extend_flush_last;
reg                             ex_dslot /* verilator public */;
reg                             delayed1_ex_dslot;
reg                             delayed2_ex_dslot;
wire                            except_started;
wire                            except_flushpipe /* verilator public */;
reg     [2:0]                    delayed_iee;
reg     [2:0]                    delayed_tee;
wire                            int_pending;
wire                            tick_pending;
wire                            fp_pending;
wire                            range_pending;
reg                             dsx;
 
reg trace_trap      ;
reg ex_freeze_prev;
reg sr_ted_prev;
reg dsr_te_prev;
reg dmr1_st_prev    ;
reg dmr1_bt_prev    ;
wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
 
//
// Simple combinatorial logic
//
assign except_started = extend_flush & except_start;
 
assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
 
assign int_pending = sig_int & (sr[`OR1200_SR_IEE] |
                                (sr_we & to_sr[`OR1200_SR_IEE]))
                    & id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken
                     & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
 
assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] |
                                  (sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val
                      & delayed_tee[2] & ~ex_freeze & ~ex_branch_taken
                      & ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
 
assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken
                    & ~ex_dslot;
 
`ifdef OR1200_IMPL_OVE
assign range_pending =  sig_range & sr[`OR1200_SR_OVE] & ~ex_freeze &
                       ~ex_branch_taken & ~ex_dslot;
`else
assign range_pending = 0;
`endif
 
// Abort write into RF by load & other instructions   
assign abort_ex = sig_dbuserr | sig_dmmufault | sig_dtlbmiss | sig_align |
                  sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
                                 & !sr_ted & !dsr_te);
 
// abort spr read/writes   
assign abort_mvspr  = sig_illegal | ((du_hwbkpt | trace_trap) & ex_pc_val
                                     & !sr_ted & !dsr_te) ;
assign spr_dat_ppc = wb_pc;
 
assign spr_dat_npc = ex_void ? id_pc : ex_pc;
 
//
// Order defines exception detection priority
//
assign except_trig = {
                      ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
                      ex_exceptflags[0]  & ~du_dsr[`OR1200_DU_DSR_IPFE],
                      ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                      sig_illegal       & ~du_dsr[`OR1200_DU_DSR_IIE],
                      sig_align         & ~du_dsr[`OR1200_DU_DSR_AE],
                      sig_dtlbmiss      & ~du_dsr[`OR1200_DU_DSR_DME],
                      sig_trap          & ~du_dsr[`OR1200_DU_DSR_TE],
                      sig_syscall       & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
                      sig_dmmufault     & ~du_dsr[`OR1200_DU_DSR_DPFE],
                      sig_dbuserr       & ~du_dsr[`OR1200_DU_DSR_BUSEE],
                      range_pending     & ~du_dsr[`OR1200_DU_DSR_RE],
                      fp_pending        & ~du_dsr[`OR1200_DU_DSR_FPE],
                      int_pending       & ~du_dsr[`OR1200_DU_DSR_IE],
                      tick_pending      & ~du_dsr[`OR1200_DU_DSR_TTE]
                      };
 
wire    trace_cond  = !ex_freeze && !ex_void && (1'b0
`ifdef OR1200_DU_DMR1_ST
    ||  dmr1_st
`endif
`ifdef OR1200_DU_DMR1_BT
    ||  ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
`endif
    );
 
assign except_stop = {
                        tick_pending            & du_dsr[`OR1200_DU_DSR_TTE],
                        int_pending             & du_dsr[`OR1200_DU_DSR_IE],
                        ex_exceptflags[1]       & du_dsr[`OR1200_DU_DSR_IME],
                        ex_exceptflags[0]        & du_dsr[`OR1200_DU_DSR_IPFE],
                        ex_exceptflags[2]       & du_dsr[`OR1200_DU_DSR_BUSEE],
                        sig_illegal             & du_dsr[`OR1200_DU_DSR_IIE],
                        sig_align               & du_dsr[`OR1200_DU_DSR_AE],
                        sig_dtlbmiss            & du_dsr[`OR1200_DU_DSR_DME],
                        sig_dmmufault           & du_dsr[`OR1200_DU_DSR_DPFE],
                        sig_dbuserr             & du_dsr[`OR1200_DU_DSR_BUSEE],
                        range_pending           & du_dsr[`OR1200_DU_DSR_RE],
                        sig_trap                & du_dsr[`OR1200_DU_DSR_TE],
                        fp_pending              & du_dsr[`OR1200_DU_DSR_FPE],
                        sig_syscall             & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
                };
 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                trace_trap  <=  1'b0 ;
        end
        else if (!(trace_trap && !ex_pc_val)) begin
                trace_trap  <=  trace_cond & !dsr_te & !sr_ted ;
        end
end
 
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
        ex_freeze_prev  <=  1'b0 ;
        sr_ted_prev     <=  1'b0 ;
        dsr_te_prev     <=  1'b0 ;
        dmr1_st_prev    <=  1'b0 ;
        dmr1_bt_prev    <=  1'b0 ;
    end
    else begin
        ex_freeze_prev  <=  ex_freeze ;
        if (!ex_freeze_prev || ex_void) begin
            sr_ted_prev     <=  sr     [`OR1200_SR_TED    ] ;
            dsr_te_prev     <=  du_dsr [`OR1200_DU_DSR_TE ] ;
            dmr1_st_prev    <=  du_dmr1[`OR1200_DU_DMR1_ST] ;
            dmr1_bt_prev    <=  du_dmr1[`OR1200_DU_DMR1_BT] ;
        end
    end
end
 
`ifdef verilator
   // Function to access wb_pc (for Verilator). Have to hide this from
   // simulator, since functions with no inputs are not allowed in IEEE
   // 1364-2001.
   function [31:0] get_wb_pc;
      // verilator public
      get_wb_pc = wb_pc;
   endfunction // get_wb_pc
 
   // Function to access id_pc (for Verilator). Have to hide this from
   // simulator, since functions with no inputs are not allowed in IEEE
   // 1364-2001.
   function [31:0] get_id_pc;
      // verilator public
      get_id_pc = id_pc;
   endfunction // get_id_pc
 
   // Function to access ex_pc (for Verilator). Have to hide this from
   // simulator, since functions with no inputs are not allowed in IEEE
   // 1364-2001.
   function [31:0] get_ex_pc;
      // verilator public
      get_ex_pc = ex_pc;
   endfunction // get_ex_pc
   // Function to access except_type[3:0] (for Verilator). Have to hide this from
   // simulator, since functions with no inputs are not allowed in IEEE
   // 1364-2001.
   function [3:0] get_except_type;
      // verilator public
      get_except_type = except_type;
   endfunction // get_except_type
 
`endif
 
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                id_pc <=  32'd0;
        id_pc_val <=  1'b0 ;
                id_exceptflags <=  3'b000;
        end
        else if (id_flushpipe) begin
        id_pc_val <=  1'b0 ;
                id_exceptflags <=  3'b000;
        end
        else if (!id_freeze) begin
                id_pc <=  if_pc;
        id_pc_val <=  1'b1 ;
                id_exceptflags <=  { sig_ibuserr, sig_itlbmiss, sig_immufault };
        end
end
 
//
// delayed_iee
//
// SR[IEE] should not enable interrupts right away
// when it is restored with l.rfe. Instead delayed_iee
// together with SR[IEE] enables interrupts once
// pipeline is again ready.
//
always @(`OR1200_RST_EVENT rst or posedge clk)
        if (rst == `OR1200_RST_VALUE)
                delayed_iee <=  3'b000;
        else if (!sr[`OR1200_SR_IEE])
                delayed_iee <=  3'b000;
        else
                delayed_iee <=  {delayed_iee[1:0], 1'b1};
 
//
// delayed_tee
//
// SR[TEE] should not enable tick exceptions right away
// when it is restored with l.rfe. Instead delayed_tee
// together with SR[TEE] enables tick exceptions once
// pipeline is again ready.
//
always @(`OR1200_RST_EVENT rst or posedge clk)
        if (rst == `OR1200_RST_VALUE)
                delayed_tee <=  3'b000;
        else if (!sr[`OR1200_SR_TEE])
                delayed_tee <=  3'b000;
        else
                delayed_tee <=  {delayed_tee[1:0], 1'b1};
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                ex_dslot <=  1'b0;
                ex_pc <=  32'd0;
                ex_pc_val <=  1'b0 ;
                ex_exceptflags <=  3'b000;
                delayed1_ex_dslot <=  1'b0;
                delayed2_ex_dslot <=  1'b0;
        end
        else if (ex_flushpipe) begin
                ex_dslot <=  1'b0;
                ex_pc_val <=  1'b0 ;
                ex_exceptflags <=  3'b000;
                delayed1_ex_dslot <=  1'b0;
                delayed2_ex_dslot <=  1'b0;
        end
        else if (!ex_freeze & id_freeze) begin
                ex_dslot <=  1'b0;
                ex_pc <=  id_pc;
                ex_pc_val <=  id_pc_val ;
                ex_exceptflags <=  3'b000;
                delayed1_ex_dslot <=  ex_dslot;
                delayed2_ex_dslot <=  delayed1_ex_dslot;
        end
        else if (!ex_freeze) begin
                ex_dslot <=  ex_branch_taken;
                ex_pc <=  id_pc;
                ex_pc_val <=  id_pc_val ;
                ex_exceptflags <=  id_exceptflags;
                delayed1_ex_dslot <=  ex_dslot;
                delayed2_ex_dslot <=  delayed1_ex_dslot;
        end
end
 
//
// PC and Exception flags pipelines
//
always @(posedge clk or `OR1200_RST_EVENT rst) begin
        if (rst == `OR1200_RST_VALUE) begin
                wb_pc <=  32'd0;
        dl_pc <=  32'd0;
        end
        else if (!wb_freeze) begin
                wb_pc <=  ex_pc;
        dl_pc <=  wb_pc;
        end
end
 
//
// We have started execution of exception handler:
//  1. Asserted for 3 clock cycles
//  2. Don't execute any instruction that is still in pipeline and is not part of exception handler
//
assign except_flushpipe = |except_trig & ~|state;
 
//
// Exception FSM that sequences execution of exception handler
//
// except_type signals which exception handler we start fetching in:
//  1. Asserted in next clock cycle after exception is recognized
//
   always @(posedge clk or `OR1200_RST_EVENT rst) begin
      if (rst == `OR1200_RST_VALUE) begin
         state <=  `OR1200_EXCEPTFSM_IDLE;
         except_type <=  `OR1200_EXCEPT_NONE;
         extend_flush <=  1'b0;
         epcr <=  32'b0;
         eear <=  32'b0;
         esr <=  {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
         extend_flush_last <=  1'b0;
         dsx <= 1'b0;
      end
      else begin
`ifdef OR1200_CASE_DEFAULT
         case (state)   // synopsys parallel_case
`else
           case (state) // synopsys full_case parallel_case
`endif
             `OR1200_EXCEPTFSM_IDLE:
               if (except_flushpipe) begin
                  state <=  `OR1200_EXCEPTFSM_FLU1;
                  extend_flush <=  1'b1;
                  esr <=  sr_we ? to_sr : sr;
                  casez (except_trig)
`ifdef OR1200_EXCEPT_ITLBMISS
                    14'b1?_????_????_????: begin
                       except_type <=  `OR1200_EXCEPT_ITLBMISS;
                       eear <=  ex_dslot ?
                               ex_pc : ex_pc;
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_IPF
                    14'b01_????_????_????: begin
                       except_type <=  `OR1200_EXCEPT_IPF;
                       eear <=  ex_dslot ?
                               ex_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_BUSERR
                    14'b00_1???_????_????: begin        // Insn. Bus Error
                       except_type <=  `OR1200_EXCEPT_BUSERR;
                       eear <=  ex_dslot ?
                               wb_pc : ex_pc;
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_ILLEGAL
                    14'b00_01??_????_????: begin
                       except_type <=  `OR1200_EXCEPT_ILLEGAL;
                       eear <=  ex_pc;
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_ALIGN
                    14'b00_001?_????_????: begin
                       except_type <=  `OR1200_EXCEPT_ALIGN;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                               wb_pc : ex_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_DTLBMISS
                    14'b00_0001_????_????: begin
                       except_type <=  `OR1200_EXCEPT_DTLBMISS;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : ex_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_TRAP
                    14'b00_0000_1???_????: begin
                       except_type <=  `OR1200_EXCEPT_TRAP;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : ex_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_SYSCALL
                    14'b00_0000_01??_????: begin
                       except_type <=  `OR1200_EXCEPT_SYSCALL;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               id_pc : delayed2_ex_dslot ?
                               id_pc : id_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_DPF
                    14'b00_0000_001?_????: begin
                       except_type <=  `OR1200_EXCEPT_DPF;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : ex_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_BUSERR
                    14'b00_0000_0001_????: begin        // Data Bus Error
                       except_type <=  `OR1200_EXCEPT_BUSERR;
                       eear <=  lsu_addr;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : ex_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_RANGE
                    14'b00_0000_0000_1???: begin
                       except_type <=  `OR1200_EXCEPT_RANGE;
                       epcr <=  ex_dslot ?
                               wb_pc : delayed1_ex_dslot ?
                               dl_pc : delayed2_ex_dslot ?
                               id_pc : ex_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_FLOAT
                    14'b00_0000_0000_01??: begin
                       except_type <=  `OR1200_EXCEPT_FLOAT;
                       epcr <=  id_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_INT
                    14'b00_0000_0000_001?: begin
                       except_type <=  `OR1200_EXCEPT_INT;
                       epcr <=  id_pc;
                       dsx <= ex_dslot;
                    end
`endif
`ifdef OR1200_EXCEPT_TICK
                    14'b00_0000_0000_0001: begin
                       except_type <=  `OR1200_EXCEPT_TICK;
                       epcr <=  id_pc;
                       dsx <= ex_dslot;
                    end
`endif
                    default:
                      except_type <=  `OR1200_EXCEPT_NONE;
                  endcase
               end
               else if (pc_we) begin
                  state <=  `OR1200_EXCEPTFSM_FLU1;
                  extend_flush <=  1'b1;
               end
               else begin
                  if (epcr_we)
                    epcr <=  datain;
                  if (eear_we)
                    eear <=  datain;
                  if (esr_we)
                    esr <=  {datain[`OR1200_SR_WIDTH-1], 1'b1, datain[`OR1200_SR_WIDTH-3:0]};
               end
             `OR1200_EXCEPTFSM_FLU1:
               if (icpu_ack_i | icpu_err_i | genpc_freeze)
                 state <=  `OR1200_EXCEPTFSM_FLU2;
             `OR1200_EXCEPTFSM_FLU2:
`ifdef OR1200_EXCEPT_TRAP
               if (except_type == `OR1200_EXCEPT_TRAP) begin
                  state <=  `OR1200_EXCEPTFSM_IDLE;
                  extend_flush <=  1'b0;
                  extend_flush_last <=  1'b0;
                  except_type <=  `OR1200_EXCEPT_NONE;
               end
               else
`endif
                 state <=  `OR1200_EXCEPTFSM_FLU3;
             `OR1200_EXCEPTFSM_FLU3:
               begin
                  state <=  `OR1200_EXCEPTFSM_FLU4;
               end
             `OR1200_EXCEPTFSM_FLU4: begin
                state <=  `OR1200_EXCEPTFSM_FLU5;
                extend_flush <=  1'b0;
                extend_flush_last <=  1'b0; // damjan
             end
`ifdef OR1200_CASE_DEFAULT
             default: begin
`else
                `OR1200_EXCEPTFSM_FLU5: begin
`endif
                   if (!if_stall && !id_freeze) begin
                      state <=  `OR1200_EXCEPTFSM_IDLE;
                      except_type <=  `OR1200_EXCEPT_NONE;
                      extend_flush_last <=  1'b0;
                   end
                end
           endcase
         end
   end
 
endmodule

Line No.	Rev	Author	Line
1	350	julius	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// OR1200's Exception logic ////`
4			`//// ////`
5			`//// This file is part of the OpenRISC 1200 project ////`
6			`//// http://www.opencores.org/project,or1k ////`
7			`//// ////`
8			`//// Description ////`
9			`//// Handles all OR1K exceptions inside CPU block. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// - make it smaller and faster ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Damjan Lampret, lampret@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// $Log: or1200_except.v,v $`
45			`//`
46			`// Revision 2.0 2010/06/30 11:00:00 ORSoC`
47			`// Major update:`
48			`// Structure reordered and bugs fixed.`
49
50			`// synopsys translate_off`
51			`include "timescale.v"
52			`// synopsys translate_on`
53			`include "or1200_defines.v"
54
55			`define OR1200_EXCEPTFSM_WIDTH 3
56			`define OR1200_EXCEPTFSM_IDLE `OR1200_EXCEPTFSM_WIDTH'd0
57			`define OR1200_EXCEPTFSM_FLU1 `OR1200_EXCEPTFSM_WIDTH'd1
58			`define OR1200_EXCEPTFSM_FLU2 `OR1200_EXCEPTFSM_WIDTH'd2
59			`define OR1200_EXCEPTFSM_FLU3 `OR1200_EXCEPTFSM_WIDTH'd3
60			`define OR1200_EXCEPTFSM_FLU4 `OR1200_EXCEPTFSM_WIDTH'd4
61			`define OR1200_EXCEPTFSM_FLU5 `OR1200_EXCEPTFSM_WIDTH'd5
62
63			`//`
64			`// Exception recognition and sequencing`
65			`//`
66
67			`module or1200_except`
68			`(`
69			`// Clock and reset`
70			`clk, rst,`
71
72			`// Internal i/f`
73			`sig_ibuserr, sig_dbuserr, sig_illegal, sig_align, sig_range, sig_dtlbmiss,`
74			`sig_dmmufault, sig_int, sig_syscall, sig_trap, sig_itlbmiss, sig_immufault,`
75			`sig_tick, ex_branch_taken, genpc_freeze, id_freeze, ex_freeze, wb_freeze,`
76			`if_stall, if_pc, id_pc, ex_pc, wb_pc, id_flushpipe, ex_flushpipe,`
77			`extend_flush, except_flushpipe, except_type, except_start, except_started,`
78			`except_stop, except_trig, ex_void, abort_mvspr, branch_op, spr_dat_ppc,`
79			`spr_dat_npc, datain, du_dsr, epcr_we, eear_we, esr_we, pc_we, epcr, eear,`
80			`du_dmr1, du_hwbkpt, du_hwbkpt_ls_r, esr, sr_we, to_sr, sr, lsu_addr,`
81	807	julius	`abort_ex, icpu_ack_i, icpu_err_i, dcpu_ack_i, dcpu_err_i, sig_fp, fpcsr_fpee,`
82			`dsx`
83	350	julius
84			`);`
85
86			`//`
87			`// I/O`
88			`//`
89			`input clk;`
90			`input rst;`
91			`input sig_ibuserr;`
92			`input sig_dbuserr;`
93			`input sig_illegal;`
94			`input sig_align;`
95			`input sig_range;`
96			`input sig_dtlbmiss;`
97			`input sig_dmmufault;`
98			`input sig_int;`
99			`input sig_syscall;`
100			`input sig_trap;`
101			`input sig_itlbmiss;`
102			`input sig_immufault;`
103			`input sig_tick;`
104			`input sig_fp;`
105			`input fpcsr_fpee;`
106			`input ex_branch_taken;`
107			`input genpc_freeze;`
108			`input id_freeze;`
109			`input ex_freeze;`
110			`input wb_freeze;`
111			`input if_stall;`
112			`input [31:0] if_pc;`
113			`output [31:0] id_pc;`
114			`output [31:0] ex_pc;`
115			`output [31:0] wb_pc;`
116			`input [31:0] datain;`
117			input [`OR1200_DU_DSR_WIDTH-1:0] du_dsr;
118			`input [24:0] du_dmr1;`
119			`input du_hwbkpt;`
120			`input du_hwbkpt_ls_r;`
121			`input epcr_we;`
122			`input eear_we;`
123			`input esr_we;`
124			`input pc_we;`
125			`output [31:0] epcr;`
126			`output [31:0] eear;`
127			output [`OR1200_SR_WIDTH-1:0] esr;
128			input [`OR1200_SR_WIDTH-1:0] to_sr;
129			`input sr_we;`
130			input [`OR1200_SR_WIDTH-1:0] sr;
131			`input [31:0] lsu_addr;`
132			`input id_flushpipe;`
133			`input ex_flushpipe;`
134			`output except_flushpipe;`
135			`output extend_flush;`
136			output [`OR1200_EXCEPT_WIDTH-1:0] except_type;
137			`output except_start;`
138			`output except_started;`
139			`output [13:0] except_stop;`
140			`output [13:0] except_trig;`
141			`input ex_void;`
142			input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op;
143			`output [31:0] spr_dat_ppc;`
144			`output [31:0] spr_dat_npc;`
145			`output abort_ex;`
146			`output abort_mvspr;`
147			`input icpu_ack_i;`
148			`input icpu_err_i;`
149			`input dcpu_ack_i;`
150			`input dcpu_err_i;`
151	807	julius	`output dsx;`
152
153	350	julius	`//`
154			`// Internal regs and wires`
155			`//`
156	353	julius	reg [`OR1200_EXCEPT_WIDTH-1:0] except_type /* verilator public */;
157			`reg [31:0] id_pc /* verilator public */;`
158	350	julius	`reg id_pc_val;`
159	353	julius	`reg [31:0] ex_pc /* verilator public */;`
160	350	julius	`reg ex_pc_val;`
161	353	julius	`reg [31:0] wb_pc /* verilator public */;`
162	350	julius	`reg [31:0] dl_pc;`
163			`reg [31:0] epcr;`
164			`reg [31:0] eear;`
165			reg [`OR1200_SR_WIDTH-1:0] esr;
166			`reg [2:0] id_exceptflags;`
167			`reg [2:0] ex_exceptflags;`
168			reg [`OR1200_EXCEPTFSM_WIDTH-1:0] state;
169			`reg extend_flush;`
170			`reg extend_flush_last;`
171	353	julius	`reg ex_dslot /* verilator public */;`
172	350	julius	`reg delayed1_ex_dslot;`
173			`reg delayed2_ex_dslot;`
174			`wire except_started;`
175	353	julius	`wire except_flushpipe /* verilator public */;`
176	350	julius	`reg [2:0] delayed_iee;`
177			`reg [2:0] delayed_tee;`
178			`wire int_pending;`
179			`wire tick_pending;`
180			`wire fp_pending;`
181	502	julius	`wire range_pending;`
182	807	julius	`reg dsx;`
183	502	julius
184	350	julius	`reg trace_trap ;`
185			`reg ex_freeze_prev;`
186			`reg sr_ted_prev;`
187			`reg dsr_te_prev;`
188			`reg dmr1_st_prev ;`
189			`reg dmr1_bt_prev ;`
190			wire dsr_te = ex_freeze_prev ? dsr_te_prev : du_dsr[`OR1200_DU_DSR_TE];
191			wire sr_ted = ex_freeze_prev ? sr_ted_prev : sr[`OR1200_SR_TED];
192			wire dmr1_st = ex_freeze_prev ? dmr1_st_prev: du_dmr1[`OR1200_DU_DMR1_ST] ;
193			wire dmr1_bt = ex_freeze_prev ? dmr1_bt_prev: du_dmr1[`OR1200_DU_DMR1_BT] ;
194
195			`//`
196			`// Simple combinatorial logic`
197			`//`
198			`assign except_started = extend_flush & except_start;`
199
200			assign except_start = (except_type != `OR1200_EXCEPT_NONE) & extend_flush;
201
202			assign int_pending = sig_int & (sr[`OR1200_SR_IEE] \|
203			(sr_we & to_sr[`OR1200_SR_IEE]))
204			`& id_pc_val & delayed_iee[2] & ~ex_freeze & ~ex_branch_taken`
205			& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_IEE]);
206
207			assign tick_pending = sig_tick & (sr[`OR1200_SR_TEE] \|
208			(sr_we & to_sr[`OR1200_SR_TEE])) & id_pc_val
209			`& delayed_tee[2] & ~ex_freeze & ~ex_branch_taken`
210			& ~ex_dslot & ~(sr_we & ~to_sr[`OR1200_SR_TEE]);
211
212			`assign fp_pending = sig_fp & fpcsr_fpee & ~ex_freeze & ~ex_branch_taken`
213			`& ~ex_dslot;`
214	502	julius
215			`ifdef OR1200_IMPL_OVE
216			assign range_pending = sig_range & sr[`OR1200_SR_OVE] & ~ex_freeze &
217			`~ex_branch_taken & ~ex_dslot;`
218			`else
219			`assign range_pending = 0;`
220			`endif
221	350	julius
222			`// Abort write into RF by load & other instructions`
223			`assign abort_ex = sig_dbuserr \| sig_dmmufault \| sig_dtlbmiss \| sig_align \|`
224			`sig_illegal \| ((du_hwbkpt \| trace_trap) & ex_pc_val`
225			`& !sr_ted & !dsr_te);`
226
227			`// abort spr read/writes`
228			`assign abort_mvspr = sig_illegal \| ((du_hwbkpt \| trace_trap) & ex_pc_val`
229			`& !sr_ted & !dsr_te) ;`
230			`assign spr_dat_ppc = wb_pc;`
231
232			`assign spr_dat_npc = ex_void ? id_pc : ex_pc;`
233
234			`//`
235			`// Order defines exception detection priority`
236			`//`
237			`assign except_trig = {`
238			ex_exceptflags[1] & ~du_dsr[`OR1200_DU_DSR_IME],
239			ex_exceptflags[0] & ~du_dsr[`OR1200_DU_DSR_IPFE],
240			ex_exceptflags[2] & ~du_dsr[`OR1200_DU_DSR_BUSEE],
241			sig_illegal & ~du_dsr[`OR1200_DU_DSR_IIE],
242			sig_align & ~du_dsr[`OR1200_DU_DSR_AE],
243			sig_dtlbmiss & ~du_dsr[`OR1200_DU_DSR_DME],
244			sig_trap & ~du_dsr[`OR1200_DU_DSR_TE],
245			sig_syscall & ~du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze,
246			sig_dmmufault & ~du_dsr[`OR1200_DU_DSR_DPFE],
247			sig_dbuserr & ~du_dsr[`OR1200_DU_DSR_BUSEE],
248	502	julius	range_pending & ~du_dsr[`OR1200_DU_DSR_RE],
249	350	julius	fp_pending & ~du_dsr[`OR1200_DU_DSR_FPE],
250			int_pending & ~du_dsr[`OR1200_DU_DSR_IE],
251			tick_pending & ~du_dsr[`OR1200_DU_DSR_TTE]
252			`};`
253
254			`wire trace_cond = !ex_freeze && !ex_void && (1'b0`
255			`ifdef OR1200_DU_DMR1_ST
256			`\|\| dmr1_st`
257			`endif
258			`ifdef OR1200_DU_DMR1_BT
259			\|\| ((branch_op != `OR1200_BRANCHOP_NOP) && (branch_op != `OR1200_BRANCHOP_RFE) && dmr1_bt)
260			`endif
261			`);`
262
263			`assign except_stop = {`
264			tick_pending & du_dsr[`OR1200_DU_DSR_TTE],
265			int_pending & du_dsr[`OR1200_DU_DSR_IE],
266			ex_exceptflags[1] & du_dsr[`OR1200_DU_DSR_IME],
267			ex_exceptflags[0] & du_dsr[`OR1200_DU_DSR_IPFE],
268			ex_exceptflags[2] & du_dsr[`OR1200_DU_DSR_BUSEE],
269			sig_illegal & du_dsr[`OR1200_DU_DSR_IIE],
270			sig_align & du_dsr[`OR1200_DU_DSR_AE],
271			sig_dtlbmiss & du_dsr[`OR1200_DU_DSR_DME],
272			sig_dmmufault & du_dsr[`OR1200_DU_DSR_DPFE],
273			sig_dbuserr & du_dsr[`OR1200_DU_DSR_BUSEE],
274	502	julius	range_pending & du_dsr[`OR1200_DU_DSR_RE],
275	350	julius	sig_trap & du_dsr[`OR1200_DU_DSR_TE],
276			fp_pending & du_dsr[`OR1200_DU_DSR_FPE],
277			sig_syscall & du_dsr[`OR1200_DU_DSR_SCE] & ~ex_freeze
278			`};`
279
280	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
281			if (rst == `OR1200_RST_VALUE) begin
282	350	julius	`trace_trap <= 1'b0 ;`
283			`end`
284			`else if (!(trace_trap && !ex_pc_val)) begin`
285			`trace_trap <= trace_cond & !dsr_te & !sr_ted ;`
286			`end`
287			`end`
288
289	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
290			if (rst == `OR1200_RST_VALUE) begin
291	350	julius	`ex_freeze_prev <= 1'b0 ;`
292			`sr_ted_prev <= 1'b0 ;`
293			`dsr_te_prev <= 1'b0 ;`
294			`dmr1_st_prev <= 1'b0 ;`
295			`dmr1_bt_prev <= 1'b0 ;`
296			`end`
297			`else begin`
298			`ex_freeze_prev <= ex_freeze ;`
299			`if (!ex_freeze_prev \|\| ex_void) begin`
300			sr_ted_prev <= sr [`OR1200_SR_TED ] ;
301			dsr_te_prev <= du_dsr [`OR1200_DU_DSR_TE ] ;
302			dmr1_st_prev <= du_dmr1[`OR1200_DU_DMR1_ST] ;
303			dmr1_bt_prev <= du_dmr1[`OR1200_DU_DMR1_BT] ;
304			`end`
305			`end`
306			`end`
307
308	353	julius	`ifdef verilator
309			`// Function to access wb_pc (for Verilator). Have to hide this from`
310			`// simulator, since functions with no inputs are not allowed in IEEE`
311			`// 1364-2001.`
312			`function [31:0] get_wb_pc;`
313			`// verilator public`
314			`get_wb_pc = wb_pc;`
315			`endfunction // get_wb_pc`
316
317			`// Function to access id_pc (for Verilator). Have to hide this from`
318			`// simulator, since functions with no inputs are not allowed in IEEE`
319			`// 1364-2001.`
320			`function [31:0] get_id_pc;`
321			`// verilator public`
322			`get_id_pc = id_pc;`
323			`endfunction // get_id_pc`
324
325			`// Function to access ex_pc (for Verilator). Have to hide this from`
326			`// simulator, since functions with no inputs are not allowed in IEEE`
327			`// 1364-2001.`
328			`function [31:0] get_ex_pc;`
329			`// verilator public`
330			`get_ex_pc = ex_pc;`
331			`endfunction // get_ex_pc`
332			`// Function to access except_type[3:0] (for Verilator). Have to hide this from`
333			`// simulator, since functions with no inputs are not allowed in IEEE`
334			`// 1364-2001.`
335			`function [3:0] get_except_type;`
336			`// verilator public`
337			`get_except_type = except_type;`
338			`endfunction // get_except_type`
339
340			`endif
341
342
343	350	julius	`//`
344			`// PC and Exception flags pipelines`
345			`//`
346	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
347			if (rst == `OR1200_RST_VALUE) begin
348	350	julius	`id_pc <= 32'd0;`
349			`id_pc_val <= 1'b0 ;`
350			`id_exceptflags <= 3'b000;`
351			`end`
352			`else if (id_flushpipe) begin`
353			`id_pc_val <= 1'b0 ;`
354			`id_exceptflags <= 3'b000;`
355			`end`
356			`else if (!id_freeze) begin`
357			`id_pc <= if_pc;`
358			`id_pc_val <= 1'b1 ;`
359			`id_exceptflags <= { sig_ibuserr, sig_itlbmiss, sig_immufault };`
360			`end`
361			`end`
362
363			`//`
364			`// delayed_iee`
365			`//`
366			`// SR[IEE] should not enable interrupts right away`
367			`// when it is restored with l.rfe. Instead delayed_iee`
368			`// together with SR[IEE] enables interrupts once`
369			`// pipeline is again ready.`
370			`//`
371	358	julius	always @(`OR1200_RST_EVENT rst or posedge clk)
372			if (rst == `OR1200_RST_VALUE)
373	350	julius	`delayed_iee <= 3'b000;`
374			else if (!sr[`OR1200_SR_IEE])
375			`delayed_iee <= 3'b000;`
376			`else`
377			`delayed_iee <= {delayed_iee[1:0], 1'b1};`
378
379			`//`
380			`// delayed_tee`
381			`//`
382			`// SR[TEE] should not enable tick exceptions right away`
383			`// when it is restored with l.rfe. Instead delayed_tee`
384			`// together with SR[TEE] enables tick exceptions once`
385			`// pipeline is again ready.`
386			`//`
387	358	julius	always @(`OR1200_RST_EVENT rst or posedge clk)
388			if (rst == `OR1200_RST_VALUE)
389	350	julius	`delayed_tee <= 3'b000;`
390			else if (!sr[`OR1200_SR_TEE])
391			`delayed_tee <= 3'b000;`
392			`else`
393			`delayed_tee <= {delayed_tee[1:0], 1'b1};`
394
395			`//`
396			`// PC and Exception flags pipelines`
397			`//`
398	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
399			if (rst == `OR1200_RST_VALUE) begin
400	350	julius	`ex_dslot <= 1'b0;`
401			`ex_pc <= 32'd0;`
402			`ex_pc_val <= 1'b0 ;`
403			`ex_exceptflags <= 3'b000;`
404			`delayed1_ex_dslot <= 1'b0;`
405			`delayed2_ex_dslot <= 1'b0;`
406			`end`
407			`else if (ex_flushpipe) begin`
408			`ex_dslot <= 1'b0;`
409			`ex_pc_val <= 1'b0 ;`
410			`ex_exceptflags <= 3'b000;`
411			`delayed1_ex_dslot <= 1'b0;`
412			`delayed2_ex_dslot <= 1'b0;`
413			`end`
414			`else if (!ex_freeze & id_freeze) begin`
415			`ex_dslot <= 1'b0;`
416			`ex_pc <= id_pc;`
417			`ex_pc_val <= id_pc_val ;`
418			`ex_exceptflags <= 3'b000;`
419			`delayed1_ex_dslot <= ex_dslot;`
420			`delayed2_ex_dslot <= delayed1_ex_dslot;`
421			`end`
422			`else if (!ex_freeze) begin`
423			`ex_dslot <= ex_branch_taken;`
424			`ex_pc <= id_pc;`
425			`ex_pc_val <= id_pc_val ;`
426			`ex_exceptflags <= id_exceptflags;`
427			`delayed1_ex_dslot <= ex_dslot;`
428			`delayed2_ex_dslot <= delayed1_ex_dslot;`
429			`end`
430			`end`
431
432			`//`
433			`// PC and Exception flags pipelines`
434			`//`
435	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
436			if (rst == `OR1200_RST_VALUE) begin
437	350	julius	`wb_pc <= 32'd0;`
438			`dl_pc <= 32'd0;`
439			`end`
440			`else if (!wb_freeze) begin`
441			`wb_pc <= ex_pc;`
442			`dl_pc <= wb_pc;`
443			`end`
444			`end`
445
446			`//`
447			`// We have started execution of exception handler:`
448			`// 1. Asserted for 3 clock cycles`
449			`// 2. Don't execute any instruction that is still in pipeline and is not part of exception handler`
450			`//`
451			`assign except_flushpipe = \|except_trig & ~\|state;`
452
453			`//`
454			`// Exception FSM that sequences execution of exception handler`
455			`//`
456			`// except_type signals which exception handler we start fetching in:`
457			`// 1. Asserted in next clock cycle after exception is recognized`
458			`//`
459	358	julius	always @(posedge clk or `OR1200_RST_EVENT rst) begin
460			if (rst == `OR1200_RST_VALUE) begin
461	350	julius	state <= `OR1200_EXCEPTFSM_IDLE;
462			except_type <= `OR1200_EXCEPT_NONE;
463			`extend_flush <= 1'b0;`
464			`epcr <= 32'b0;`
465			`eear <= 32'b0;`
466			esr <= {2'h1, {`OR1200_SR_WIDTH-3{1'b0}}, 1'b1};
467			`extend_flush_last <= 1'b0;`
468	807	julius	`dsx <= 1'b0;`
469	350	julius	`end`
470			`else begin`
471			`ifdef OR1200_CASE_DEFAULT
472			`case (state) // synopsys parallel_case`
473			`else
474			`case (state) // synopsys full_case parallel_case`
475			`endif
476			`OR1200_EXCEPTFSM_IDLE:
477			`if (except_flushpipe) begin`
478			state <= `OR1200_EXCEPTFSM_FLU1;
479			`extend_flush <= 1'b1;`
480			`esr <= sr_we ? to_sr : sr;`
481	363	julius	`casez (except_trig)`
482	350	julius	`ifdef OR1200_EXCEPT_ITLBMISS
483	363	julius	`14'b1?_????_????_????: begin`
484	350	julius	except_type <= `OR1200_EXCEPT_ITLBMISS;
485			`eear <= ex_dslot ?`
486			`ex_pc : ex_pc;`
487			`epcr <= ex_dslot ?`
488			`wb_pc : ex_pc;`
489	807	julius	`dsx <= ex_dslot;`
490	350	julius	`end`
491			`endif
492			`ifdef OR1200_EXCEPT_IPF
493	363	julius	`14'b01_????_????_????: begin`
494	350	julius	except_type <= `OR1200_EXCEPT_IPF;
495			`eear <= ex_dslot ?`
496			`ex_pc : delayed1_ex_dslot ?`
497			`id_pc : delayed2_ex_dslot ?`
498			`id_pc : id_pc;`
499			`epcr <= ex_dslot ?`
500			`wb_pc : delayed1_ex_dslot ?`

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_except.v] - Blame information for rev 833