OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_fpu_pre_norm_div.v] - Blame information for rev 479

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 350 julius 
//////////////////////////////////////////////////////////////////////
2 
////                                                              ////
3 
////  or1200_fpu_pre_norm_div                                     ////
4 
////                                                              ////
5 
////  This file is part of the OpenRISC 1200 project              ////
6 
////  http://opencores.org/project,or1k                           ////
7 
////                                                              ////
8 
////  Description                                                 ////
9 
////  pre-normalization entity for the division unit              ////
10 
////                                                              ////
11 
////  To Do:                                                      ////
12 
////                                                              ////
13 
////                                                              ////
14 
////  Author(s):                                                  ////
15 
////      - Original design (FPU100) -                            ////
16 
////        Jidan Al-eryani, jidan@gmx.net                        ////
17 
////      - Conv. to Verilog and inclusion in OR1200 -            ////
18 
////        Julius Baxter, julius@opencores.org                   ////
19 
////                                                              ////
20 
//////////////////////////////////////////////////////////////////////
21 
//
22 
//  Copyright (C) 2006, 2010
23 
//
24 
//      This source file may be used and distributed without
25 
//      restriction provided that this copyright statement is not
26 
//      removed from the file and that any derivative work contains
27 
//      the original copyright notice and the associated disclaimer.
28 
//
29 
//              THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
30 
//      EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
31 
//      TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
32 
//      FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
33 
//      OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
34 
//      INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 
//      (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
36 
//      GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
37 
//      BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
38 
//      LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
39 
//      (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40 
//      OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 
//      POSSIBILITY OF SUCH DAMAGE.
42 
//
43 
 
44 
module or1200_fpu_pre_norm_div
45 
  (
46 
   clk_i,
47 
   opa_i,
48 
   opb_i,
49 
   exp_10_o,
50 
   dvdnd_50_o,
51 
   dvsor_27_o
52 
   );
53 
 
54 
 
55 
   parameter FP_WIDTH = 32;
56 
   parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
57 
   parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
58 
   parameter FRAC_WIDTH = 23;
59 
   parameter EXP_WIDTH = 8;
60 
   parameter ZERO_VECTOR = 31'd0;
61 
   parameter INF = 31'b1111111100000000000000000000000;
62 
   parameter QNAN = 31'b1111111110000000000000000000000;
63 
   parameter SNAN = 31'b1111111100000000000000000000001;
64 
 
65 
   input clk_i;
66 
   input [FP_WIDTH-1:0] opa_i;
67 
   input [FP_WIDTH-1:0] opb_i;
68 
   output reg [EXP_WIDTH+1:0] exp_10_o;
69 
   output [2*(FRAC_WIDTH+2)-1:0] dvdnd_50_o;
70 
   output [FRAC_WIDTH+3:0]        dvsor_27_o;
71 
 
72 
 
73 
   wire [EXP_WIDTH-1:0]   s_expa;
74 
   wire [EXP_WIDTH-1:0]   s_expb;
75 
   wire [FRAC_WIDTH-1:0]          s_fracta;
76 
   wire [FRAC_WIDTH-1:0]          s_fractb;
77 
   wire [2*(FRAC_WIDTH+2)-1:0]    s_dvdnd_50_o;
78 
   wire [FRAC_WIDTH+3:0]          s_dvsor_27_o;
79 
   reg [5:0]                      s_dvd_zeros;
80 
   reg [5:0]                      s_div_zeros;
81 
   reg [EXP_WIDTH+1:0]            s_exp_10_o;
82 
 
83 
   reg [EXP_WIDTH+1:0]            s_expa_in;
84 
   reg [EXP_WIDTH+1:0]            s_expb_in;
85 
   wire                          s_opa_dn, s_opb_dn;
86 
 
87 
   wire [FRAC_WIDTH:0]            s_fracta_24;
88 
   wire [FRAC_WIDTH:0]            s_fractb_24;
89 
 
90 
 
91 
   assign s_expa = opa_i[30:23];
92 
   assign s_expb = opb_i[30:23];
93 
   assign s_fracta = opa_i[22:0];
94 
   assign s_fractb = opb_i[22:0];
95 
   assign dvdnd_50_o = s_dvdnd_50_o;
96 
   assign dvsor_27_o    = s_dvsor_27_o;
97 
 
98 
   // Output Register
99 
   always @(posedge clk_i)
100 
     exp_10_o <= s_exp_10_o;
101 
 
102 
   assign s_opa_dn = !(|s_expa);
103 
   assign s_opb_dn = !(|s_expb);
104 
 
105 
   assign s_fracta_24 = {!s_opa_dn,s_fracta};
106 
   assign s_fractb_24 = {!s_opb_dn,s_fractb};
107 
 
108 
 
109 
   // count leading zeros
110 
   //s_dvd_zeros <= count_l_zeros( s_fracta_24 );
111 
   always @(s_fracta_24)
112 364 julius 
     casez(s_fracta_24) // synopsys full_case parallel_case
113 
       24'b1???????????????????????: s_dvd_zeros = 0;
114 
       24'b01??????????????????????: s_dvd_zeros = 1;
115 
       24'b001?????????????????????: s_dvd_zeros = 2;
116 
       24'b0001????????????????????: s_dvd_zeros = 3;
117 
       24'b00001???????????????????: s_dvd_zeros = 4;
118 
       24'b000001??????????????????: s_dvd_zeros = 5;
119 
       24'b0000001?????????????????: s_dvd_zeros = 6;
120 
       24'b00000001????????????????: s_dvd_zeros = 7;
121 
       24'b000000001???????????????: s_dvd_zeros = 8;
122 
       24'b0000000001??????????????: s_dvd_zeros = 9;
123 
       24'b00000000001?????????????: s_dvd_zeros = 10;
124 
       24'b000000000001????????????: s_dvd_zeros = 11;
125 
       24'b0000000000001???????????: s_dvd_zeros = 12;
126 
       24'b00000000000001??????????: s_dvd_zeros = 13;
127 
       24'b000000000000001?????????: s_dvd_zeros = 14;
128 
       24'b0000000000000001????????: s_dvd_zeros = 15;
129 
       24'b00000000000000001???????: s_dvd_zeros = 16;
130 
       24'b000000000000000001??????: s_dvd_zeros = 17;
131 
       24'b0000000000000000001?????: s_dvd_zeros = 18;
132 
       24'b00000000000000000001????: s_dvd_zeros = 19;
133 
       24'b000000000000000000001???: s_dvd_zeros = 20;
134 
       24'b0000000000000000000001??: s_dvd_zeros = 21;
135 
       24'b00000000000000000000001?: s_dvd_zeros = 22;
136 
       24'b000000000000000000000001: s_dvd_zeros = 23;
137 
       24'b000000000000000000000000: s_dvd_zeros = 24;
138 350 julius 
     endcase
139 
 
140 
   //s_div_zeros <= count_l_zeros( s_fractb_24 );
141 
   always @(s_fractb_24)
142 364 julius 
     casez(s_fractb_24) // synopsys full_case parallel_case
143 
       24'b1???????????????????????: s_div_zeros = 0;
144 
       24'b01??????????????????????: s_div_zeros = 1;
145 
       24'b001?????????????????????: s_div_zeros = 2;
146 
       24'b0001????????????????????: s_div_zeros = 3;
147 
       24'b00001???????????????????: s_div_zeros = 4;
148 
       24'b000001??????????????????: s_div_zeros = 5;
149 
       24'b0000001?????????????????: s_div_zeros = 6;
150 
       24'b00000001????????????????: s_div_zeros = 7;
151 
       24'b000000001???????????????: s_div_zeros = 8;
152 
       24'b0000000001??????????????: s_div_zeros = 9;
153 
       24'b00000000001?????????????: s_div_zeros = 10;
154 
       24'b000000000001????????????: s_div_zeros = 11;
155 
       24'b0000000000001???????????: s_div_zeros = 12;
156 
       24'b00000000000001??????????: s_div_zeros = 13;
157 
       24'b000000000000001?????????: s_div_zeros = 14;
158 
       24'b0000000000000001????????: s_div_zeros = 15;
159 
       24'b00000000000000001???????: s_div_zeros = 16;
160 
       24'b000000000000000001??????: s_div_zeros = 17;
161 
       24'b0000000000000000001?????: s_div_zeros = 18;
162 
       24'b00000000000000000001????: s_div_zeros = 19;
163 
       24'b000000000000000000001???: s_div_zeros = 20;
164 
       24'b0000000000000000000001??: s_div_zeros = 21;
165 
       24'b00000000000000000000001?: s_div_zeros = 22;
166 
       24'b000000000000000000000001: s_div_zeros = 23;
167 
       24'b000000000000000000000000: s_div_zeros = 24;
168 350 julius 
     endcase
169 
 
170 
   // left-shift the dividend and divisor
171 
   wire [FRAC_WIDTH:0]            fracta_lshift_intermediate;
172 
   wire [FRAC_WIDTH:0]            fractb_lshift_intermediate;
173 
   assign fracta_lshift_intermediate = s_fracta_24 << s_dvd_zeros;
174 
   assign fractb_lshift_intermediate = s_fractb_24 << s_div_zeros;
175 
 
176 
   assign s_dvdnd_50_o = {fracta_lshift_intermediate,26'd0};
177 
 
178 
   assign s_dvsor_27_o = {3'd0,fractb_lshift_intermediate};
179 
 
180 
   always @(posedge clk_i)
181 
     begin
182 
        // pre-calculate exponent
183 
        s_expa_in <= {2'd0,s_expa} + {9'd0,s_opa_dn};
184 
        s_expb_in <= {2'd0,s_expb} + {9'd0,s_opb_dn};
185 
        s_exp_10_o <= s_expa_in - s_expb_in + 10'b0001111111 -
186 
                      {4'd0,s_dvd_zeros} + {4'd0,s_div_zeros};
187 
     end
188 
 
189 
 
190 
endmodule // or1200_fpu_pre_norm_div
191 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.