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[/] [openrisc/] [trunk/] [orpsocv2/] [rtl/] [verilog/] [or1200/] [or1200_immu_tlb.v] - Blame information for rev 361

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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  OR1200's Instruction TLB                                    ////
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////                                                              ////
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////  This file is part of the OpenRISC 1200 project              ////
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////  http://www.opencores.org/cores/or1k/                        ////
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////                                                              ////
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////  Description                                                 ////
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////  Instantiation of ITLB.                                      ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - make it smaller and faster                               ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Damjan Lampret, lampret@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: or1200_immu_tlb.v,v $
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// Revision 2.0  2010/06/30 11:00:00  ORSoC
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// Minor update: 
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// Bugs fixed, coding style changed. 
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//
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// Revision 1.9  2004/06/08 18:17:36  lampret
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// Non-functional changes. Coding style fixes.
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//
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// Revision 1.8  2004/04/05 08:29:57  lampret
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// Merged branch_qmem into main tree.
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//
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// Revision 1.6.4.1  2003/12/09 11:46:48  simons
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// Mbist nameing changed, Artisan ram instance signal names fixed, some synthesis waning fixed.
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//
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// Revision 1.6  2002/10/28 16:34:32  mohor
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// RAMs wrong connected to the BIST scan chain.
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//
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// Revision 1.5  2002/10/17 20:04:40  lampret
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// Added BIST scan. Special VS RAMs need to be used to implement BIST.
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//
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// Revision 1.4  2002/08/14 06:23:50  lampret
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// Disabled ITLB translation when 1) doing access to ITLB SPRs or 2) crossing page. This modification was tested only with parts of IMMU test - remaining test cases needs to be run.
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//
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// Revision 1.3  2002/02/11 04:33:17  lampret
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// Speed optimizations (removed duplicate _cyc_ and _stb_). Fixed D/IMMU cache-inhibit attr.
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//
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// Revision 1.2  2002/01/28 01:16:00  lampret
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// Changed 'void' nop-ops instead of insn[0] to use insn[16]. Debug unit stalls the tick timer. Prepared new flag generation for add and and insns. Blocked DC/IC while they are turned off. Fixed I/D MMU SPRs layout except WAYs. TODO: smart IC invalidate, l.j 2 and TLB ways.
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//
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// Revision 1.1  2002/01/03 08:16:15  lampret
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// New prefixes for RTL files, prefixed module names. Updated cache controllers and MMUs.
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//
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// Revision 1.8  2001/10/21 17:57:16  lampret
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// Removed params from generic_XX.v. Added translate_off/on in sprs.v and id.v. Removed spr_addr from dc.v and ic.v. Fixed CR+LF.
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//
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// Revision 1.7  2001/10/14 13:12:09  lampret
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// MP3 version.
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//
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// Revision 1.1.1.1  2001/10/06 10:18:36  igorm
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// no message
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//
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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`include "or1200_defines.v"
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//
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// Insn TLB
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//
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module or1200_immu_tlb(
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        // Rst and clk
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        clk, rst,
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        // I/F for translation
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        tlb_en, vaddr, hit, ppn, uxe, sxe, ci,
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`ifdef OR1200_BIST
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        // RAM BIST
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        mbist_si_i, mbist_so_o, mbist_ctrl_i,
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`endif
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        // SPR access
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        spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o
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);
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parameter dw = `OR1200_OPERAND_WIDTH;
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parameter aw = `OR1200_OPERAND_WIDTH;
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//
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// I/O
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//
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//
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// Clock and reset
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//
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input                           clk;
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input                           rst;
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//
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// I/F for translation
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//
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input                           tlb_en;
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input   [aw-1:0]         vaddr;
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output                          hit;
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output  [31:`OR1200_IMMU_PS]    ppn;
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output                          uxe;
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output                          sxe;
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output                          ci;
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`ifdef OR1200_BIST
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//
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// RAM BIST
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//
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input mbist_si_i;
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input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
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output mbist_so_o;
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`endif
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//
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// SPR access
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//
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input                           spr_cs;
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input                           spr_write;
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input   [31:0]                   spr_addr;
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input   [31:0]                   spr_dat_i;
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output  [31:0]                   spr_dat_o;
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//
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// Internal wires and regs
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//
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wire    [`OR1200_ITLB_TAG]      vpn;
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wire                            v;
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wire    [`OR1200_ITLB_INDXW-1:0] tlb_index;
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wire                            tlb_mr_en;
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wire                            tlb_mr_we;
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wire    [`OR1200_ITLBMRW-1:0]    tlb_mr_ram_in;
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wire    [`OR1200_ITLBMRW-1:0]    tlb_mr_ram_out;
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wire                            tlb_tr_en;
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wire                            tlb_tr_we;
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wire    [`OR1200_ITLBTRW-1:0]    tlb_tr_ram_in;
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wire    [`OR1200_ITLBTRW-1:0]    tlb_tr_ram_out;
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// BIST
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`ifdef OR1200_BIST
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wire                        itlb_mr_ram_si;
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wire                        itlb_mr_ram_so;
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wire                        itlb_tr_ram_si;
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wire                        itlb_tr_ram_so;
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`endif
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//
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// Implemented bits inside match and translate registers
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//
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// itlbwYmrX: vpn 31-19  v 0
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// itlbwYtrX: ppn 31-13  uxe 7  sxe 6
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//
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// itlb memory width:
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// 19 bits for ppn
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// 13 bits for vpn
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// 1 bit for valid
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// 2 bits for protection
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// 1 bit for cache inhibit
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//
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// Enable for Match registers
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//
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assign tlb_mr_en = tlb_en | (spr_cs & !spr_addr[`OR1200_ITLB_TM_ADDR]);
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//
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// Write enable for Match registers
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//
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assign tlb_mr_we = spr_cs & spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR];
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//
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// Enable for Translate registers
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//
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assign tlb_tr_en = tlb_en | (spr_cs & spr_addr[`OR1200_ITLB_TM_ADDR]);
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//
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// Write enable for Translate registers
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//
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assign tlb_tr_we = spr_cs & spr_write & spr_addr[`OR1200_ITLB_TM_ADDR];
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//
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// Output to SPRS unit
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//
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assign spr_dat_o = (!spr_write & !spr_addr[`OR1200_ITLB_TM_ADDR]) ?
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            {vpn, tlb_index, {`OR1200_ITLB_TAGW-7{1'b0}}, 1'b0, 5'b00000, v} :
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                (!spr_write & spr_addr[`OR1200_ITLB_TM_ADDR]) ?
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                        {ppn, {`OR1200_IMMU_PS-8{1'b0}}, uxe, sxe, {4{1'b0}}, ci, 1'b0} :
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                        32'h00000000;
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//
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// Assign outputs from Match registers
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//
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assign {vpn, v} = tlb_mr_ram_out;
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//
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// Assign to Match registers inputs
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//
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assign tlb_mr_ram_in = {spr_dat_i[`OR1200_ITLB_TAG], spr_dat_i[`OR1200_ITLBMR_V_BITS]};
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//
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// Assign outputs from Translate registers
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//
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assign {ppn, uxe, sxe, ci} = tlb_tr_ram_out;
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//
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// Assign to Translate registers inputs
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//
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assign tlb_tr_ram_in = {spr_dat_i[31:`OR1200_IMMU_PS],
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                        spr_dat_i[`OR1200_ITLBTR_UXE_BITS],
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                        spr_dat_i[`OR1200_ITLBTR_SXE_BITS],
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                        spr_dat_i[`OR1200_ITLBTR_CI_BITS]};
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//
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// Generate hit
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//
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assign hit = (vpn == vaddr[`OR1200_ITLB_TAG]) & v;
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//
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// TLB index is normally vaddr[18:13]. If it is SPR access then index is
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// spr_addr[5:0].
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//
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assign tlb_index = spr_cs ? spr_addr[`OR1200_ITLB_INDXW-1:0] : vaddr[`OR1200_ITLB_INDX];
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`ifdef OR1200_BIST
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assign itlb_mr_ram_si = mbist_si_i;
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assign itlb_tr_ram_si = itlb_mr_ram_so;
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assign mbist_so_o = itlb_tr_ram_so;
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`endif
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//
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// Instantiation of ITLB Match Registers
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//
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   or1200_spram #
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     (
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      .aw(6),
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      .dw(14)
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      )
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   itlb_mr_ram
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     (
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      .clk(clk),
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`ifdef OR1200_BIST
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      // RAM BIST
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      .mbist_si_i(itlb_mr_ram_si),
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      .mbist_so_o(itlb_mr_ram_so),
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      .mbist_ctrl_i(mbist_ctrl_i),
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`endif
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      .ce(tlb_mr_en),
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      .we(tlb_mr_we),
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      //.oe(1'b1),
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      .addr(tlb_index),
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      .di(tlb_mr_ram_in),
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      .doq(tlb_mr_ram_out)
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      );
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//
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// Instantiation of ITLB Translate Registers
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//
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   or1200_spram #
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     (
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      .aw(6),
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      .dw(22)
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      )
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   itlb_tr_ram
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     (
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      .clk(clk),
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`ifdef OR1200_BIST
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      // RAM BIST
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      .mbist_si_i(itlb_tr_ram_si),
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      .mbist_so_o(itlb_tr_ram_so),
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      .mbist_ctrl_i(mbist_ctrl_i),
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`endif
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      .ce(tlb_tr_en),
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      .we(tlb_tr_we),
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      //.oe(1'b1),
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      .addr(tlb_index),
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      .di(tlb_tr_ram_in),
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      .doq(tlb_tr_ram_out)
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      );
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endmodule

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